A printed circuit board, a semiconductor module and a method for manufacturing the same suitable for implementing a nitride-based semiconductor device

Abstract

The present disclosure provides a semiconductor module including a semiconductor device that is removably press-fitted in a cavity formed in a printed circuit board, a printed circuit board suitable for implementing the semiconductor device, and a method for manufacturing the same. The semiconductor device and the cavity of the printed circuit board can cooperate with each other and act as an electrical plug and an electrical socket, respectively. Soldering the semiconductor device on the printed circuit board can be eliminated. Therefore, the packaging process can be more flexible, and the reliability problem of the solder joint can be eliminated. In addition, a heat sink can be installed on the top and / or bottom of the semiconductor device after the semiconductor device is received in the cavity of the printed circuit board. The heat dissipation efficiency can be greatly enhanced.

Description

Technical Field

[0001] The present invention generally relates to an electronic device package. More particularly, the present invention relates to a nitride-based semiconductor module including a nitride semiconductor device mounted in a printed circuit board (PCB) and a method of manufacturing the PCB and the semiconductor device. Background Art

[0002] Nitride semiconductor devices, such as gallium nitride (GaN) devices, are prevalent in the development of semiconductor technologies and devices, such as high-power switching and high-frequency applications. Typically, nitride semiconductor devices are packaged in leaded or leadless packages and assembled in a printed circuit board (PCB) using either through-hole mounting or surface-mounting. Both processes require the use of solder to provide an electrical connection between the component and the PCB. Solder joints may degrade and have reliability issues during power cycling due to mismatches in the coefficient of thermal expansion between the solder joint and the PCB. For high-power switching and high-frequency applications, the heat dissipation path through the PCB is insufficient to dissipate the heat generated by the device. In addition, the leads of the leaded package have parasitic impedance and reactance, which limits high-frequency performance. Therefore, there is a need to improve the packaging design of nitride semiconductor devices so that they can be more flexible for mass production and more reliable. Summary of the invention

[0003] An object of the present disclosure is to provide an electronic package and a method for manufacturing the same that can solve the above-mentioned reliability and parasitic impedance and reactance problems.

[0004] According to one aspect of the present application, a nitride-based semiconductor module including a nitride-based device removably press-fitted in a cavity formed in a printed circuit board and a method for manufacturing the same are provided. The nitride-based semiconductor device and the cavity of the printed circuit board can cooperate with each other and act as an electrical plug and an electrical socket, respectively. Soldering the nitride-based device on the printed circuit board can be eliminated. Therefore, the packaging process can be more flexible, and the reliability problem of the solder joint can be eliminated. In addition, a heat sink can be installed on the top and / or bottom of the semiconductor device after the semiconductor device is received in the cavity of the printed circuit board. The heat dissipation efficiency can be greatly enhanced.

[0005] According to another aspect of the present application, a semiconductor device includes: a nitride-based chip having an active surface formed with a plurality of conductive pads and a passive surface opposite to the active surface; a housing enclosing the nitride-based chip and having a top surface, a bottom surface, and a plurality of side surfaces; and a plurality of conductive paths configured to electrically connect the nitride-based chip to an external system, each conductive path having a plurality of external conductive contacts exposed on the plurality of side surfaces and extending from the top surface of the housing to the bottom surface along the plurality of side surfaces. The housing has a shape that is substantially conformal to the shape of the nitride-based chip, thereby achieving chip-scale packaging. The plurality of external conductive contacts can be electrically coupled to a plurality of internal conductive leads in a cavity of a printed circuit board, so that the nitride-based semiconductor device can act as an electrical plug, thereby mating with an electrical socket acted as by the cavity of the printed circuit board.

[0006] According to another aspect of the present application, a printed circuit board includes: an upper surface; a lower surface opposite to the upper surface; one or more substrate layers arranged between the upper surface and the lower surface; a cavity having one or more inner side walls substantially perpendicular to the upper surface and the lower surface; and a plurality of internal conductive leads fixed on and extending from the upper surface of the printed circuit board and bent into the cavity. The cavity of the printed circuit board has a shape conformal to the shape of the housing of the nitride-based semiconductor device, so that the nitride-based semiconductor device can be removably press-fitted into the cavity of the printed circuit board. The plurality of internal conductive leads in the cavity of the printed circuit board are configured to elastically contact the plurality of external conductive contacts of the nitride-based semiconductor device and can be electrically coupled thereto, so that the cavity can act as an electrical socket, thereby mating with an electrical plug acted as by the nitride-based semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Preferred embodiments of the present disclosure are described in more detail below with reference to the accompanying drawings, in which:

[0008] Figure 1A is a simplified top view of a semiconductor module according to an embodiment of the present disclosure, Figure 1B It is along Figure 1A A cross-sectional view of the semiconductor module taken along the cutting line AA' in FIG.

[0009] Figure 2 is a cross-sectional view of an electronic assembly with a heat sink installed according to an embodiment of the present application;

[0010] Figure 3A is a simplified top view of a semiconductor module according to another embodiment of the present invention, Figure 3B It is along Figure 3A A cross-sectional view taken along the cutting line A-A' in FIG.

[0011] Figure 4is a cross-sectional view of an electronic assembly with a heat sink installed according to another embodiment of the present application;

[0012] Figure 5A Show Figure 1A For more details of the top view of the semiconductor device, Figure 5B Show Figure 1B More details of the cross-sectional view of the semiconductor device in FIG.

[0013] Fig. 6A is a top view of a semiconductor device according to another embodiment of the present invention, Figure 6B It is along Fig. 6A A cross-sectional view taken along the cutting line A-A' in FIG.

[0014] Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 7E , Figure 7F , Figure 7G and Figure 7H Describes the use of multiple Figure 5A and Figure 5B The steps of the method of the semiconductor device of the embodiment;

[0015] Fig. 8A , Figure 8B , Figure 8C , Fig.8D , Fig. 8E , Figure 8F , Figure 8G and Figure 8H Describes the use of multiple Fig. 6A and Figure 6B The steps of the method of the semiconductor device of the embodiment;

[0016] Fig. 9A Show Figure 1A For more details of the top view of the printed circuit board, Fig. 9B Show Figure 1B More details of the cross-sectional view of the printed circuit board;

[0017] Fig. 10A and Fig. 10B Shows how semiconductor devices are assembled to Fig. 9A and Fig. 9B In the printed circuit board;

[0018] Fig.11A , Fig. 11B and Fig. 11C Describe the use of manufacturing Fig. 9A and Fig. 9B The steps of the method of printing a circuit board of an embodiment;

[0019] Fig. 12A Show Figure 3A For more details of the top view of the printed circuit board, Fig. 12B Show Figure 3B More details of the cross-sectional view of the printed circuit board;

[0020] Fig.13A and Fig. 13B Shows how semiconductor devices are assembled to Fig. 12A and 12B In the printed circuit board;

[0021] Fig.14A , Fig. 14B and Fig. 14C Describe the use of manufacturing Fig. 12A and Fig. 12B The steps of an embodiment of a method of printing a circuit board are as follows.

[0022] It should be noted that the various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. DETAILED DESCRIPTION

[0023] Preferred embodiments of the present disclosure will be readily understood from the following detailed description made in conjunction with the accompanying drawings. Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar components.

[0024] Spatial descriptors such as "above," "below," "upward," "left," "right," "downward," "first," "second," "vertical," "horizontal," "side," "higher," "lower," "upper," "above," "below," etc. are specified relative to a particular component or group of components or a particular plane of a component or group of components for the orientation of a component as shown in the associated figure. It should be understood that the spatial descriptors used herein are for illustrative purposes only and that actual embodiments of the structures described herein may be spatially arranged in any orientation or manner, with the proviso that the advantages of the embodiments of the present disclosure will not deviate from such arrangements.

[0025] Furthermore, it should be noted that in an actual device, due to device manufacturing conditions, the actual shapes of the various structures depicted as approximately rectangular may be curved, have rounded edges, have slightly uneven thicknesses, etc. The use of straight lines and right angles is merely for convenience in representing layers and features.

[0026] In the following description, a semiconductor module including a semiconductor device removably press-fitted in a printed circuit board and a method for manufacturing the same, etc. are described as preferred examples. It will be clear to those skilled in the art that modifications including additions and / or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the present disclosure is written to enable those skilled in the art to practice the teachings herein without undue experimentation.

[0027] Figure 1A is a simplified top view of a semiconductor module 10A according to an embodiment of the present disclosure, Figure 1B It is along Figure 1A FIG. 1 is a cross-sectional view of the semiconductor module 10A taken along the cutting line AA′ in FIG.

[0028] The semiconductor module 10A may include a printed circuit board 50A. The printed circuit board 50A may be a multilayer board having a conductive layer that is patterned and formed between substrate layers that may be fiberglass or other insulating substrate layers. The printed circuit board 50A may have a cavity 510A and a plurality of internal conductive leads 520 that extend from a surface 501 of the printed circuit board 50A and bend into the cavity 510A.

[0029] The semiconductor device 30A may have a housing 31A and a plurality of external conductive contacts 341 exposed on a plurality of side surfaces 303 of the housing 31A.

[0030] The cavity 510A of the printed circuit board 50A and the housing 31A of the semiconductor device 30A may have shapes that conform to each other so that the semiconductor device 30A may be removably press-fitted into the cavity 510A of the printed circuit board 50A.

[0031] The semiconductor's multiple external conductive contacts 341 may be configured to resiliently contact and electrically couple with multiple internal conductive leads 520 in the cavity 510A of the printed circuit board 50A, so that the semiconductor device 30A may act as an electrical plug, mating with the cavity 510A acting as an electrical socket.

[0032] refer to Figure 2 In some embodiments, after the semiconductor device 30A is assembled into the cavity 510A of the printed circuit board 50A, a first heat sink 910A may be mounted on the top surface of the semiconductor device 30A and a second heat sink 920A may be mounted on the bottom surface of the semiconductor device 30A.

[0033] Figure 3A is a simplified top view of a semiconductor module 10B according to another embodiment of the present invention, Figure 3B It is along Figure 3A Cross-sectional view taken along the cutting line AA' in FIG. Figure 3A-3B The semiconductor module 10B is similar to Figure 1A-1B The semiconductor module 10A of FIG. 1 is a semiconductor module 10A of FIG. 1 , but the semiconductor module 10B includes a printed circuit board 50B having a cavity 510B, the cavity having a blind hole structure. For simplicity, Figure 3A-3B and Figure 1A-1B The same elements in the drawings have the same reference numerals and are not described in further detail.

[0034] refer to Figure 4 In some embodiments, after semiconductor device 30A is assembled into cavity 510B of printed circuit board 50B, heat sink 910B may be mounted on a top surface of the semiconductor device.

[0035] It should be understood that the semiconductor module may further include other electronic components mounted to the printed circuit board. The other electronic components may include different types of semiconductors or IC devices, transistors, diodes, passive electronic components such as resistors, capacitors, resistor packs, inductors, transformers, and other components such as connectors, jumper wires, posts, handles, guides, mechanical brackets, and mechanical devices.

[0036] Figure 5A Show Figure 1A For more details of the top view of the semiconductor device 30A, Figure 5B More details of a cross-sectional view of semiconductor device 30A are shown.

[0037] The semiconductor device 30A may include a semiconductor chip 310 , a case 31A enclosing the semiconductor chip 310 and configured to protect the semiconductor chip, and a plurality of conductive paths 32A configured to electrically connect the semiconductor chip 310 to an external system (not shown).

[0038] The semiconductor chip may have an active surface 311 on which a plurality of conductive pads 313 are formed; and an inactive surface 312 opposite to the active surface.

[0039] In various embodiments, the semiconductor chip 310 may be, for example but not limited to, a nitride-based chip including a plurality of semiconductor layers, and the semiconductor layers may include materials such as gallium nitride (GaN), aluminum gallium nitride (AlGaN), silicon, or fluorine ions.

[0040] The housing 31A may have a top surface 301, a bottom surface 302, and a plurality of side surfaces 303. The housing 31A may include an insulating layer 320 positioned below the semiconductor chip 310 and an encapsulation layer 330 surrounding the semiconductor chip 310. The housing 31A may be generally formed in a shape generally conformal to the shape of the semiconductor chip 310 to achieve chip-scale packaging.

[0041] The insulating layer 320 may have a first surface 321 facing the semiconductor chip 310 and a second surface 322 opposite to the first surface 321. The first surface 321 of the insulating layer 320 may be in contact with the active surface 311 of the semiconductor chip 310.

[0042] The encapsulation layer 330 may have a first surface 331 adjacent to the inactive surface 312 of the semiconductor chip 310 , and a second surface 332 opposite to the first surface 331 and adjacent to the second surface 322 of the insulation layer 320 .

[0043] The first surface 331 of the encapsulation layer 330 may be substantially coplanar with the inactive surface 312 of the semiconductor chip 310. Thus, the first surface 331 of the encapsulation layer 330 and the inactive surface 312 of the semiconductor chip 310 form a top surface of the semiconductor device 30A.

[0044] The second surface 332 of the encapsulation layer 330 may be substantially coplanar with the second surface 322 of the insulating layer 320. Thus, the second surface 332 of the encapsulation layer 330 and the second surface 322 of the insulating layer 320 form a bottom surface of the semiconductor device 30A.

[0045] In some embodiments, the plurality of side surfaces 303 may be substantially perpendicular to the active surface 311 of the semiconductor chip 310. That is, the side surfaces 303 may substantially form an angle of 90° with the active surface 311 of the semiconductor chip 310. In some embodiments, the side surfaces 303 may be inclined and form an angle α with the active surface 311 of the semiconductor chip 310. The angle α may be in the range of approximately 90° to approximately 135°.

[0046] The plurality of conductive paths 32A may include a plurality of external conductive contacts 341 that are exposed on and extend along the side surface 303 of the housing 31A to provide electrical connection to an external circuit (not shown). In some embodiments, the plurality of external conductive contacts 341 may extend along the entire height of the side surface 303 from the bottom surface 302 to the top surface 301 of the housing 31A.

[0047] In some embodiments, the semiconductor device 310 may include one or more seed layers (not shown) disposed respectively under the one or more external conductive contacts 341 to enhance adhesion between the external conductive contacts 341 and the encapsulation layer.

[0048] The plurality of conductive paths 32A may further include a plurality of conductive vias 351 electrically coupled to the conductive pads 313 of the semiconductor chip 310 and extending substantially longitudinally from the active surface 311 of the semiconductor chip 310 to the bottom surface 302 of the housing 31A. The plurality of conductive vias may be formed through the insulating layer from the first surface 321 to the second surface 322 of the insulating layer 320.

[0049] The plurality of conductive paths 32A may further include a plurality of conductive traces 352, which extend respectively from the conductive vias 351 and generally laterally above the bottom surface 302 to the side surface 303 of the housing 31A to electrically couple with the external conductive contacts 341. The conductive traces 352 may be formed on the second surface 322 of the insulating layer 320 and the second surface 332 of the encapsulation layer 330.

[0050] Conductive trace 352 and external conductive contact 341 form a cup-shaped member that receives the semiconductor chip. The cup-shaped member formed by conductive trace 352 and external conductive contact 341 can surround / enclose the semiconductor chip. The cup-shaped member formed by conductive trace 352 and external conductive contact 341 can surround / enclose the insulating layer 320. The cup-shaped member formed by conductive trace 352 and external conductive contact 341 can surround / enclose the encapsulation layer 330.

[0051] Fig. 6A is a top view of a semiconductor device 30B according to another embodiment of the present invention, Figure 6B It is along Fig. 6A Cross-sectional view taken along the cutting line AA' in FIG. Figure 6A-6B The semiconductor device 30B is similar to Figure 5A-5B The semiconductor device 30A is shown in FIG. 3 , but its encapsulation layer 430 is configured to completely encapsulate the semiconductor chip 310. For simplicity, Figure 6A-6B and Figure 5A-5B The same elements in the drawings have the same reference numerals and are not described in further detail.

[0052] like Fig. 6A and 6B As shown in , the encapsulation layer 430 may have a first surface 431 above the inactive surface 312 of the semiconductor chip, and a second surface 432 opposite to the first surface 431 and adjacent to the second surface 322 of the insulating layer 320. Thus, the first surface 431 of the encapsulation layer forms the top surface of the semiconductor device 30B (or housing).

[0053] Fig. 7A , 7B , 7C, 7D, 7E, 7F, 7G and 7H depict a method for manufacturing a plurality of Figure 5A-5BThe steps of the method of the semiconductor device of the embodiment of the present invention are shown in FIG. For simplicity, only two semiconductor devices are shown in this embodiment. It should be understood that the method can be used to manufacture a batch of any number of semiconductor devices.

[0054] exist Fig. 7A In the steps shown in , a base plate is provided and a plurality of insulating adhesives are applied thereto. The base plate may include, but is not limited to, a silicon (Si) or silicon carbide (SiC) substrate. The insulating adhesive may be in the form of a paste applied to the base plate by a dispensing or printing process. Alternatively, the insulating adhesive may be in the form of a film applied to the base plate by a pick-and-place process.

[0055] exist Figure 7B In the step shown in , a plurality of semiconductor chips are flipped on an insulating adhesive, wherein the conductive pad of each semiconductor chip faces the insulating adhesive. Next, the insulating adhesive can be cured to fix the semiconductor chip on a base plate and form a plurality of insulating layers respectively under the semiconductor chip.

[0056] exist Figure 7C In the steps shown in , an encapsulant may be applied to form an encapsulation layer surrounding the plurality of semiconductor chips and on top of the insulating layer. The encapsulation layer may have: a first surface adjacent to and substantially coplanar with the inactive surface of the semiconductor chip; and a second surface adjacent to and substantially coplanar with the second surface of the insulating layer. The encapsulation layer may be applied to surround the semiconductor chip without covering the inactive surface of the semiconductor chip. Alternatively, the encapsulation layer may be applied to completely cover the semiconductor chip, and then the top portion of the encapsulation layer may be removed to expose the inactive surface of the semiconductor chip.

[0057] exist Fig.7D In the step shown in , the base plate is removed to expose the second surface of the insulating layer, so that the second surface of the insulating layer and the second surface of the encapsulation layer together form the bottom surface of the semiconductor device.

[0058] exist Fig. 7E In the step shown in , one or more conductive vias are formed through the insulating layer such that the conductive vias extend substantially longitudinally from a first surface to a second surface of the insulating layer and are each electrically connected to one or more conductive pads of the semiconductor chip.

[0059] The formation of the conductive via may include: forming a through hole in the insulating layer by photolithography and etching processes; forming an oxide liner on the sidewall of the through hole; filling the through hole with a conductive material such as a metal, and then polishing the outside of the through hole to remove excess metal.

[0060] exist Figure 7FIn the step shown in , one or more conductive traces are formed on the second surface of the insulating layer and the second surface of the encapsulation layer, so that the one or more conductive traces are respectively electrically connected to the conductive vias and extend substantially laterally above the bottom surface of the semiconductor device.

[0061] The conductive traces may be formed by depositing a metal material using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, physical vapor deposition (PVD), another suitable process, or a combination thereof.

[0062] exist Figure 7G In the step shown in , one or more conductive vias are formed in the encapsulation layer, so that the one or more conductive vias are respectively electrically connected to the one or more conductive traces and extend through the encapsulation layer generally longitudinally from the first surface to the second surface of the encapsulation layer.

[0063] The formation of the conductive via may include: forming a through hole in the encapsulation layer by photolithography and etching processes; forming an oxide liner on the sidewall of the through hole; filling the through hole with a conductive material such as a metal, and then polishing the outside of the through hole to remove excess metal.

[0064] exist Figure 7H In the step shown in , the semiconductor devices are separated from each other by dicing, so that the one or more conductive vias are exposed on the side surfaces of the semiconductor devices and extend substantially longitudinally there along to form one or more external conductive contacts 341 .

[0065] Fig. 8A , 8B , 8C, 8D, 8E, 8F, 8G and 8H depict a method for manufacturing a plurality of Figure 6A-6B The steps of a method of an embodiment of a semiconductor device are described. Fig. 8A , 8B , 8C, 8D, 8E, 8F, 8G, and 8H are similar to the methods shown in Fig. 7A , 7B , 7C, 7D, 7E, 7F, 7G and 7H, but in Figure 8C In the step of applying an encapsulant to form an encapsulation layer completely covering the plurality of semiconductor chips and above the insulating layer, such that the encapsulation layer may have a top surface above the inactive surfaces of the semiconductor chips.

[0066] Fig. 9A More details of the top view of the printed circuit board 50A are shown, Fig. 9B It is along Fig. 9A Cross-sectional view taken along the cutting line AA' in FIG.

[0067] The printed circuit board 50A may include an upper surface 501 and a lower surface 502 opposite to the upper surface. Each of the upper surface 501 and the lower surface 502 may be deposited with a conductive metal layer having a pattern of pads 503 and traces 504.

[0068] In various embodiments, the printed circuit board may further include one or more substrate layers (not shown) arranged between the upper surface and the lower surface, each substrate layer having a conductive metal layer with traces and pads patterned on both sides and one or more through holes for interconnecting the conductive traces and pads.

[0069] The cavity 510A may have a through-hole structure having a top opening at an upper surface of the printed circuit board 50A and a bottom opening at a lower surface of the printed circuit board 50A.

[0070] The plurality of internal conductive leads 520 of the printed circuit board 50A may be a plurality of conductive leads 520 electrically connected to the plurality of conductive pads 503 near the cavity 510A and on the upper surface 501 of the printed circuit board 50A. Each of the conductive leads 520 may have a first lead portion 521 fixed on the conductive pads 503 and extending from the conductive pads 503 to the edge 511 of the cavity 510A. Each of the conductive leads 520 may further have a second lead portion 522 bent from the first lead portion 521 and extending generally longitudinally downward into the cavity 510A along the inner sidewall 503. In some embodiments, each conductive lead may further have a third lead portion bent from the second lead portion and extending generally laterally toward the central area of ​​the cavity.

[0071] refer to Figures 10A-10B When the semiconductor device 30A is inserted into the cavity 510A of the printed circuit board 50A, the plurality of internal conductive leads 520 may be configured to contact the plurality of external conductive contacts 341 of the semiconductor device 30A. The plurality of internal conductive leads may be in a first state, in which they are not in contact with the external conductive contacts 341 of the semiconductor device 30A, and may reversibly change to a second state, in which they are in contact with the external conductive contacts 341 of the semiconductor device 30A.

[0072] More specifically, the second lead portion 522 is elastically deformable to elastically contact the external conductive contact 341 of the semiconductor device when the semiconductor device 30A is inserted into the cavity. For example, in the first state, the second lead portion 522 has a curved surface. When the semiconductor device 30A is inserted into the cavity 510A, the second lead portion 522 is pushed by the semiconductor device 30A and has a movable end 523 that abuts against the inner side wall 503 in the cavity 510A, so that the second lead portion 522 is deformed to have a substantially flat surface that is coupled with the external conductive contact 341 of the semiconductor device 30A.

[0073] In addition, the conductive lead 520 can bend its second lead portion 522 at a first bending angle β1 relative to its first lead portion 521 in the first state; and bend its second lead portion 522 at a second bending angle β2 relative to its first lead portion 521 which is smaller than the first bending angle β1 in the second state.

[0074] Fig.11A , 11B and 11C depicts the use of manufacturing according to Figures 9A-9B The steps of an embodiment of a method of printing a circuit board are as follows.

[0075] exist Fig.11A In the steps shown in , a printed circuit board having conductive traces and pads on the upper and lower surfaces and patterned thereon is provided. The conductive traces and pads may be formed by copper plating, followed by surface finish plating using gold, silver, tin, nickel or various alloys.

[0076] exist Fig. 11B In the step shown in , a perforated cavity is formed in a printed circuit board by machine cutting or laser drilling. That is, the cavity may have a top opening at the upper surface of the printed circuit board and a bottom opening at the lower surface of the printed circuit board.

[0077] exist Fig. 11C In the steps shown in , a plurality of internal conductive leads are placed on a plurality of conductive pads near the cavity and fixed to the upper surface of the printed circuit board by welding, so that each conductive lead may have a first lead portion extending substantially laterally from the conductive pad to the edge of the cavity; and a second lead portion bent from the first lead portion and extending substantially longitudinally downward along the inner side wall into the cavity. In some embodiments, each conductive lead may further have a third lead portion bent from the second lead portion and extending substantially laterally toward the central area of ​​the cavity.

[0078] Fig. 12A More details of the top view of the printed circuit board 50B are shown, Fig. 12B It is along Fig. 12A Cross-sectional view taken along the cutting line AA' in FIG. Fig. 12A and Fig. 12B The printed circuit board 50B is similar to Fig. 9A and Fig. 9B PCB 50A, but PCB 50B includes cavity 510B having a blind hole structure. For simplicity, Fig. 12A and Fig. 12B and Fig. 9A and Fig. 9B The same elements in the drawings have the same reference numerals and are not described in further detail.

[0079] like Fig. 12A and Fig. 12B As shown in , the cavity 510B of the printed circuit board 700 may have a top opening at the upper surface 501 of the printed circuit board 50B and a bottom base 512B formed at a substrate layer between the upper and lower surfaces of the printed circuit board.

[0080] Similarly, refer to Fig.13A and Fig. 13B , the cavity 510B may have an inner shape that conforms to the outer shape of the semiconductor device 30A, so that the semiconductor device 30A may be removably fitted into the cavity 510B.

[0081] Fig.14A , 14B and 14C depiction for manufacturing according to Fig. 12A and Fig. 12B The steps of an embodiment of a method of printing a circuit board are as follows. Fig.14A , 14B The method shown in 14C is similar to Fig.11A , 11B and the method shown in 11C, but in Fig. 14B In the step of forming a blind hole cavity in the printed circuit board by machine cutting or laser drilling, the cavity may be a blind hole having a top opening at the upper surface of the printed circuit board and a bottom base at the substrate layer between the upper and lower surfaces of the printed circuit board.

[0082] The foregoing description of the present invention has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art.

[0083] The embodiment was chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use contemplated.

[0084] As used herein and not otherwise defined, the terms "substantially", "approximately" and "about" are used to describe and take into account minor variations. When used in conjunction with an event or circumstance, the term may encompass situations where the event or circumstance explicitly occurs as well as situations where the event or circumstance approximately occurs.

[0085] As used herein, the singular terms "a", "an", and "the" may include plural references unless the context clearly dictates otherwise. When describing some embodiments, a component disposed "on or over" another component may encompass the case where the former component is directly on (e.g., in physical contact with) the latter component, as well as the case where one or more intermediate components are positioned between the former component and the latter component.

[0086] Although the present disclosure has been described and illustrated with reference to the specific embodiments of the present disclosure, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims.

[0087] The illustrations may not necessarily be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the process reproduction in the present disclosure and the actual device. In addition, it should be understood that actual devices and layers may deviate from the rectangular layer depictions of the drawings and may include angular surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure that are not specifically described. This specification and drawings should be considered illustrative and not restrictive. Modifications may be made to make specific circumstances, materials, material compositions, methods or processes suitable for the objectives, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the appended claims.

[0088] Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations may be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limiting.

Claims

1. A semiconductor module, It is characterized in that include: A semiconductor device comprising: A semiconductor chip having an active surface formed with a plurality of conductive pads and a passive surface opposite to the active surface; a housing enclosing the semiconductor chip and having a top surface, a bottom surface, and a plurality of side surfaces; and, a plurality of conductive paths configured to electrically connect the semiconductor chip to an external system, the plurality of conductive paths having a plurality of external conductive contacts exposed on the plurality of side surfaces and extending from the top surface of the housing to the bottom surface along the plurality of side surfaces, the plurality of conductive paths further comprising a plurality of conductive vias and a plurality of conductive traces, the conductive vias being each electrically coupled to a conductive pad of the semiconductor chip and extending substantially longitudinally from an active surface of the semiconductor chip to the bottom surface of the housing, the conductive traces extending substantially laterally from the plurality of conductive vias and above the bottom surface of the housing to the side surfaces of the housing to electrically couple with the plurality of external conductive contacts; wherein the housing has a shape substantially conformal to that of the semiconductor chip, thereby realizing chip-scale packaging; A printed circuit board comprising: upper surface; a lower surface, which is opposite to the upper surface; one or more substrate layers disposed between the upper and lower surfaces; a cavity having one or more inner sidewalls generally perpendicular to the upper and lower surfaces; a plurality of internal conductive leads fixed on and extending from the upper surface of the printed circuit board and bent into the cavity; wherein the plurality of internal conductive leads in the cavity of the printed circuit board are configured to be able to elastically contact a plurality of external conductive contacts of the semiconductor device and to be able to electrically couple with the plurality of external conductive contacts; and each of the internal conductive leads comprises: A first lead portion, which is fixed on the conductive pad on the upper surface and extends from the conductive pad to the edge of the cavity; the first lead portion is straight and adheres to the upper surface of the printed circuit board; a second lead portion that bends from the first lead portion and extends generally longitudinally downwardly into the cavity along one of the inner side walls; wherein the cavity of the printed circuit board and the housing of the semiconductor device have shapes that conform to each other so that the semiconductor device can be removably press-fitted into the cavity of the printed circuit board; and wherein the plurality of external conductive contacts of the semiconductor device are configured to be contactable with and electrically coupleable with a plurality of internal conductive leads in the cavity of the printed circuit board such that the semiconductor device acts as an electrical plug to mate with the cavity acting as an electrical socket; The semiconductor device also includes a first heat sink mounted on a top surface of the semiconductor device.

2. The semiconductor module according to claim 1, It is characterized in that The cavity of the printed circuit board has a perforated structure.

3. The semiconductor module according to claim 2, It is characterized in that Further included is a second heat sink mounted on a bottom surface of the semiconductor device.

4. The semiconductor module according to claim 1, It is characterized in that The cavity of the printed circuit board has a blind hole structure.

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