Chip detection method, device, equipment and storage medium

Abstract

The present application proposes a chip detection method, apparatus, device, and storage medium. The chip detection method includes: obtaining the first low-level duration and the first high-level duration of the transmission bit 0 data, and the second low-level duration and the second high-level duration of the transmission bit 1 data when the chip under test performs data communication; determining whether the first low-level duration, the first high-level duration, the second low-level duration, the second high-level duration, and the relationship between the four meet preset conditions; the preset conditions are set according to the performance parameters of a preset reference chip; if so, determining that the chip under test meets the performance parameters of the preset reference chip; if not, determining that the chip under test does not meet the performance parameters of the preset reference chip. The present application can greatly improve the accuracy of differential detection and reduce the misjudgment and missed judgment phenomena caused by traditional methods.

Description

Technical Field

[0001] The present application belongs to the field of chip technology, and specifically relates to a chip detection method, device, equipment and storage medium. Background Art

[0002] With the advancement of chip technology, the number of chip manufacturers has increased. For chips of the same specifications (size, electrical performance, etc.) (including, but not limited to, chips used in microcontrollers), there are often multiple products on the market from multiple manufacturers. However, the performance of products from different manufacturers often varies. Therefore, before using a chip, it is usually necessary to test it to confirm that it is the selected chip.

[0003] In the prior art, when testing chips, especially when two chips use similar processes, the data of the two chips at specific points are often not much different, so it is easy to cause misjudgment and missed judgment, resulting in inaccurate test results. Summary of the Invention

[0004] The present application proposes a chip detection method, device, equipment and storage medium, which can greatly improve the accuracy of differential detection and reduce the misjudgment and missed judgment caused by traditional methods.

[0005] The first embodiment of the present application provides a chip detection method, including:

[0006] Obtaining the first low-level duration and the first high-level duration of the transmission bit 0 data, and the second low-level duration and the second high-level duration of the transmission bit 1 data when the chip under test performs data communication;

[0007] Determining whether the first low-level duration, the first high-level duration, the second low-level duration, the second high-level duration, and the relationship therebetween meet a preset condition; the preset condition is set according to performance parameters of a preset reference chip;

[0008] If so, it is determined that the chip under test meets the performance parameters of the preset reference chip; if not, it is determined that the chip under test does not meet the performance parameters of the preset reference chip.

[0009] In some embodiments of the present application, determining whether the first low-level duration, the first high-level duration, the second low-level duration, the second high-level duration, and the relationship therebetween meet a preset condition includes:

[0010] respectively calculating a first ratio of the first low-level duration to the first high-level duration, and a second ratio of the second low-level duration to the second high-level duration;

[0011] Determine whether the first ratio, the second ratio, and the first low-level duration and the second low-level duration or the first high-level duration and the second high-level duration all meet preset conditions.

[0012] In some embodiments of the present application, the preset conditions include: the first low-level duration belongs to a first preset range, the second low-level duration belongs to a second preset range, the first ratio belongs to a third preset range, and the second ratio belongs to a fourth preset range.

[0013] In some embodiments of the present application, determining whether the first ratio, the second ratio, and the first low-level duration and the second low-level duration or the first high-level duration and the second high-level duration all meet preset conditions includes:

[0014] Determining whether the first low-level duration falls within a first preset range;

[0015] If so, determining whether the second low-level duration falls within a second preset range;

[0016] If so, determining whether the first ratio falls within a third preset range; and

[0017] If so, it is determined whether the second ratio falls within a fourth preset range.

[0018] In some embodiments of the present application, before determining whether the first low-level duration, the first high-level duration, the second low-level duration, the second high-level duration, and the relationship between the four satisfy a preset condition, a preset condition determination step is further included. The preset condition determination step includes:

[0019] When the preset reference chip performs data communication, a first maximum value and a first minimum value of a first low-level duration, a second maximum value and a second minimum value of a first high-level duration, a third maximum value and a third minimum value of a second low-level duration, and a fourth maximum value and a fourth minimum value of a second high-level duration are obtained from a plurality of the preset reference cores;

[0020] The preset condition is determined according to the first maximum extreme value, the first minimum extreme value, the second maximum extreme value, the second minimum extreme value, the third maximum extreme value, the third minimum extreme value, the fourth maximum extreme value, and the fourth minimum extreme value.

[0021] In some embodiments of the present application, determining the preset condition according to the first maximum extreme value, the first minimum extreme value, the second maximum extreme value, the second minimum extreme value, the third maximum extreme value, the third minimum extreme value, the fourth maximum extreme value, and the fourth minimum extreme value includes:

[0022] Determine the first preset range according to the first maximum extreme value and the first minimum extreme value;

[0023] Determine the second preset range according to the third maximum extreme value and the third minimum extreme value;

[0024] Determining the third preset range according to the first maximum extreme value, the first minimum extreme value, the second maximum extreme value, and the second minimum extreme value;

[0025] The fourth preset range is determined according to the third maximum extreme value, the third minimum extreme value, the fourth maximum extreme value, and the fourth minimum extreme value.

[0026] In some embodiments of the present application, before determining whether the first low-level duration falls within a first preset range, the method further includes:

[0027] Acquiring a current ambient temperature, and determining a first compensation coefficient based on the current ambient temperature and a preset first correspondence relationship; the first correspondence relationship records a correspondence between the ambient temperature and the first compensation coefficient;

[0028] The first preset range is compensated using the first compensation coefficient.

[0029] In some embodiments of the present application, before obtaining the current ambient temperature and determining the first compensation coefficient based on the current ambient temperature and a preset first correspondence, the method further includes:

[0030] Obtaining a first low-level duration when the preset reference chip transmits bit 0 data at a reference ambient temperature, and using the first low-level duration as a first low-level duration reference value;

[0031] Taking one degree Celsius as a step, sequentially obtain a reference value of the low-level duration of the preset reference chip transmitting bit 0 data at each ambient temperature in the chip use environment;

[0032] The ratio of the high-level duration reference value corresponding to each ambient temperature value to the first low-level duration reference value is respectively determined as the first compensation coefficient corresponding to each ambient temperature value.

[0033] In some embodiments of the present application, before determining whether the second low-level duration falls within a second preset range, the method further includes:

[0034] Acquiring a current ambient temperature, and determining a second compensation coefficient based on the current ambient temperature and a preset second corresponding relationship; wherein the second corresponding relationship records a corresponding relationship between the ambient temperature and the second compensation coefficient;

[0035] The second preset range is compensated using the second compensation coefficient.

[0036] In some embodiments of the present application, before obtaining the current ambient temperature and determining the second compensation coefficient based on the current ambient temperature and a preset second correspondence, the method further includes:

[0037] Obtaining a second low level duration reference value when the preset reference chip transmits bit 1 data;

[0038] Taking one degree Celsius as a step, sequentially obtain a reference value of the low-level duration of the preset reference chip transmitting bit 1 data at each ambient temperature in the chip use environment;

[0039] The ratio of the low-level duration reference value corresponding to each ambient temperature value to the second low-level duration reference value is respectively determined as the second compensation coefficient corresponding to each ambient temperature value.

[0040] An embodiment of a second aspect of the present application provides a chip detection device, comprising:

[0041] A data acquisition module is used to obtain the first low-level duration and the first high-level duration of the transmission bit 0 data, as well as the second low-level duration and the second high-level duration of the transmission bit 1 data when the chip under test performs data communication;

[0042] a condition determination module, configured to determine whether the first low-level duration, the first high-level duration, the second low-level duration, the second high-level duration, and the relationship therebetween satisfy a preset condition; the preset condition being set according to performance parameters of a preset reference chip;

[0043] The result determination module is configured to determine, if yes, whether the chip under test meets the performance parameters of the preset reference chip; and if no, determine that the chip under test does not meet the performance parameters of the preset reference chip.

[0044] An embodiment of the third aspect of the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps described in the first aspect when executing the computer program.

[0045] An embodiment of the fourth aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, wherein the program is executed by a processor to implement the method described in the first aspect.

[0046] The technical solutions provided in the embodiments of this application have at least the following technical effects or advantages:

[0047] The chip detection method provided in the embodiment of the present application obtains the first low level duration and the first high level duration of the transmission bit 0 data, and the second low level duration and the second high level duration of the transmission bit 1 data when the chip to be tested performs data communication. Then determine whether the first low level duration, the first high level duration, the second low level duration, the second high level duration and the relationship between the four meet the preset conditions; if so, determine that the chip to be tested meets the performance parameters of the preset reference chip; if not, determine that the chip to be tested does not meet the performance parameters of the preset reference chip. In this way, by comparing the first low level duration, the first high level duration, the second low level duration, the second high level duration and the relationship between the four, with the preset conditions, the performance (including but not limited to power consumption performance and diode performance) detection of the chip to be tested can be achieved to improve the yield of the product, and the chip is subjected to anti-counterfeiting identification (chips with the same characteristic description and the preset reference belong to the same manufacturer, and chips without the same characteristic description and the preset reference do not belong to the same manufacturer). Moreover, this method distinguishes the performance of different chips from two aspects: the duration range of high and low levels and the relationship between them. It can greatly improve the accuracy of differentiation detection and reduce the misjudgment and missed judgment caused by traditional methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present application. Throughout the accompanying drawings, the same reference numerals are used to denote the same components.

[0049] In the attached figure:

[0050] Figure 1 A schematic diagram of a chip detection method according to an embodiment of the present application is shown;

[0051] Figure 2 A schematic diagram of a low-level timing sequence for transmitting bit 0 data in one embodiment of the present application is shown;

[0052] Figure 3 A schematic diagram of a high-level timing sequence for transmitting bit 0 data in one embodiment of the present application is shown;

[0053] Figure 4 A schematic diagram of a low-level timing sequence for transmitting bit 1 data in an embodiment of the present application is shown;

[0054] Figure 5 A schematic diagram of a high-level timing sequence for transmitting bit 1 data in an embodiment of the present application is shown;

[0055] Figure 6 A schematic diagram showing a flow chart of another chip detection method provided in one embodiment of the present application is shown;

[0056] Figure 7 A schematic structural diagram of an electronic device provided in one embodiment of the present application is shown;

[0057] Figure 8 A schematic diagram of a storage medium provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0058] The following describes exemplary embodiments of the present application in more detail with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0059] It should be noted that, unless otherwise specified, the technical or scientific terms used in this application should have the common meanings understood by those skilled in the art to which this application belongs.

[0060] In existing related technologies, the high-level duration (also known as width) range, low-level duration range, and total cycle range (the sum of the high-level duration and low-level duration of BIT0 or BIT1) of bit 0 (BIT0) and bit 1 (BIT1) can be tested separately. These duration ranges can then be used to distinguish between identical chips from different manufacturers. However, range testing tends to oversize the reference range, making it difficult to accurately determine chip differences based on the high and low level duration ranges. Consequently, it is difficult to effectively distinguish identical chips from different manufacturers, which can easily lead to misjudgments and inaccurate chip differentiation.

[0061] For example, when a chip's BIT0 clock frequency is relatively high, its low-level and high-level durations are both relatively short. When the BIT0 clock frequency is relatively low, its low-level and high-level durations are both relatively long. If the high and low-level duration ranges are used to distinguish the same type of chip from different manufacturers, the reference ranges for the high and low-level durations need to include both large and small tolerances. Therefore, when the actual chip being tested is smaller than the value of a reference chip of the same type, not only the small error but also the large error is considered. In this way, a chip with a smaller actual detection value compared to the reference chip of the same type may be judged as having a larger actual detection value compared to the other reference chips. This can lead to misjudgment and inaccurate chip differentiation. Furthermore, chip performance is often highly temperature-dependent. During testing, there is a significant temperature difference between the current ambient temperature and the temperature of the reference chip tested. Accounting for temperature influences requires setting a larger reference range, which further reduces the accuracy of distinguishing the same type of chip from different manufacturers using this method.

[0062] To solve the above problems, the embodiments of the present application propose a chip detection method, device, equipment and storage medium. The chip in this embodiment is usually a chip used on a single-chip microcomputer, which can be an analog chip or a digital chip, and this embodiment does not specifically limit this. The chip detection method respectively obtains the first low-level duration and the first high-level duration of the transmission bit 0 data, and the second low-level duration and the second high-level duration of the transmission bit 1 data when the chip to be tested performs data communication. Then determine whether the first low-level duration, the first high-level duration, the second low-level duration, the second high-level duration and the relationship between the four meet the preset conditions; if so, determine that the chip to be tested meets the performance parameters of the preset benchmark chip; if not, determine that the chip to be tested does not meet the performance parameters of the preset benchmark chip. In this way, by comparing the first low-level duration, the first high-level duration, the second low-level duration, the second high-level duration, and the relationship between the four with the preset conditions, the performance of the chip to be tested (including but not limited to power consumption performance and diode performance) can be detected to improve the product yield rate, and the chip can be anti-counterfeiting identified (chips with the same characteristic description and preset reference belong to the same manufacturer, and chips with different characteristic descriptions and preset references do not belong to the same manufacturer). This method distinguishes the performance of different chips from two aspects: the duration range of high and low levels and the relationship between them, which can greatly improve the accuracy of the differentiated detection and reduce the misjudgment and missed judgment caused by traditional methods.

[0063] As mentioned above, this embodiment can be applied to the chip production process to test the chip performance to improve the yield rate of the product. It can also be applied to the chip use process to perform anti-counterfeiting identification on the chip to ensure that genuine chips are used and the performance of the product is guaranteed. Accordingly, when applied to the chip production process, the preset reference chip is usually a chip with relatively ideal performance produced by a certain manufacturer itself. The various electrical properties, specifications, dimensions, internal logic, etc. of the preset reference chip can be tested and recorded before the test is tested, and this can be used to check whether the subsequent production chips meet the standards. When applied to the chip use process, the preset reference chip is usually a chip with relatively ideal performance produced by a certain manufacturer to be selected (it can be itself or an upstream manufacturer). Similarly, the various electrical properties, specifications, dimensions, internal logic, etc. of the preset reference chip can be tested and recorded before the test is tested, and this can be used to check whether the subsequent production chips meet the standards.

[0064] Please refer to Figure 1 , is a flow chart of the chip detection method provided in the embodiment of the present application, such as Figure 1 As shown, the method includes the following steps:

[0065] Step S1, obtaining the first low level duration and the first high level duration of the transmission bit 0 data, and the second low level duration and the second high level duration of the transmission bit 1 data when the chip under test performs data communication.

[0066] BIT0 and BIT1 are the basic units of data communication. Different bit logic can be defined by different high and low level duration settings. For example, a low level duration of 7μs and a high level duration of 3μs (the ratio of low level duration to high level duration is 7 / 3) represents logic BIT0; a low level duration of 2μs and a high level duration of 8μs (the ratio of low level duration to high level duration is 8 / 2) represents logic BIT1.

[0067] Typically, the high and low level durations and ratios of Bit0 and Bit1 are fixed as the design is fixed (when the chip design is fixed, the high and low level durations and ratios of the chip when transmitting Bit0 and Bit1 are also fixed). Due to chip characteristics, when the chip design fluctuates, the high and low level durations will increase or decrease simultaneously within a fixed range and at a fixed ratio.

[0068] like Figure 2 and Figure 3 As shown in FIG, they are respectively a low level timing diagram and a high level timing diagram of transmitting bit 0 data when the chip under test performs data communication. Figure 4 and Figure 5 As shown in FIG, there are respectively a low-level timing diagram and a high-level timing diagram of transmitting bit 1 data when the chip under test performs data communication.

[0069] Step S2, determining whether the first low-level duration, the first high-level duration, the second low-level duration, the second high-level duration and the relationship therebetween meet a preset condition.

[0070] The preset conditions can be set based on the performance parameters of a preset reference chip. The preset reference chip can be understood as a standard chip used to determine whether the chip under test meets the performance indicators of the standard chip, or whether it is the same type of chip from the same manufacturer as the standard chip.

[0071] In some embodiments, the above-mentioned step S2 may include the following processing: respectively calculating the first ratio of the first low-level duration and the first high-level duration, and the second ratio of the second low-level duration and the second high-level duration; determining whether the first ratio, the second ratio, and the first low-level duration and the second low-level duration or the first high-level duration and the second high-level duration all meet the preset conditions.

[0072] This embodiment specifically introduces a first ratio of the first low-level duration to the first high-level duration, and a second ratio of the second low-level duration to the second high-level duration. Specifically, the relationship between the four is the first ratio and the second ratio. Because the first and second ratios are also fixed as the chip design is fixed, they can well reflect the differences between the two chips. Therefore, this embodiment, which uses the duration range of the chip to be tested, as well as the first and second ratios, to perform chip detection, can effectively improve the accuracy of differential detection and reduce the misjudgment and missed detection phenomena caused by traditional methods.

[0073] It can be understood that the relationship between the above four is the first ratio and the second ratio, which is only one implementation of this embodiment and is not limited to this. For example, the ratio of the sum of the first low-level duration and the second low-level duration to the sum of the first high-level duration and the second high-level duration can also be used.

[0074] Specifically, the preset conditions include: the first low-level duration belongs to a first preset range, the second low-level duration belongs to a second preset range, the first ratio belongs to a third preset range, and the second ratio belongs to a fourth preset range.

[0075] It is understandable that this embodiment is not limited to using the first low level duration to be within the first preset range and the second low level duration to be within the second preset range to detect the chip type. For example, the first high level duration and the second high level duration may also be used to perform chip detection.

[0076] Based on the above-mentioned preset conditions, determining whether the first ratio, the second ratio, and the first low-level duration and the second low-level duration or the first high-level duration and the second high-level duration all meet the preset conditions may include the following processing: determining whether the first low-level duration belongs to the first preset range; if so, determining whether the second low-level duration belongs to the second preset range; if so, determining whether the first ratio belongs to the third preset range; and if so, determining whether the second ratio belongs to the fourth preset range.

[0077] It is understandable that the above steps of determining whether the first ratio, the second ratio, and the first low-level duration and the second low-level duration or the first high-level duration and the second high-level duration all meet the preset conditions are only one implementation method and do not limit the execution order. This embodiment is not limited to this. For example, it is also possible to first determine whether the second low-level duration falls within the second preset range, or first determine whether the first ratio falls within the third preset range; and if so, determine whether the second ratio falls within the fourth preset range. As long as the detection can be performed based on the four preset ranges. In addition, this embodiment can also use the first high-level duration and the second high-level duration for detection, as long as the detection function of the chip can be achieved.

[0078] In this embodiment, the preset conditions are usually measured in advance and preset on the execution subject. Therefore, before the above-mentioned step S2, the method also includes a preset condition determination step, which may include the following processing: obtaining the first maximum and first minimum values ​​of the first low-level duration, the second maximum and second minimum values ​​of the first high-level duration, the third maximum and third minimum values ​​of the second low-level duration, and the fourth maximum and fourth minimum values ​​of the second high-level duration of multiple preset reference cores when the preset reference chip performs data communication; and determining the preset conditions based on the first maximum, first minimum, second maximum, second minimum, third maximum, third minimum, fourth maximum, and fourth minimum values.

[0079] The above-mentioned multiple preset reference cores are the same type of chips from the same manufacturer, and their manufacturing processes, sizes, etc. are consistent. The extreme value can be understood as the maximum or minimum value among multiple similar test results. For example, the first maximum extreme value of the above-mentioned first low-level duration, that is, the maximum value among the low-level durations of the bit 0 data corresponding to each preset reference chip in the test results of data communication detection for the above-mentioned multiple preset reference cores. The first minimum extreme value of the above-mentioned first low-level duration, that is, the minimum value among the low-level durations of the bit 0 data corresponding to each preset reference chip in the test results of data communication detection for the above-mentioned multiple preset reference cores. The second maximum extreme value and second minimum extreme value of the first high-level duration, the third maximum extreme value and third minimum extreme value of the second low-level duration, and the fourth maximum extreme value and fourth minimum extreme value of the second high-level duration can all refer to the understanding of the first maximum extreme value and first minimum extreme value of the first low-level duration, and will not be repeated here.

[0080] In some embodiments, when determining the preset conditions based on the first maximum extreme value, the first minimum extreme value, the second maximum extreme value, the second minimum extreme value, the third maximum extreme value, the third minimum extreme value, the fourth maximum extreme value and the fourth minimum extreme value, the following processing can be included: determining the first preset range based on the first maximum extreme value and the first minimum extreme value; determining the second preset range based on the third maximum extreme value and the third minimum extreme value; determining the third preset range based on the first maximum extreme value, the first minimum extreme value, the second maximum extreme value and the second minimum extreme value; determining the fourth preset range based on the third maximum extreme value, the third minimum extreme value, the fourth maximum extreme value and the fourth minimum extreme value.

[0081] It will be understood that each of the above preset ranges is a data value interval. The first preset range is determined based on the first maximum value and the first minimum value, i.e., the lower limit of the first preset range is the first minimum value, and the upper limit is the first maximum value. The second preset range is determined based on the third maximum value and the third minimum value, i.e., the lower limit of the second preset range is the third minimum value, and the upper limit is the third maximum value.

[0082] The third preset range is used to limit the first ratio. To include all possible situations, the third preset range may be selected such that the lower limit is the smallest and the upper limit is the largest. Specifically, the third preset range may be determined based on the first maximum value, the first minimum value, the second maximum value, and the second minimum value.

[0083] The fourth preset range is used to limit the second ratio. To include all possible situations, the fourth preset range may be selected to minimize the lower limit and maximize the upper limit. Specifically, the fourth preset range may be determined based on the second maximum extreme value, the second minimum extreme value, the second maximum extreme value, and the second minimum extreme value.

[0084] It is understood that when obtaining each extreme value, it is determined by testing multiple identical preset reference chips. For example, multiple (eg, 100) reference chips are tested at room temperature of 25°C.

[0085] In some embodiments, before determining whether the first low-level duration falls within a first preset range, the following processing is further included, based on the impact of ambient temperature on the chip: obtaining the current ambient temperature, determining a first compensation coefficient based on the current ambient temperature and a preset first correspondence; the first correspondence records the correspondence between the ambient temperature and the first compensation coefficient; and compensating the first preset range using the first compensation coefficient. Thus, by setting the first compensation coefficient and compensating the first preset range, the first preset range is more closely aligned with the performance parameters of a preset benchmark chip under the current environment, further improving the accuracy of chip detection.

[0086] Specifically, before determining the first compensation coefficient based on the current ambient temperature and the preset first corresponding relationship, the following processing may also be included: obtaining the first low-level duration of the preset reference chip when transmitting bit 0 data at the reference ambient temperature, and using the first low-level duration as the first low-level duration reference value; taking one degree Celsius as a step, obtaining in turn the low-level duration reference value of the preset reference chip transmitting bit 0 data at each ambient temperature in the chip usage environment; and determining the ratio of the high-level duration reference value corresponding to each ambient temperature value to the first low-level duration reference value as the first compensation coefficient corresponding to each ambient temperature value.

[0087] The reference ambient temperature may be, but is not limited to, 25° C. (Celsius), and those skilled in the art may make a specific selection based on the specific use environment of the chip.

[0088] In other embodiments, before determining whether the second low-level duration falls within the second preset range, the following processing may be further included: obtaining the current ambient temperature, determining a second compensation coefficient based on the current ambient temperature and a preset second correspondence relationship; the second correspondence relationship records the correspondence between the ambient temperature and the second compensation coefficient; and compensating the second preset range using the second compensation coefficient. Thus, by setting the second compensation coefficient and compensating the second preset range, the second preset range is more closely aligned with the performance parameters of the preset reference chip in the current environment, further improving the accuracy of chip detection.

[0089] Specifically, before obtaining the current ambient temperature and determining the second compensation coefficient based on the current ambient temperature and the preset second corresponding relationship, it also includes: obtaining the second low-level duration reference value when the preset reference chip transmits bit 1 data; taking one degree Celsius as a step, successively obtaining the low-level duration reference value of the preset reference chip transmitting bit 1 data at each ambient temperature in the chip usage environment; and determining the ratio of the low-level duration reference value corresponding to each ambient temperature value to the second low-level duration reference value as the second compensation coefficient corresponding to each ambient temperature value.

[0090] It will be appreciated that each benchmark value is determined by testing multiple identical, pre-set benchmark chips. For example, multiple (e.g., 10) benchmark chips are tested at 25°C and the average value is calculated. The temperature of the chip environment can be, but is not limited to, 0°C to 60°C.

[0091] Step S3: If yes, it is determined that the chip under test meets the performance parameters of the preset reference chip; if not, it is determined that the chip under test does not meet the performance parameters of the preset reference chip.

[0092] The following is combined with Figure 6 The process of chip detection based on high and low levels in this embodiment is described in detail. Figure 6As shown, when the chip under test performs data communication, the low-level duration T1 of the transmission bit 0 data, the high-level duration T2 of the transmission bit 0 data, the low-level duration T1 of the transmission bit 1 data, and the high-level duration T4 of the transmission bit 1 data are tested. Then, based on the corresponding relationship between the current ambient temperature and the preset temperature-compensation coefficient, the compensation coefficient is determined, and then the first preset range and the second preset range are determined. Then, based on the first preset range and the second preset range, the above-mentioned T1 and T3 are range-judged. If T1 falls within the first preset range and T3 falls within the second preset range, the ratio X (T1 / T2) and the ratio Y (T3 / T4) are then judged. If the ratio X falls within the third preset range and the ratio Y falls within the fourth preset range, it is determined that the chip under test meets the performance parameters of the preset reference chip, that is, the chip under test is qualified, or it is from the same manufacturer as the preset reference chip. If one of the above judgments does not fall within the corresponding preset range, it is determined that the chip under test does not meet the performance parameters of the preset reference chip, that is, the chip under test is unqualified, or it is from a different manufacturer than the preset reference chip.

[0093] In summary, the chip detection method provided in this embodiment obtains the first low level duration and the first high level duration of the transmission bit 0 data, and the second low level duration and the second high level duration of the transmission bit 1 data when the chip to be tested performs data communication. Then, it is determined whether the first low level duration, the first high level duration, the second low level duration, the second high level duration and the relationship between the four meet the preset conditions; if so, it is determined that the chip to be tested meets the performance parameters of the preset reference chip; if not, it is determined that the chip to be tested does not meet the performance parameters of the preset reference chip. In this way, by comparing the first low level duration, the first high level duration, the second low level duration, the second high level duration and the relationship between the four with the preset conditions, the performance (including but not limited to power consumption performance and diode performance) of the chip to be tested can be detected to improve the yield of the product and to perform anti-counterfeiting identification on the chip (chips with the same characteristic description and the preset reference belong to the same manufacturer, and chips that do not have the same characteristic description and the preset reference do not belong to the same manufacturer). Moreover, this method distinguishes the performance of different chips from two aspects: the duration range of high and low levels and the relationship between them. It can greatly improve the accuracy of differentiation detection and reduce the misjudgment and missed judgment caused by traditional methods.

[0094] Based on the same concept as above, this embodiment further provides a chip detection device, which includes:

[0095] A data acquisition module is used to obtain the first low-level duration and the first high-level duration of the transmission bit 0 data, as well as the second low-level duration and the second high-level duration of the transmission bit 1 data when the chip under test performs data communication;

[0096] A condition determination module is used to determine whether the first low-level duration, the first high-level duration, the second low-level duration, the second high-level duration, and the relationship between the four satisfy a preset condition; the preset condition is set according to the performance parameters of a preset reference chip;

[0097] The result determination module is used to determine that if yes, the chip under test meets the performance parameters of the preset reference chip; if no, determine that the chip under test does not meet the performance parameters of the preset reference chip.

[0098] The chip detection device provided in this embodiment is based on the same concept as the above-mentioned chip detection method, so it can at least achieve the above-mentioned beneficial effects, and any of the above-mentioned implementation methods can be applied to the chip detection device provided in this embodiment, which will not be repeated here.

[0099] The present application also provides an electronic device to perform the above chip detection method. Figure 7 , which shows a schematic diagram of an electrical device provided by some embodiments of the present application. Figure 7 As shown, the electrical device 40 includes: a processor 400, a memory 401, a bus 402 and a communication interface 403. The processor 400, the communication interface 403 and the memory 401 are connected through the bus 402; the memory 401 stores a computer program that can be run on the processor 400, and when the processor 400 runs the computer program, it executes the chip detection method provided in any of the aforementioned embodiments of the present application.

[0100] The memory 401 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage. The communication connection between the device network element and at least one other network element is achieved through at least one communication interface 403 (which may be wired or wireless), and may use the Internet, a wide area network, a local area network, a metropolitan area network, etc.

[0101] Bus 402 may be an ISA bus, a PCI bus, or an EISA bus. Buses may be classified as address buses, data buses, and control buses. Memory 401 is used to store programs, and processor 400 executes the programs upon receiving execution instructions. The chip detection method disclosed in any of the aforementioned embodiments of the present application may be applied to or implemented by processor 400.

[0102] The processor 400 may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by hardware integrated logic circuits in the processor 400 or by software instructions. The above processor 400 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an off-the-shelf field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in conjunction with the embodiments of this application can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium mature in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, etc. The storage medium is located in the memory 401 , and the processor 400 reads the information in the memory 401 and completes the steps of the above method in combination with its hardware.

[0103] The electrical equipment provided in the embodiment of the present application and the chip detection method provided in the embodiment of the present application are based on the same inventive concept and have the same beneficial effects as the methods adopted, operated or implemented therein.

[0104] The present application also provides a computer-readable storage medium corresponding to the chip detection method provided in the above embodiment. Figure 8 The computer-readable storage medium shown is a CD 30 on which a computer program (ie, a program product) is stored. When the computer program is run by a processor, it executes the chip detection method provided by any of the aforementioned embodiments.

[0105] It should be noted that examples of computer-readable storage media may also include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other optical or magnetic storage media, which are not listed here one by one.

[0106] The computer-readable storage medium provided in the above-mentioned embodiments of the present application and the chip detection method provided in the embodiments of the present application are based on the same inventive concept and have the same beneficial effects as the methods adopted, run or implemented by the application programs stored therein.

[0107] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application, and they should all be included in the scope of the claims and specification of the present application. In particular, as long as there is no structural conflict, the various technical features mentioned in the various embodiments can be combined in any way. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions that fall within the scope of the claims.

Claims

1. A chip detection method, characterized in that: The method comprises: Obtaining the first low-level duration and the first high-level duration of the transmission bit 0 data, and the second low-level duration and the second high-level duration of the transmission bit 1 data when the chip under test performs data communication; Determining whether the first low-level duration, the first high-level duration, the second low-level duration, the second high-level duration, and the relationship therebetween meet a preset condition; the preset condition is set according to performance parameters of a preset reference chip; If yes, it is determined that the chip under test meets the performance parameters of the preset reference chip; if no, it is determined that the chip under test does not meet the performance parameters of the preset reference chip; Determining whether the first low-level duration, the first high-level duration, the second low-level duration, the second high-level duration, and the relationship therebetween meet a preset condition includes: respectively calculating a first ratio of the first low-level duration to the first high-level duration, and a second ratio of the second low-level duration to the second high-level duration; Determine whether the first ratio, the second ratio, and the first low-level duration and the second low-level duration or the first high-level duration and the second high-level duration all meet the preset condition.

2. The method according to claim 1, characterized in that The preset conditions include: the first low-level duration belongs to a first preset range, the second low-level duration belongs to a second preset range, the first ratio belongs to a third preset range, and the second ratio belongs to a fourth preset range.

3. The method according to claim 1 or 2, characterized in that Determining whether the first ratio, the second ratio, and the first low-level duration and the second low-level duration or the first high-level duration and the second high-level duration all meet preset conditions includes: Determining whether the first low-level duration falls within a first preset range; If so, determining whether the second low-level duration falls within a second preset range; If so, determining whether the first ratio falls within a third preset range; and If so, it is determined whether the second ratio falls within a fourth preset range.

4. The method according to claim 3, characterized in that Before determining whether the first low-level duration, the first high-level duration, the second low-level duration, the second high-level duration, and the relationship between the four satisfy a preset condition, a preset condition determining step is further included, and the preset condition determining step includes: When the preset reference chip performs data communication, a first maximum value and a first minimum value of a first low-level duration, a second maximum value and a second minimum value of a first high-level duration, a third maximum value and a third minimum value of a second low-level duration, and a fourth maximum value and a fourth minimum value of a second high-level duration are obtained from a plurality of the preset reference cores; The preset condition is determined according to the first maximum extreme value, the first minimum extreme value, the second maximum extreme value, the second minimum extreme value, the third maximum extreme value, the third minimum extreme value, the fourth maximum extreme value, and the fourth minimum extreme value.

5. The method according to claim 4, characterized in that Determining the preset condition according to the first maximum extreme value, the first minimum extreme value, the second maximum extreme value, the second minimum extreme value, the third maximum extreme value, the third minimum extreme value, the fourth maximum extreme value, and the fourth minimum extreme value includes: Determine the first preset range according to the first maximum extreme value and the first minimum extreme value; Determine the second preset range according to the third maximum extreme value and the third minimum extreme value; Determining the third preset range according to the first maximum extreme value, the first minimum extreme value, the second maximum extreme value, and the second minimum extreme value; The fourth preset range is determined according to the third maximum extreme value, the third minimum extreme value, the fourth maximum extreme value, and the fourth minimum extreme value.

6. The method according to claim 5, characterized in that Before determining whether the first low-level duration falls within a first preset range, the method further includes: Acquiring a current ambient temperature, and determining a first compensation coefficient based on the current ambient temperature and a preset first correspondence relationship; the first correspondence relationship records a correspondence between the ambient temperature and the first compensation coefficient; The first preset range is compensated using the first compensation coefficient.

7. The method according to claim 6, characterized in that Before obtaining the current ambient temperature and determining the first compensation coefficient based on the current ambient temperature and a preset first corresponding relationship, the method further includes: Obtaining a first low-level duration when the preset reference chip transmits bit 0 data at a reference ambient temperature, and using the first low-level duration as a first low-level duration reference value; Taking one degree Celsius as a step, sequentially obtain a reference value of the low-level duration of the preset reference chip transmitting bit 0 data at each ambient temperature in the chip use environment; The ratio of the high-level duration reference value corresponding to each ambient temperature value to the first low-level duration reference value is respectively determined as the first compensation coefficient corresponding to each ambient temperature value.

8. The method according to claim 5, characterized in that Before determining whether the second low-level duration falls within a second preset range, the method further includes: Acquiring a current ambient temperature, and determining a second compensation coefficient based on the current ambient temperature and a preset second corresponding relationship; wherein the second corresponding relationship records a corresponding relationship between the ambient temperature and the second compensation coefficient; The second preset range is compensated using the second compensation coefficient.

9. The method according to claim 8, characterized in that Before obtaining the current ambient temperature and determining the second compensation coefficient based on the current ambient temperature and a preset second corresponding relationship, the method further includes: Obtaining a second low level duration reference value when the preset reference chip transmits bit 1 data; Taking one degree Celsius as a step, sequentially obtain a reference value of the low-level duration of the preset reference chip transmitting bit 1 data at each ambient temperature in the chip use environment; The ratio of the low-level duration reference value corresponding to each ambient temperature value to the second low-level duration reference value is respectively determined as the second compensation coefficient corresponding to each ambient temperature value.

10. A chip detection device, characterized in that: The device comprises: A data acquisition module is used to obtain the first low-level duration and the first high-level duration of the transmission bit 0 data, as well as the second low-level duration and the second high-level duration of the transmission bit 1 data when the chip under test performs data communication; A condition determination module, used to determine whether the first low-level duration, the first high-level duration, the second low-level duration, the second high-level duration, and the relationship therebetween meet a preset condition; the preset condition is set according to the performance parameters of a preset reference chip; determining whether the first low-level duration, the first high-level duration, the second low-level duration, the second high-level duration, and the relationship therebetween meet the preset condition, including: respectively calculating a first ratio of the first low-level duration to the first high-level duration, and a second ratio of the second low-level duration to the second high-level duration; determining whether the first ratio, the second ratio, and the first low-level duration and the second low-level duration or the first high-level duration and the second high-level duration all meet the preset condition; The result determination module is configured to determine, if yes, whether the chip under test meets the performance parameters of the preset reference chip; and if no, determine that the chip under test does not meet the performance parameters of the preset reference chip.

11. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the method according to any one of claims 1 to 9 is implemented.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that: The program is executed by a processor to implement the method according to any one of claims 1 to 9.

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