A circuit and method for recovering FPGA program online update failure

Abstract

A circuit and method for recovering an FPGA program after an online update failure, which can automatically restore the program and state after an online update failure of the FPGA program. The circuit includes a main control FPGA, a first auxiliary circuit, a second auxiliary circuit, and a third auxiliary circuit, wherein the first auxiliary circuit, the second auxiliary circuit, and the third auxiliary circuit are respectively connected to the main control FPGA; the first auxiliary circuit executes the connection and automatic switching of the first FLASH storage chip and the second FLASH storage chip interface with the loading configuration pin of the main control FPGA; the second auxiliary circuit connects the first FLASH storage chip and the second FLASH storage chip, and the second auxiliary circuit executes the reset of the main control FPGA itself and delays the storage of the reset signal; the third auxiliary circuit is connected to a host computer through an external communication interface.

Description

Technical Field

[0001] The present invention relates to the technical field of programmable logic devices, and in particular to a recoverable circuit for failure in online updating of an FPGA program, and a recoverable method for failure in online updating of an FPGA program. Background Art

[0002] FPGA (Field-Programmable Gate Array) is a semi-customized circuit in the application-specific integrated circuit. It is a programmable logic array that can effectively solve the problem of the small number of gate circuits in the original device. The basic structure of FPGA includes programmable input and output units, configurable logic blocks, digital clock management modules, embedded block RAM, wiring resources, embedded dedicated hard cores, and bottom-level embedded functional units. Due to the characteristics of rich wiring resources, reprogrammable and high integration, and low investment, FPGA has been widely used in the field of digital circuit design. The design process of FPGA includes algorithm design, code simulation, design, and board debugging. Designers and actual needs establish algorithm architecture, use EDA to establish design plans or HD to write design codes, and ensure that the design plans meet actual requirements through code simulation. Finally, board-level debugging is performed, and the relevant files are downloaded to the FPGA chip using the configuration circuit to verify the actual operation effect.

[0003] In the field of FPGA chip applications, online program updates of the device where the FPGA is located are a common and important function and requirement. Conventional program updates require opening the device or chassis shell and then updating the program through a dedicated burner. Online updates do not require opening the device or chassis shell and can directly update the program through common external interfaces such as serial ports, which simplifies the burning process and improves efficiency.

[0004] However, when the FPGA program is updated online, the original program in the Flash is usually required to support the generation of external interfaces and communication protocols through the FPGA in order to erase and solidify the Flash program. In this process, if the erasure and solidification of the Flash cannot be completed due to power failure or other reasons, the original program in the Flash will be destroyed, the device will lose all functions, and the next online update will be impossible. This reduces the reliability and adaptability of the FPGA and the device it is in. Therefore, how to automatically restore the program and state after the online update of the FPGA program fails is a technical problem that technicians in this field currently need to solve. Summary of the invention

[0005] In order to overcome the defects of the prior art, the technical problem to be solved by the present invention is to provide a circuit capable of recovering an FPGA program online update failure, which can automatically realize program and status recovery after the FPGA program online update fails.

[0006] This FPGA program online update failure recovery circuit includes a main control FPGA, a first auxiliary circuit, a second auxiliary circuit, and a third auxiliary circuit, wherein the first auxiliary circuit, the second auxiliary circuit, and the third auxiliary circuit are respectively connected to the main control FPGA;

[0007] The first auxiliary circuit performs connection and automatic switching between the first FLASH memory chip, the second FLASH memory chip interface and the loading configuration pins of the main control FPGA;

[0008] The second auxiliary circuit is connected to the first FLASH memory chip and the second FLASH memory chip, and the second auxiliary circuit performs the reset of the main control FPGA itself and delays the storage of the reset signal;

[0009] The third auxiliary circuit is connected to the host computer through an external communication interface.

[0010] The present invention connects the first FLASH memory chip and the second FLASH memory chip through the second auxiliary circuit, the second auxiliary circuit executes the reset of the main control FPGA itself, and delays the storage of the reset signal, the first auxiliary circuit executes the connection and automatic switching of the first FLASH memory chip, the second FLASH memory chip interface and the loading configuration pin of the main control FPGA, and the third auxiliary circuit is connected to the host computer through the external communication interface, even if the Flash erasure and curing are not completed, the original program in the Flash will not be destroyed, the reliability and adaptability of the FPGA and the device in which it is located are improved, so that after the online update of the FPGA program fails, the program and state are automatically restored.

[0011] A method for recovering from a failed online update of an FPGA program is also provided, which comprises the following steps:

[0012] (1) The master FPGA loads the program in the first FLASH storage chip by default and detects the second

[0013] Whether there is a program in the FLASH memory chip, if there is a program, execute step (2), otherwise execute step (3);

[0014] (2) The master control FPGA reloads the program in the second FLASH storage chip and jumps to step (4);

[0015] (3) The master FPGA continues to run the program in the first FLASH storage chip;

[0016] (4)End.

[0017] Another method for recovering from a failed online update of an FPGA program is also provided, which includes the following steps:

[0018] (a) When powered on, the CS1 signal is valid by default, and the master FPGA loads the first FLASH memory chip.

[0019] Program in the film;

[0020] (b) After the program is loaded, configure CS2 to be valid and detect it through the update status monitoring unit

[0021] The state of a specific flag bit in the second FLASH memory chip;

[0022] (c) If the detection flag is valid, the master FPGA executes step (e) and feeds back a solidification completion signal to the host computer; if the detection flag is invalid, step (d) is executed and fed back to the host computer.

[0023] Host computer solidification failure signal;

[0024] (d) indicates that there is no upgrade program in the second FLASH storage chip, or the upgrade program fails, then it is restored to the default CS1 valid state, and the main control FPGA continues to execute the first FLASH storage chip

[0025] Medium program;

[0026] (e) The main control FPGA keeps the chip select as CS2, and the CS2 chip select signal is locked by the first auxiliary circuit;

[0027] (f) The master control FPGA sends a reset instruction, and the reset instruction restarts the master control FPGA via the second auxiliary circuit;

[0028] (g) FPGA loads the code stream in the second FLASH memory chip and uses the program in the second FLASH memory chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 The principle block diagram of the FPGA program online update failure recoverable circuit according to the present invention is shown.

[0030] Figure 2 A circuit diagram of a first auxiliary circuit according to the present invention is shown.

[0031] Figure 3 A circuit diagram of a second auxiliary circuit according to the present invention is shown.

[0032] Figure 4 A flow chart of a method for recovering a failed online update of an FPGA program according to the present invention is shown.

[0033] Figure 5 The present invention is a flowchart of solidifying a program in a first FLASH storage chip of a method for recovering a failed online update of an FPGA program according to the present invention.

[0034] Figure 6 The present invention is a flowchart of solidifying a program in a second FLASH storage chip according to a method for recovering a failed online update of an FPGA program. DETAILED DESCRIPTION

[0035] like Figure 1 As shown, this FPGA program online update failure recovery circuit includes a main control FPGA, a first auxiliary circuit (auxiliary circuit 1), a second auxiliary circuit (auxiliary circuit 2), and a third auxiliary circuit (auxiliary circuit 3), wherein the first auxiliary circuit, the second auxiliary circuit, and the third auxiliary circuit are respectively connected to the main control FPGA;

[0036] The first auxiliary circuit performs connection and automatic switching between the first FLASH memory chip (Flash1), the second FLASH memory chip (Flash2) interface and the loading configuration pins of the main control FPGA;

[0037] The second auxiliary circuit is connected to the first FLASH memory chip and the second FLASH memory chip, and the second auxiliary circuit performs the reset of the main control FPGA itself and delays the storage of the reset signal;

[0038] The third auxiliary circuit is connected to the host computer through an external communication interface.

[0039] The present invention connects the first FLASH memory chip and the second FLASH memory chip through the second auxiliary circuit, the second auxiliary circuit executes the reset of the main control FPGA itself, and delays the storage of the reset signal, the first auxiliary circuit executes the connection and automatic switching of the first FLASH memory chip, the second FLASH memory chip interface and the loading configuration pin of the main control FPGA, and the third auxiliary circuit is connected to the host computer through the external communication interface, even if the Flash erasure and curing are not completed, the original program in the Flash will not be destroyed, the reliability and adaptability of the FPGA and the device in which it is located are improved, so that after the online update of the FPGA program fails, the program and state are automatically restored.

[0040] Preferably, the master control FPGA includes an initial module and an update module, the initial module includes: an online update unit, an update status detection unit, a Flash interface switching unit and a self-reset unit, and the update module includes an online update unit;

[0041] The online update unit performs: host computer communication, communication command analysis, data protocol conversion, Flash interface protocol and data burning;

[0042] Update status monitoring unit execution: Flash interface protocol, data reading and judgment;

[0043] The Flash interface switching unit switches the interface between the FPGA and the Flash between the first FLASH storage chip and the second FLASH storage chip, and the states include: initial stage, state monitoring stage, monitoring completion stage, and online update stage;

[0044] The self-reset unit determines whether to output a reset signal to the third auxiliary circuit according to the output result of the update status monitoring unit.

[0045] Preferably, if Figure 2 As shown, the first auxiliary circuit includes a delay circuit and a hysteresis trigger circuit; the delay circuit includes a first resistor R1 (300Ω), a second resistor R2 (10kΩ), and a first capacitor C1 (47nF); the hysteresis trigger circuit includes an inverter S with a Schmitt trigger, a third resistor R3 (10kΩ), and a fourth resistor R4 (10kΩ); the second resistor and the first capacitor are connected in parallel, one end of which is grounded and the other end is connected between the first resistor and the inverter with the Schmitt trigger, the third resistor is connected to the input end of the inverter with the Schmitt trigger, the output of the inverter with the Schmitt trigger is connected to the reset input pin of the FPGA, and the fourth resistor is connected to the output of the inverter with the Schmitt trigger; the inverter with the Schmitt trigger is a chip 54LS132;

[0046] Select any IO3 on the FPGA to send a reset command signal to enter the first resistor of the delay circuit. The delay circuit uses two resistors and a capacitor to quickly establish and slowly release the high-level signal of the reset command; then enter the hysteresis circuit. The hysteresis circuit uses an inverter with a Schmitt trigger and two resistors, and uses its own threshold hysteresis to achieve level maintenance; finally, the reset command after delay and level maintenance is output to the reset input pin of the FPGA.

[0047] The purpose of the first auxiliary circuit is to realize the self-reset of FPGA. During the FPGA reset process, the reset signal needs to maintain a stable low level for a period of time. The reset signal itself is output by the FPGA pin, and the pin level will change during the reset process, so the circuit needs to have a "memory retention" function.

[0048] Preferably, if Figure 3 As shown, the second auxiliary circuit includes two chips 54LS279, three chips 54LS132 and three resistors R5, R6, R7;

[0049] The input of each chip 54LS279 is connected to two arbitrary pins IO1 and IO2 of FPGA, and the output is connected to the input of a chip 54LS132. The fifth resistor and the seventh resistor are connected to a chip

[0050] The pin IO1 corresponding to 54LS279 and the pin IO2 corresponding to another chip 54LS279, the sixth resistor is connected to the input of the third chip 54LS132 and the output of the third chip 54LS132 is connected to the input of the first chip 54LS132 and the second chip 54LS132;

[0051] Among the Flash interface pins of the FPGA chip, the three pins CLK, SI and SO are simultaneously connected to the corresponding pins of the two Flash chips; the FCS chip select pin and two arbitrary pins IO1 and IO2 of the FPGA enter the second auxiliary circuit, and the circuit outputs CS1 and CS2 signals which are respectively connected to the CS pins of the two Flash chips; the FPGA switches the FPGA chip select signal to the CS pins of the two Flash chips through different combinations of IO1 and IO2 output levels, and can keep the signal stable during the FPGA reset and loading process.

[0052] The chip select signals corresponding to the IO1 and IO2 combinations are shown in Table 1.

[0053] Table 1

[0054] stage IO1, IO2 FPGA interface switches to Initial stage 1，1 Flash1 Condition monitoring phase 1，0 Flash2 Monitoring completion stage (flash2 has no complete program) 0，1 Flash1 Monitoring completion stage (flash2 has a complete program) 1，0 Flash2 Online update phase 1，0 Flash2

[0055] The purpose of the second auxiliary circuit is to realize the "switch hold" function of the chip select signals of the two Flash chips of the FPGA.

[0056] Preferably, the first FLASH storage chip is a default loading Flash, which is burned and fixed by the equipment manufacturer through the jtag interface during the production and debugging stage; the second FLASH storage chip is an online update program Flash, which is updated and fixed online through the serial port.

[0057] In brief, the FPGA program online update failure recovery method of the present invention comprises the following steps:

[0058] (1) The master FPGA loads the program pro1 in the first FLASH storage chip by default, and detects whether there is program pro2 in the second FLASH storage chip. If there is a program, execute steps

[0059] (2), otherwise, execute step (3);

[0060] (2) The master control FPGA reloads the program in the second FLASH storage chip and jumps to step (4);

[0061] (3) The master FPGA continues to run the program in the first FLASH storage chip;

[0062] (4)End.

[0063] Preferably, in the production debugging stage, the first auxiliary circuit sets the first FLASH memory chip select signal to be valid and the CS2 signal to be invalid by default.

[0064] Preferably, during the application phase, when the program is updated online, the host computer and the device are connected using an external interface, and the host computer outputs an instruction to update the second FLASH storage chip to the main control FPGA through an external communication tool, and sends the code stream data; after the main control FPGA recognizes the instruction, it updates the code stream data to the second FLASH storage chip through the instruction parsing IP and the protocol conversion IP, completing the online program update process.

[0065] like Figure 4 As shown, another method for recovering from a failed online update of an FPGA program is also provided, which includes the following steps:

[0066] (a) When powered on, the CS1 signal is valid by default, and the main control FPGA loads the program in the first FLASH storage chip;

[0067] (b) after the program is loaded, configure CS2 to be valid, and detect the status of a specific flag bit in the second FLASH storage chip through an update status monitoring unit;

[0068] (c) If the detection flag is valid, the master FPGA executes step (e) and feeds back a curing completion signal to the host computer; if the detection flag is invalid, step (d) is executed and a curing failure signal is fed back to the host computer;

[0069] (d) indicates that there is no upgrade program in the second FLASH storage chip, or the upgrade program fails, then the default CS1 valid state is restored, and the master control FPGA continues to execute the program in the first FLASH storage chip;

[0070] (e) The main control FPGA keeps the chip select as CS2, and the CS2 chip select signal is locked by the first auxiliary circuit;

[0071] (f) The master control FPGA sends a reset instruction, and the reset instruction restarts the master control FPGA via the second auxiliary circuit;

[0072] (g) FPGA loads the code stream in the second FLASH memory chip and uses the program in the second FLASH memory chip.

[0073] The present invention is described in more detail below.

[0074] Devices with FPGA online update requirements can usually be divided into the manufacturer's production and debugging stage and the user application stage;

[0075] Production debugging stage

[0076] 1) During the production debugging phase, the manufacturer uses a burner to write the initial program to the FPGA through the Jtag interface.

[0077] "pro1" is fixed to Flash. Since the Flash1 chip select signal is enabled by default in auxiliary circuit 1, "pro1" will be loaded into Flash1; while the CS2 signal is disabled, there is no program in Flash2; 2) After the device is powered on again, since the CS1 signal is enabled by default, the FPGA will read the program in Flash1

[0078] "pro1". Then comes the application phase.

[0079] Application Phase

[0080] 3) If the program needs to be updated online during the application phase, use an external interface to connect the host computer and the device. The host computer outputs the update Flash2 command to the FPGA through an external communication tool and sends the "pro2" code stream data;

[0081] 4) After FPGA recognizes the instruction, it updates the code stream data to Flash2 through the instruction parsing IP and protocol conversion IP. The online update process is completed;

[0082] 5) When the application stage program is loaded, FPGA operations are performed in the following order:

[0083] a) When powered on, the CS1 signal is valid by default, and the FPGA loads the program "Pro1" in FLASH1;

[0084] b) After the program is loaded, configure CS2 to be valid, and detect the status of specific flag bits in FLASH2 through the update status monitoring unit, such as 0x00 address 0x55AA is a successful burning flag;

[0085] c) If the b operation detection flag is valid, the FPGA executes e operation and feeds back a curing completion signal to the host computer; if the b operation detection flag is invalid, the FPGA executes d operation and feeds back a curing failure signal to the host computer;

[0086] d) Indicates that there is no upgrade program in Flash2, or the upgrade program fails, then it will be restored to the default CS1 valid state, and the FPGA will continue to execute the "Pro1" application.

[0087] e) FPGA keeps chip select as CS2, and the CS2 chip select signal is locked by auxiliary circuit 1;

[0088] f) FPGA sends a reset instruction, and the reset instruction restarts the FPGA through auxiliary circuit 2;

[0089] FPGA loads the pro2 code stream in Flash2 and uses the "Pro2" application.

[0090] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any simple modification, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are still within the protection scope of the technical solution of the present invention.

Claims

1. A circuit capable of recovering from failure of online updating of FPGA program, characterized in that: It includes a main control FPGA, a first auxiliary circuit, a second auxiliary circuit, and a third auxiliary circuit, wherein the first auxiliary circuit, the second auxiliary circuit, and the third auxiliary circuit are respectively connected to the main control FPGA; The first auxiliary circuit performs connection and automatic switching between the first FLASH memory chip, the second FLASH memory chip interface and the loading configuration pins of the main control FPGA; The second auxiliary circuit is connected to the first FLASH memory chip and the second FLASH memory chip, and the second auxiliary circuit performs the reset of the main control FPGA itself and delays the storage of the reset signal; The third auxiliary circuit is connected to the host computer via an external communication interface; The master control FPGA includes an initial module and an update module, the initial module includes: an online update unit, an update status detection unit, a Flash interface switching unit and a self-reset unit, and the update module includes an online update unit; The online update unit performs: host computer communication, communication command analysis, data protocol conversion, Flash interface protocol and data burning; Update status monitoring unit execution: Flash interface protocol, data reading and judgment; The Flash interface switching unit switches the interface between the FPGA and the Flash between the first FLASH storage chip and the second FLASH storage chip, and the states include: initial stage, state monitoring stage, monitoring completion stage, and online update stage; The self-reset unit determines whether to output a reset signal to the third auxiliary circuit according to the output result of the update status monitoring unit; The first auxiliary circuit includes a delay circuit and a hysteresis trigger circuit; the delay circuit includes a first resistor (R1), a second resistor (R2), and a first capacitor (C1); the hysteresis trigger circuit includes an inverter (S) with a Schmitt trigger, a third resistor (R3), and a fourth resistor (R4); the second resistor and the first capacitor are connected in parallel, one end of which is grounded and the other end is connected between the first resistor and the inverter with the Schmitt trigger, the third resistor is connected to the input end of the inverter with the Schmitt trigger, the output of the inverter with the Schmitt trigger is connected to the reset input pin of the FPGA, and the fourth resistor is connected to the output of the inverter with the Schmitt trigger; the inverter with the Schmitt trigger is a chip 54LS132; the first resistor is 300Ω, the second resistor is 10kΩ, the first capacitor is 47nF, the third resistor is 10kΩ, and the fourth resistor is 10kΩ; Select any IO3 on the FPGA to send a reset command signal to enter the first resistor of the delay circuit. The delay circuit uses two resistors and a capacitor to quickly establish and slowly release the high-level signal of the reset command; then enter the hysteresis circuit. The hysteresis circuit uses an inverter with a Schmitt trigger and two resistors, and uses its own threshold hysteresis to achieve level maintenance; finally, the reset command after delay and level maintenance is output to the reset input pin of the FPGA.

2. The FPGA program online update failure recovery circuit according to claim 1, characterized in that: The second auxiliary circuit includes two chips 54LS279, three chips 54LS132 and three resistors (R5, R6, R7); The input of each chip 54LS279 is connected to two arbitrary pins IO1 and IO2 of the FPGA, and the output is connected to the input of a chip 54LS132. The fifth resistor and the seventh resistor are respectively connected to the pin IO1 corresponding to one chip 54LS279 and the pin IO2 corresponding to another chip 54LS279. The sixth resistor is connected to the input of the third chip 54LS132, and the output of the third chip 54LS132 is connected to the input of the first chip 54LS132 and the second chip 54LS132. Among the Flash interface pins of the FPGA chip, the three pins CLK, SI and SO are simultaneously connected to the corresponding pins of the two Flash chips; the FCS chip select pin and two arbitrary pins IO1 and IO2 of the FPGA enter the second auxiliary circuit, and the circuit outputs CS1 and CS2 signals which are respectively connected to the CS pins of the two Flash chips; the FPGA switches the FPGA chip select signal to the CS pins of the two Flash chips through different combinations of IO1 and IO2 output levels, and can keep the signal stable during the FPGA reset and loading process.

3. The FPGA program online update failure recovery circuit according to claim 2, characterized in that: The first FLASH storage chip is the default loading Flash, which is burned and fixed by the equipment manufacturer through the JTAG interface during the production and debugging stage; the second FLASH storage chip is the online update program Flash, which is updated and fixed online through the serial port.

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