A layout structure of a semiconductor device

Abstract

The application provides a layout structure of a semiconductor device, comprising two word lines extending along a first direction, a plurality of source lines arranged along the first direction between the two word lines, and gaps between adjacent two source lines, wherein the word lines have first protruding parts protruding into each of the gaps, the two first protruding parts in each of the gaps are arranged staggeredly along the first direction, each of the first protruding parts is provided with a word line plug, and an isolation structure is arranged between each of the first protruding parts and the adjacent source line. The isolation structure isolates the source line and the word line plug, prevents short circuit between the word line plug and the source line when the word line plug is deviated, and avoids leakage between the source line and the word line.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a layout structure of a semiconductor device. BACKGROUND

[0002] Since the advent of semiconductor devices, the integration of semiconductor devices has been increasing, and the size of semiconductor devices has been decreasing with market demand, and semiconductor devices have been developing towards smaller sizes and higher integration densities. In the preparation process of the back-end-of-line of semiconductor devices, metal interconnection lines are usually used to lead out the structures of each device, and the electrical connection between two layers is realized through a plug structure, but as the size of semiconductor devices continues to shrink, the critical dimension of the plug structure used for leading out is also becoming smaller and smaller, which leads to the problem of position deviation or size increase of the plug structure during preparation, and further causes unnecessary short circuit and leakage between other structures. SUMMARY

[0003] The purpose of the present application is to provide a layout structure of a semiconductor device to avoid the short circuit and leakage problems caused by the position deviation of the plug structure.

[0004] In order to achieve the above purpose, the present application provides a layout structure of a semiconductor device, comprising:

[0005] Two word lines extending in a first direction, a plurality of source lines arranged in the first direction between the two word lines, a gap between adjacent two source lines, the word line having a first protruding part protruding into each of the gaps, the two first protruding parts in the gap being staggered arranged in the first direction, and a word line plug being arranged on each of the first protruding parts, and an isolation structure being arranged between each of the first protruding parts and the adjacent source line.

[0006] Optionally, the first protruding part comprises a first part and a second part, the first part extending in a second direction, the second part extending in the first direction, one end of the first part being connected with the word line, the other end being connected with one end of the second part, and the word line plug being located on the second part.

[0007] Optionally, the second part extends in the first direction away from the adjacent source line.

[0008] Optionally, it further comprises a source line plug, the source line plug being located on the source line.

[0009] Optionally, the word line has a second protruding part protruding into each of the gaps, the second protruding part being located between each of the first protruding parts and the adjacent source line, and the second protruding part constituting the isolation structure.

[0010] Optionally, the second protruding part comprises a third part and a fourth part, the third part extends along the second direction, the fourth part extends along the first direction, one end of the third part is connected with the word line, and the other end is connected with one end of the fourth part.

[0011] Optionally, the fourth part extends away from or close to the adjacent source line along the first direction.

[0012] Optionally, the gap between the source line, the word line and the isolation structure is filled with a dielectric layer.

[0013] Optionally, the end of the source line has a sharp end, and the sharp end faces the word line plug.

[0014] Optionally, the sharp end does not extend beyond the side of the isolation structure away from the source line in the first direction.

[0015] The present application provides a layout structure of a semiconductor device, comprising: two word lines extending along a first direction, a plurality of source lines arranged along the first direction between the two word lines, a gap between adjacent two source lines, the word line has a first protruding part protruding into each gap, the two first protruding parts in the gap are arranged staggered in the first direction, and each first protruding part is provided with a word line plug, and an isolation structure is arranged between each first protruding part and the adjacent source line. The isolation structure isolates the source line and the word line plug, prevents the word line plug from being short-circuited with the source line when the position of the word line plug deviates, and avoids the leakage between the source line and the word line. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 It is a structural schematic diagram of I / O layout;

[0017] Figure 2 It is a scanning electron microscope (SEM) image of a layout structure of a semiconductor device;

[0018] Figure 3 It is Figure 2 It is a SEM image along the B-B' line section;

[0019] Figure 4 It is a schematic diagram of a layout structure of a semiconductor device provided by the first embodiment of the present application;

[0020] Figure 5 It is a schematic diagram of a layout structure of a semiconductor device provided by the second embodiment of the present application;

[0021] Figure 6 It is a schematic diagram of a layout structure of a semiconductor device provided by the third embodiment of the present application;

[0022] wherein the figure description is:

[0023] x - first direction; y - second direction;

[0024] 100, 200 - dielectric layer; 101, 201 - word line; 108, 202 - first protrusion; 102 - first part; 103 - second part; 104, 204 - word line plug; 105, 203 - source line; 106, 205 - source line plug; 107 - isolation structure; 109 - second protrusion. DETAILED DESCRIPTION

[0025] Figure 1 is a structural diagram of an I / O layout, Figure 2 is an electron microscope image of a semiconductor structure layout, as Figure 1 shown, the I / O (input / output) layout is composed of a plurality of I / O sub-layouts distributed side by side along the second direction y, according to process requirements, a plurality of adjacent I / O layouts need to be connected together to form a layout structure of a semiconductor device as Figure 2 shown, Figure 2 the layout structure of the semiconductor device shown includes two word lines 201 extending along the first direction x, a plurality of source lines 203 arranged along the first direction x between the two word lines 201, a gap between adjacent two source lines 203, a first protrusion 202 of the word line 201 protruding into the gap, two first protrusions 202 in the gap are arranged staggered in the first direction x, each source line 203 has a source line plug 205, and each first protrusion 202 has a word line plug 204.

[0026] In addition, the word line 201 and the source line 203 and the adjacent I / O sub-layout are filled with a dielectric layer 200, and the dielectric layer 100 between the word line 201 and the source line 203 also has a floating gate, and the corresponding I / O sub-layout in the I / O layout that needs to be connected shares the word line 201 and the floating gate,

[0027] as shown in the circle in Figure 2 Due to the shape limitation of the dielectric layer 200, a sharp tip will be formed during the formation of the source line 203, and the sharp tip is directed towards the word line plug 204, resulting in a relatively close distance between the source line 203 and the word line plug 204; and as the size of the semiconductor device continues to shrink, the process window for forming the word line plug 204 is also continuously shrinking, resulting in the word line plug 204 being prone to positional deviation during the formation process. Figure 3 is Figure 2 is an electron microscope image along the B-B' line section, as Figure 3As shown, when the position of the word line plug 204 is offset, the tip of the source line 203 will be short-circuited with the word line plug 204, causing the source line 203 to be short-circuited with the word line 201, which affects the performance of the semiconductor device.

[0028] The specific embodiments of the present application will be described below in detail with reference to the accompanying drawings. The advantages and features of the present application will be more apparent from the following description. It should be noted that the drawings are very simplified and are not drawn to scale, and are only used to facilitate and clarify the purpose of illustrating the embodiments of the present application.

[0029] Hereinafter, the terms "first", "second", and the like are used to distinguish between similar elements, and are not necessarily used to describe a particular order or time sequence. It should be understood that these terms as used herein can be replaced under appropriate circumstances. Similarly, if the method described herein includes a series of steps, and the steps presented herein are not necessarily the only order in which the steps can be performed, and some of the steps described can be omitted and / or other steps not described herein can be added to the method.

[0030] Embodiment One

[0031] Figure 4 The structural schematic diagram of the layout structure of the semiconductor device provided for this embodiment is shown in Figure 4 As shown, the layout structure of the semiconductor device provided in this embodiment includes two word lines 101 extending along a first direction x and a plurality of source lines 105 arranged along the first direction x between the two word lines 101. Wherein, there is a gap between two source lines 105, and a source line plug 106 is arranged on each source line 105; the word line 101 has a first protruding portion 108 protruding between each gap, the two first protruding portions 108 in the gap are arranged in staggered manner in the first direction x, and a word line plug 104 is arranged on the first protruding portion 108 of the word line 101; an isolation structure 107 is arranged between each first protruding portion 108 and the adjacent source line 105.

[0032] In addition, the source line 105, the word line 101, and the isolation structure 107 are filled with a dielectric layer 100, so as to insulate the source line 105 and the word line 101, and the dielectric layer 100 further has a floating gate.

[0033] In order to ensure the uniformity of the semiconductor device performance, the width of the floating gate is substantially the same everywhere, and the width of the dielectric layer 100 on the floating gate is also substantially the same everywhere. In the semiconductor manufacturing process, the dielectric layer 100 is generally formed first, and the source line material layer is filled in the trench formed in the dielectric layer 100 to form the source line 105. However, when two dielectric layers 100 approach each other, a sharp end will be formed at the intersection of the two dielectric layers 100. When the source line 105 is formed between the two dielectric layers 100, the end of the source line 105 will also form a sharp end, and the sharp end will face the word line plug 104. Therefore, the embodiment provides the isolation structure 107 between the source line 105 and the first protruding portion 102, so that the sharp end does not move away from the side of the source line 105 beyond the isolation structure 107 in the first direction x, thereby enhancing the isolation effect between the source line 105 and the word line plug 104, and avoiding short circuit between the word line plug 104 and the source line 105 when the position of the word line plug 104 deviates.

[0034] Referring back to Figure 4 , the first protruding portion 108 includes a first portion 102 and a second portion 103. The first portion 102 extends in the second direction y, and the second portion 103 extends in the first direction x. One end of the first portion 102 is connected to the word line 101, and the other end of the first portion 102 is connected to the second portion 103. The word line plug 104 is located on the second portion 103.

[0035] In the semiconductor structure forming process, the dielectric layer 100 is generally formed first, and then the word line material layer is deposited on the outside of the dielectric layer 100 to form the word line 101. Under the existing deposition process, the top surface of the word line 101 formed will have a slope. The height of the top surface of the word line 101 near the dielectric layer 100 is generally higher than the height of the top surface of the word line 101 away from the dielectric layer 100. When the word line plug 104 is formed on the sloped top surface of the word line 101, the position of the word line plug 104 is more likely to deviate, affecting the electrical connection effect between the word line plug 104 and the word line 101, and also increasing the probability of short circuit between the word line plug 104 and other structures.

[0036] In the embodiment, the second portion 103 and the first portion 102 extend in different directions, so that the contact area between the second portion 103 and the dielectric layer 100 is increased. The second portion 103 is in contact with the dielectric layer 100 around it. The dielectric layer 100 provides support for the word line material layer, reducing the slope of the top surface of the second portion 103, and thereby reducing the probability of position deviation of the word line plug 104.

[0037] In the embodiment, the second part 103 extends away from the source line 105, increasing the distance between the source line 105 and the word line plug 104, and enhancing the isolation effect between the word line plug 104 and the source line 105.

[0038] Embodiment two

[0039] Figure 5 A structural schematic diagram of a layout structure of a semiconductor device provided by the embodiment is shown in FIG. 2. The embodiment is different from the embodiment one in that, in the embodiment, the word line 101 has a second protruding part 109 protruding into each of the gaps, the second protruding part 109 extends along the second direction y, and the second protruding part 109 is located between each of the first protruding parts 108 and the end of the source line 105, the second protruding part 109 constituting the isolation structure 107. Figure 5

[0040] The second protruding part 109 is formed synchronously with the word line 101, saving the process steps.

[0041] Embodiment three

[0042] Figure 6 A structural schematic diagram of a layout structure of a semiconductor device provided by the embodiment is shown in FIG. 3. The embodiment is different from the embodiment two in that, in the embodiment, the second protruding part 109 has a third part and a fourth part, the third part extends along the second direction y, the fourth part extends along the first direction x, one end of the third part is connected with the word line 101, and the other end is connected with one end of the fourth part, the second protruding part constituting the isolation structure, and a dielectric layer 100 is filled between the second protruding part 109 and the first protruding part 108. The embodiment does not limit the extending direction of the fourth part, and the fourth part can extend away from or close to the source line 105 along the first direction x, further increasing the distance between the tip of the source line 105 and the word line plug 104, to enhance the isolation effect. Figure 6

[0043] ​​In summary, the application provides a layout structure of a semiconductor device, comprising two word lines 101 extending along a first direction x and a plurality of source lines 105 arranged along the first direction x between the two word lines 101. The two source lines 105 have a gap therebetween, and each source line 105 is provided with a source line plug 106. The word line 101 has a first protrusion 108 protruding between each gap, the two first protrusions 108 in the gap are arranged staggered in the first direction x, and the first protrusion 108 of the word line 101 is provided with a word line plug 104. Each first protrusion 108 is provided with an isolation structure 107 between the first protrusion 108 and the source line 105. The isolation structure 107 isolates the source line 105 and the word line plug 104, prevents the word line plug 104 from being short-circuited with the source line 105 when the word line plug 104 is shifted, and avoids the source line 105 and the word line 101 from being short-circuited.

[0044] The above is only the preferred embodiment of the application, and does not limit the application. Any person skilled in the art can make equivalent replacements, modifications or changes to the technical solutions and technical contents disclosed by the application without departing from the scope of the technical solutions of the application, and the application still falls within the protection scope of the application.

Claims

1. A layout structure for a semiconductor device, characterized in that, It includes two word lines extending along a first direction, and several source lines arranged along the first direction between the two word lines. There is a gap between two adjacent source lines. Each word line has a first protrusion protruding into each of the gaps. Two first protrusions in the gaps are staggered in the first direction, and each first protrusion is provided with a word line plug. Each first protrusion is provided with an isolation structure between itself and the adjacent source line.

2. The layout structure of a semiconductor device as described in claim 1, characterized in that, The first protrusion includes a first part and a second part. The first part extends along a second direction, and the second part extends along the first direction. One end of the first part is connected to the word line, and the other end is connected to one end of the second part. The word line plug is located on the second part.

3. The layout structure of a semiconductor device as described in claim 2, characterized in that, The second portion extends along the first direction in a direction away from the adjacent source line.

4. The layout structure of a semiconductor device as described in claim 1, characterized in that, It also includes a source plug located on the source line.

5. The layout structure of a semiconductor device as described in claim 1, characterized in that, The word line has a second protrusion that protrudes into each of the gaps, the second protrusion being located between each of the first protrusions and the adjacent source line, the second protrusion constituting the isolation structure.

6. The layout structure of a semiconductor device as described in claim 5, characterized in that, The second protrusion includes a third part and a fourth part. The third part extends along a second direction, and the fourth part extends along a first direction. One end of the third part is connected to the letter line, and the other end is connected to one end of the fourth part.

7. The layout structure of a semiconductor device as described in claim 6, characterized in that, The fourth portion extends along the first direction in a direction away from or close to the source line.

8. The layout structure of a semiconductor device as described in claim 1, characterized in that, The gaps between the source line, the word line, and the isolation structure are all filled with a dielectric layer.

9. The layout structure of a semiconductor device as described in claim 1, characterized in that, The source line has a pointed end that faces the word line plug.

10. The layout structure of a semiconductor device as described in claim 9, characterized in that, The tip does not extend beyond the side of the isolation structure away from the source line in the first direction.

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