An impedance matching circuit for a memory

Abstract

This invention discloses an impedance matching circuit for a memory. The circuit includes a resistance matching module, a resistance implementation module, and a controller. The resistance matching module connects the output line of the controller to the DQ line of the memory, so that the resistance of the DQ line of the memory is applied to the output line of the controller. The controller obtains the optimal resistance value applied to the DQ line of the memory as the matching resistance value. Based on the matching resistance value, the controller outputs a control signal to the resistance implementation module to control a first resistor connected to the address line of the memory and a second resistor connected to the data line of the memory. This circuit achieves resistance matching for the address line and data line of the memory respectively, meeting the requirements for different impedance matching of the address line and control, improving signal integrity, and avoiding difficulties in high-speed data transmission and distortion of output data.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and more specifically, to an impedance matching circuit for a memory. Background Technology

[0002] In current home communication devices, in order to eliminate signal reflection from the memory and increase voltage and timing margin, impedance matching of the memory is mostly achieved by series matching of a single resistor or wired matching.

[0003] Current impedance matching methods offer relatively simple impedance matching capabilities. However, due to variations in copper thickness and surface roughness during the manufacturing process of memory chips, the circuit impedance cannot reach a uniform standard, resulting in certain errors. In such cases, a single impedance matching system cannot adequately meet the impedance matching requirements, leading to impedance mismatch at the interface lines, which in turn causes difficulties in high-speed data transmission and distortion of output data. Summary of the Invention

[0004] To address the aforementioned problems, this invention proposes an impedance matching circuit for a memory, which can dynamically adjust the matching resistor of the memory impedance matching, improve signal integrity, and avoid difficulties in high-speed data transmission and distortion of output data.

[0005] This invention provides an impedance matching circuit for a memory, the circuit comprising: a resistance matching module, a resistance implementation module, and a controller;

[0006] The resistance matching module is used to connect the output line of the controller to the DQ line of the memory, so that the resistance of the DQ line of the memory is applied to the output line of the controller.

[0007] The controller sends a step signal through the output line and collects the reflected signal on its output line. By controlling the mode register of the memory, it changes the resistance value of the DQ line loaded in the memory so that the waveform of the reflected signal matches the waveform of the step signal. The resistance value of the DQ line loaded in the memory is obtained as the matching resistance value.

[0008] The controller outputs a control signal to the resistance implementation module according to the matched resistance value, thereby controlling the first resistor connected to the address line of the memory and the second resistor connected to the data line of the memory.

[0009] Preferably, the resistance matching module includes a first switching unit, a second switching unit, a third switching unit, and a fourth switching unit;

[0010] The input terminal of the first switching unit serves as the first input terminal of the resistance matching module and is connected to the output line of the controller; the output terminal of the first switching unit serves as the output terminal of the resistance matching module and is connected to the DQ line of the memory; the control terminal of the first switching unit serves as the first control signal terminal of the resistance matching module.

[0011] The input terminal of the second switching unit serves as the second input terminal of the resistance matching module and is connected to the DQ line of the controller; the output terminal of the second switching unit is connected to the output terminal of the first switching unit; the control terminal of the second switching unit serves as the second control signal terminal of the resistance matching module.

[0012] The input terminal of the third switching unit is connected to the input terminal of the first switching unit, and the output terminal of the third switching unit is grounded; the control terminal of the third switching unit serves as the third control signal terminal of the resistance matching module.

[0013] The input terminal of the fourth switching unit is connected to the input terminal of the second switching unit, and the output terminal of the fourth switching unit is grounded; the control terminal of the fourth switching unit serves as the fourth control signal terminal of the resistance matching module.

[0014] As an improvement to the above scheme, the controller outputs a high-level signal to the first control signal terminal and the fourth control signal terminal, and outputs a low-level signal to the second control signal terminal and the third control signal terminal, so that the output line of the controller is connected to the DQ line of the memory, and the DQ line of the controller is grounded.

[0015] As a preferred embodiment, the circuit further includes an analog-to-digital converter module;

[0016] The controller is connected to its output line through the analog-to-digital converter module, and collects the reflected signal of the step signal output by its output line reflected back through the DQ line of the memory.

[0017] Preferably, the controller controls the mode register to set the resistance value of the DQ line loaded from the memory to a preset initial value;

[0018] A step signal is sent through the output line, and the reflected signal on the output line is collected.

[0019] The waveform of the received reflected signal is detected, and the detected waveform is compared with the waveform of the step signal to see if they are the same.

[0020] When the detected waveform is different from the waveform of the step signal, it is determined that the received reflected signal does not match the waveform of the step signal. The mode register is controlled to change the resistance value of the DQ line loaded in the memory, and the waveform of the received reflected signal is detected again. When the detected waveform is different from the waveform of the step signal, the mode register is controlled to change the resistance value of the DQ line loaded in the memory again until the detected waveform is the same as the waveform of the step signal.

[0021] When the detected waveform is the same as the waveform of the step signal, the resistance value of the DQ line loaded in the memory is obtained as the matching resistance value.

[0022] Preferably, the resistance value realization module includes a first resistance value unit and a second resistance value unit;

[0023] The first resistance unit includes m switch subunits and m resistor subunits. The input terminal of the i-th switch subunit is connected to the first terminal of the i-th resistor subunit. The second terminal of the i-th resistor subunit serves as the input terminal of the first resistance unit and as the first input terminal of the resistance implementation module, and is connected to the first power supply terminal of the controller. The control terminal of the i-th switch subunit serves as the control terminal of the first resistance unit and as the first control terminal of the resistance implementation module, and is connected to the high-level output terminal of the controller. The output terminal of the i-th switch subunit serves as the output terminal of the first resistance unit and as the first output terminal of the resistance implementation module, and is connected to the address line of the memory.

[0024] The second resistance unit includes n switch subunits and n resistor subunits. The input terminal of the j-th switch subunit is connected to the first terminal of the j-th resistor subunit. The second terminal of the j-th resistor subunit serves as the input terminal of the second resistance unit and as the second input terminal of the resistance implementation module, and is connected to the second power supply terminal of the controller. The control terminal of the j-th switch subunit serves as the control terminal of the second resistance unit and as the second control terminal of the resistance implementation module, and is connected to the first level output terminal of the controller. The output terminal of the j-th switch subunit serves as the output terminal of the second resistance unit and as the second output terminal of the resistance implementation module, and is connected to the data line of the memory.

[0025] Where m, n≥2, i=1,2…m, j=1,2…n.

[0026] Furthermore, any of the resistor sub-units of the first resistance unit is an impedance device composed of several resistors connected in series and parallel, a polysilicon resistor, or a variable resistor.

[0027] Each of the second resistance units is an impedance device composed of several resistors connected in series and parallel, a polysilicon resistor, or a variable resistor.

[0028] As a parallel solution to the above scheme, any switching sub-unit of the first resistance unit is a transistor, a MOSFET, or a field-effect transistor.

[0029] Any of the switching sub-units of the second resistance unit is a transistor, MOSFET, or field-effect transistor.

[0030] Preferably, the output lines of the controller are address lines or data lines.

[0031] Preferably, the memory is DDR3 DRAM, and the controller is a DDR3 DRAM controller.

[0032] This invention provides an impedance matching circuit for a memory, comprising: a resistance matching module, a resistance implementation module, and a controller; the resistance matching module connects the output line of the controller to the DQ line of the memory, so that the resistance of the DQ line of the memory is applied to the output line of the controller; the controller sends a step signal through the output line and collects the reflected signal on its output line, and changes the resistance value applied to the DQ line of the memory by controlling the mode register of the memory, so that the waveform of the reflected signal matches the waveform of the step signal, and obtains the resistance value applied to the DQ line of the memory as the matching resistance value; the controller outputs a control signal to the resistance implementation module according to the matching resistance value, controlling the first resistor connected to the address line of the memory and the second resistor connected to the data line of the memory. The corresponding output signal is retrieved from a preset resistance and output signal table based on the matching resistance value and output signal. The signal is then output to the resistance implementation module, which controls the first resistor of the resistance implementation unit connected to the address lines of the memory to achieve impedance matching of the address lines. The module also controls the second resistor of the resistance implementation unit connected to the data lines of the memory to achieve impedance matching of the data lines. The resistance implementation module can achieve impedance matching of the address lines and data lines of the memory respectively, meeting the needs of address lines and controlling different impedance matching, improving signal integrity, and avoiding difficulties in high-speed data transmission and distortion of output data. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the impedance matching circuit of a memory provided in an embodiment of the present invention;

[0034] Figure 2 This is a schematic diagram of the structure of a resistance matching module provided in an embodiment of the present invention;

[0035] Figure 3This is a schematic diagram of the resistance implementation module provided in an embodiment of the present invention. Detailed Implementation

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] Example 1

[0038] See Figure 1 This is a schematic diagram of the impedance matching circuit of a memory provided in an embodiment of the present invention. The circuit includes: a resistance matching module, a resistance implementation module, and a controller.

[0039] The resistance matching module is used to connect the output line of the controller to the DQ line of the memory, so that the resistance of the DQ line of the memory is applied to the output line of the controller.

[0040] The controller generates a step signal and outputs it to the DQ line of the memory via the output line and the resistance matching module. The mode register of the memory is pre-configured with a preset resistance value on the termination resistor of the DQ line. After reflection by the DQ line of the memory, the controller detects the reflected signal, and the resistance value information of the termination resistor is loaded on the reflected signal.

[0041] Adding a termination resistor to the farthest branch end to absorb reflections and improve signal integrity is an economical and compromise solution. By adopting this solution, DDR3 can improve signal quality while providing higher signal transmission rates and enhancing the scalability of the memory system.

[0042] By observing the waveform of the reflected signal, it is possible to determine whether the resistance value of the terminating resistor is appropriate, thus minimizing the impedance mismatch of the line. By adjusting the resistance on the DQ line through the mode register, the waveform of the reflected signal can be matched with that of the step signal, and the resistance value of the DQ line loaded in the memory can be obtained as the matching resistance value.

[0043] By matching the signal waveform of the controller, the impedance value with the smaller impedance mismatch can be determined as the matching resistance value;

[0044] The corresponding output signal is retrieved from a preset resistance and output signal table based on the matching resistance value and output signal. The signal is then output to the resistance implementation module, which controls the first resistor of the resistance implementation unit connected to the address lines of the memory to achieve impedance matching of the address lines. The module also controls the second resistor of the resistance implementation unit connected to the data lines of the memory to achieve impedance matching of the data lines. The resistance implementation module can achieve impedance matching of the address lines and data lines of the memory respectively, meeting the needs of address lines and controlling different impedance matching, improving signal integrity, and avoiding difficulties in high-speed data transmission and distortion of output data.

[0045] Example 2

[0046] See Figure 2 This is a schematic diagram of a resistance matching module provided in an embodiment of the present invention; the resistance matching module includes a first switching unit Q1, a second switching unit Q2, a third switching unit Q3, and a fourth switching unit Q4;

[0047] The input terminal of the first switching unit Q1 serves as the first input terminal IN1 of the resistance matching module and is connected to the output line of the controller; the output terminal of the first switching unit Q1 serves as the output terminal OUT of the resistance matching module and is connected to the DQ line of the memory; the control terminal of the first switching unit Q1 serves as the first control signal terminal C1 of the resistance matching module.

[0048] The input terminal of the second switching unit Q2 serves as the second input terminal IN2 of the resistance matching module and is connected to the DQ line of the controller; the output terminal of the second switching unit Q2 is connected to the output terminal of the first switching unit Q1; the control terminal of the second switching unit Q2 serves as the second control signal terminal C2 of the resistance matching module.

[0049] The input terminal of the third switch unit Q3 is connected to the input terminal of the first switch unit Q1, and the output terminal of the third switch unit Q3 is grounded; the control terminal of the third switch unit Q3 serves as the third control signal terminal C3 of the resistance matching module.

[0050] The input terminal of the fourth switch unit Q4 is connected to the input terminal of the second switch unit Q2, and the output terminal of the fourth switch unit Q4 is grounded; the control terminal of the fourth switch unit Q4 serves as the fourth control signal terminal C4 of the resistance matching module.

[0051] By controlling the potential of the first control signal terminal C1, the second control signal terminal C2, the third control signal terminal C3, and the fourth control signal terminal C4, the connection relationship between the first input terminal / second input terminal and the output terminal of the impedance matching unit can be changed.

[0052] Example 3

[0053] Based on the above embodiments, in another embodiment of the present invention, the controller outputs a high-level signal to the first control signal terminal C1 and the fourth control signal terminal C4, and outputs a low-level signal to the second control signal terminal C2 and the third control signal terminal C3, so that the first switch unit Q1 and the fourth switch unit Q4 are turned on, the second switch unit Q2 and the third switch unit Q3 are turned off, the output line of the controller is connected to the DQ line of the memory, and the DQ line of the controller is grounded.

[0054] It should be noted that, in other embodiments, the controller outputs a high-level signal to the second control signal terminal C2 and the third control signal terminal C3, and outputs a low-level signal to the first control signal terminal C1 and the fourth control signal terminal C4, so that the first switch unit Q1 and the fourth switch unit Q4 are turned off, the second switch unit Q2 and the third switch unit Q3 are turned on, the controller's DQ line is connected to the memory's DQ line, and the controller's output line is grounded.

[0055] After the controller and memory are initialized, the controller controls the control signal terminal of the resistance matching module, which enables the controller's output line to be connected to the DQ line of the memory.

[0056] By controlling the control signal terminal of the resistance matching module, the controller's output line can be connected to the DQ line of the memory, so that the resistance of the memory's DQ line is applied to the controller's output line.

[0057] Example 4

[0058] In another embodiment provided by the present invention, the circuit further includes an analog-to-digital conversion module;

[0059] The controller is connected to its output line through the analog-to-digital converter module. It collects the reflected signal of the step signal output by the output line and the reflected signal reflected back by the DQ line of the memory. It can convert the analog signal reflected by the DQ line into a digital signal, eliminate the noise generated in the reflection, and facilitate signal matching and comparison.

[0060] Example 5

[0061] In another embodiment provided by the present invention, the process of the controller determining the matching resistance value includes:

[0062] After the controller and memory have completed initialization, the mode register controls the resistance value of the DQ line loaded by the memory to a preset initial value ZQ.

[0063] A step signal with a voltage amplitude of 1V is sent through the output line, and the reflected signal on the output line is collected.

[0064] The waveform of the received reflected signal is detected, and the detected waveform is compared with the waveform of the step signal to see if they are the same.

[0065] When the detected waveform is different from the waveform of the step signal, that is, when the amplitude of the waveform changes significantly and the error is outside the preset range, or when the waveform generates an oscillation signal, it is determined that the received reflected signal does not match the waveform of the step signal. The mode register is then controlled to change the resistance value of the DQ line loaded in the memory. The resistance value of the DQ line is adjusted by the mode register to ZQ / 2, ZQ / 3, ZQ / 4, ZQ / 5, ZQ / 6, ZQ / 7, etc., so as to find a suitable resistance value to minimize impedance mismatch.

[0066] The waveform of the received reflected signal is detected again. When the detected waveform is not the same as the waveform of the step signal, the mode register is controlled to change the resistance value of the DQ line loaded in the memory again until the detected waveform is the same as the waveform of the step signal.

[0067] When the detected waveform is the same as the waveform of the step signal, the resistance value of the DQ line loaded in the memory is obtained as the matching resistance value.

[0068] By comparing the reflected signal and the step signal with the controller, the impedance of the DQ line can be adjusted to achieve optimal impedance matching. This allows the system to adapt to impedance differences caused by different board materials and board manufacturers, ensuring that each product is in the best impedance matching state.

[0069] Example 6

[0070] See Figure 3 This is a schematic diagram of the resistance implementation module provided in an embodiment of the present invention; the resistance implementation module includes a first resistance unit and a second resistance unit; the first resistance unit is used to implement impedance matching of the address lines of the memory, and the second resistance unit is used to implement impedance matching of the data lines of the memory;

[0071] The first resistance unit includes four switch subunits, namely the first switch subunit Q1', the second switch subunit Q2', the third switch subunit Q3' and the fourth switch subunit Q4'. The first resistance unit also includes four resistor subunits, namely the first resistor subunit R1, the second resistor subunit R2, the third resistor subunit R3 and the fourth resistor subunit R4. The resistance value of each resistor subunit is different.

[0072] The input terminal of the first switch subunit Q1' is connected to the first terminal of the first resistor subunit R1. The second terminal of the first resistor subunit R1 serves as the input terminal of the first resistance value unit and as the first input terminal in1 of the resistance value implementation module, and is connected to the first power supply terminal VDDQ1 of the controller. The control terminal of the first switch subunit Q1' serves as the control terminal of the first resistance value unit and as the first control terminal c1 of the resistance value implementation module, and is connected to the high-level output terminal VOH of the controller. The output terminal of the first switch subunit Q1' serves as the output terminal of the first resistance value unit and as the first output terminal out1 of the resistance value implementation module, and is connected to the address line address of the memory.

[0073] The input terminal of the second switch subunit Q2' is connected to the input terminal of the first resistance unit through the second resistor subunit R2. The control terminal of the second switch subunit Q2' serves as the control terminal of the first resistance unit, and the output terminal of the second switch subunit Q2' serves as the output terminal of the first resistance unit.

[0074] The input terminal of the third switch subunit Q3' is connected to the input terminal of the first resistance unit through the third resistor subunit R3. The control terminal of the third switch subunit Q3' serves as the control terminal of the first resistance unit, and the output terminal of the third switch subunit Q3' serves as the output terminal of the first resistance unit.

[0075] The input terminal of the fourth switch subunit Q4' is connected to the input terminal of the first resistance unit through the fourth resistor subunit R4. The control terminal of the fourth switch subunit Q4' serves as the control terminal of the first resistance unit, and the output terminal of the fourth switch subunit Q4' serves as the output terminal of the first resistance unit.

[0076] The second resistance unit includes four switch sub-units, namely the fifth switch sub-unit Q5', the sixth switch sub-unit Q6', the seventh switch sub-unit Q7' and the eighth switch sub-unit Q8'. The second resistance unit also includes four resistor sub-units, namely the fifth resistor sub-unit R5, the sixth resistor sub-unit R6, the seventh resistor sub-unit R7 and the eighth resistor sub-unit R8. The resistance value of each resistor sub-unit is different.

[0077] The input terminal of the fifth switch subunit Q5' is connected to the first terminal of the fifth resistor subunit R5. The second terminal of the fifth resistor subunit R5 serves as the input terminal of the second resistance value unit and as the second input terminal in2 of the resistance value realization module, and is connected to the second power supply terminal VDDQ2 of the controller. The control terminal of the fifth switch subunit Q5' serves as the control terminal of the second resistance value unit and as the second control terminal c2 of the resistance value realization module, and is connected to the low-level output terminal VOL of the controller. The output terminal of the fifth switch subunit Q5' serves as the output terminal of the second resistance value unit and as the second output terminal out2 of the resistance value realization module, and is connected to the data line date of the memory.

[0078] The input terminal of the sixth switch subunit Q6' is connected to the input terminal of the second resistance unit through the sixth resistor subunit R6. The control terminal of the sixth switch subunit Q6' serves as the control terminal of the second resistance unit, and the output terminal of the sixth switch subunit Q6' serves as the output terminal of the second resistance unit.

[0079] The input terminal of the seventh switch subunit Q7' is connected to the input terminal of the second resistance unit through the seventh resistor subunit R7. The control terminal of the seventh switch subunit Q7' serves as the control terminal of the second resistance unit, and the output terminal of the seventh switch subunit Q7' serves as the output terminal of the second resistance unit.

[0080] The input terminal of the eighth switch subunit Q8' is connected to the input terminal of the second resistance unit through the eighth resistor subunit R8. The control terminal of the eighth switch subunit Q8' serves as the control terminal of the second resistance unit, and the output terminal of the eighth switch subunit Q8' serves as the output terminal of the second resistance unit.

[0081] The voltage signal input to the first control terminal of the module is realized by the resistance value, and different switch sub-units in the first resistance unit are turned on respectively. The different resistance sub-units are connected to the address lines to realize the impedance matching of the address lines.

[0082] The voltage signal input to the second control terminal of the module is achieved by using the resistance value, which is used to match the conduction of different switch sub-units in the second resistance unit. Different resistance sub-units are then connected to the address lines to achieve impedance matching of the data lines.

[0083] It should be noted that the control voltage of the first or second resistance unit can control at least one of the switching sub-units to be turned on, thereby connecting the corresponding resistance sub-unit to the circuit; when two or more switching sub-units are turned on, the turned resistance sub-units are connected in parallel to the circuit.

[0084] It should be noted that in this embodiment, the specific connection relationship is illustrated by taking four switch sub-units and four resistor sub-units in both the first and second resistance units. In other embodiments, the number of switch sub-units and resistor sub-units in the first and second resistance units can be other numbers. The more switch sub-units and resistor sub-units used, the higher the accuracy of the resistance can be achieved.

[0085] Example 7

[0086] In another embodiment provided by the present invention, any one of the resistor sub-units in the first resistance unit can be any of the following resistor devices: an impedance device composed of several resistors connected in series and parallel, a polysilicon resistor, or a variable resistor.

[0087] Any of the following resistor sub-units in the second resistance unit can be a resistor device: an impedance device composed of several resistors connected in series and parallel, a polysilicon resistor, or a variable resistor.

[0088] Impedance devices composed of several resistors connected in series and parallel can improve the resistance accuracy of the resistor subunit. By using polysilicon resistors or variable resistors, stepless resistance changes can be achieved, thereby improving the accuracy of impedance matching.

[0089] Example 8

[0090] In another embodiment of the present invention, any of the switching sub-units of the first resistance unit may be any of the following switching devices: transistor, MOSFET or field-effect transistor.

[0091] Any of the following switching devices can be used in the second resistance unit: transistor, MOSFET, or field-effect transistor.

[0092] Using switching transistors such as triodes, MOSFETs, or field-effect transistors provides excellent conduction performance, high stability, and low circuit cost.

[0093] Example 9

[0094] In another embodiment provided by the present invention, the output line of the controller is an address line or a data line;

[0095] The controller can output a step potential signal via address lines or data lines.

[0096] Example 10

[0097] In another embodiment of the present invention, the memory is DDR3 DRAM and the controller is a DDR3 DRAM controller.

[0098] DDR3 DRAM memory has a clock rate of 800MHz, a very fast signal transmission rate, and also has high security and reliability. Signal integrity has a great impact on the performance of DDR3 DRAM memory. By using a matching resistor that dynamically adjusts the impedance matching of the memory, the accuracy of the matching resistor can be guaranteed.

[0099] It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this invention, and these improvements and modifications are also considered to be within the scope of protection of this invention.

Claims

1. An impedance matching circuit for a memory, characterized in that, The circuit includes: a resistance matching module, a resistance implementation module, and a controller; The resistance matching module is used to connect the output line of the controller to the DQ line of the memory, so that the resistance of the DQ line of the memory is applied to the output line of the controller. The controller sends a step signal through the output line and collects the reflected signal on its output line. By controlling the mode register of the memory, it changes the resistance value of the DQ line loaded in the memory so that the waveform of the reflected signal matches the waveform of the step signal. The resistance value of the DQ line loaded in the memory is obtained as the matching resistance value. The controller outputs a control signal to the resistance implementation module according to the matched resistance value, thereby controlling the first resistor connected to the address line of the memory and the second resistor connected to the data line of the memory.

2. The impedance matching circuit for the memory according to claim 1, characterized in that, The resistance matching module includes a first switching unit, a second switching unit, a third switching unit, and a fourth switching unit; The input terminal of the first switching unit serves as the first input terminal of the resistance matching module and is connected to the output line of the controller; the output terminal of the first switching unit serves as the output terminal of the resistance matching module and is connected to the DQ line of the memory; the control terminal of the first switching unit serves as the first control signal terminal of the resistance matching module. The input terminal of the second switching unit serves as the second input terminal of the resistance matching module and is connected to the DQ line of the controller; the output terminal of the second switching unit is connected to the output terminal of the first switching unit; the control terminal of the second switching unit serves as the second control signal terminal of the resistance matching module. The input terminal of the third switching unit is connected to the input terminal of the first switching unit, and the output terminal of the third switching unit is grounded; the control terminal of the third switching unit serves as the third control signal terminal of the resistance matching module. The input terminal of the fourth switching unit is connected to the input terminal of the second switching unit, and the output terminal of the fourth switching unit is grounded; the control terminal of the fourth switching unit serves as the fourth control signal terminal of the resistance matching module.

3. The impedance matching circuit for the memory according to claim 2, characterized in that, The controller outputs a high-level signal to the first control signal terminal and the fourth control signal terminal, and outputs a low-level signal to the second control signal terminal and the third control signal terminal, so that the output line of the controller is connected to the DQ line of the memory, and the DQ line of the controller is grounded.

4. The impedance matching circuit for the memory according to claim 1, characterized in that, The circuit also includes an analog-to-digital conversion module; The controller is connected to its output line through the analog-to-digital converter module, and collects the reflected signal of the step signal output by its output line reflected back through the DQ line of the memory.

5. The impedance matching circuit for the memory according to claim 1, characterized in that, The controller controls the mode register to set the resistance value of the DQ line loaded from the memory to a preset initial value; A step signal is sent through the output line, and the reflected signal on the output line is collected. The waveform of the received reflected signal is detected, and the detected waveform is compared with the waveform of the step signal to see if they are the same. When the detected waveform is different from the waveform of the step signal, it is determined that the received reflected signal does not match the waveform of the step signal. The mode register is controlled to change the resistance value of the DQ line loaded in the memory, and the waveform of the received reflected signal is detected again. When the detected waveform is different from the waveform of the step signal, the mode register is controlled to change the resistance value of the DQ line loaded in the memory again until the detected waveform is the same as the waveform of the step signal. When the detected waveform is the same as the waveform of the step signal, the resistance value of the DQ line loaded in the memory is obtained as the matching resistance value.

6. The impedance matching circuit for the memory according to claim 1, characterized in that, The resistance value implementation module includes a first resistance value unit and a second resistance value unit; The first resistance unit includes m switch subunits and m resistor subunits. The input terminal of the i-th switch subunit is connected to the first terminal of the i-th resistor subunit. The second terminal of the i-th resistor subunit serves as the input terminal of the first resistance unit and as the first input terminal of the resistance implementation module, and is connected to the first power supply terminal of the controller. The control terminal of the i-th switch subunit serves as the control terminal of the first resistance unit and as the first control terminal of the resistance implementation module, and is connected to the high-level output terminal of the controller. The output terminal of the i-th switch subunit serves as the output terminal of the first resistance unit and as the first output terminal of the resistance implementation module, and is connected to the address line of the memory. The second resistance unit includes n switch subunits and n resistor subunits. The input terminal of the j-th switch subunit is connected to the first terminal of the j-th resistor subunit. The second terminal of the j-th resistor subunit serves as the input terminal of the second resistance unit and as the second input terminal of the resistance implementation module, and is connected to the second power supply terminal of the controller. The control terminal of the j-th switch subunit serves as the control terminal of the second resistance unit and as the second control terminal of the resistance implementation module, and is connected to the first level output terminal of the controller. The output terminal of the j-th switch subunit serves as the output terminal of the second resistance unit and as the second output terminal of the resistance implementation module, and is connected to the data line of the memory. Where m, n≥2, i=1,2…m, j=1,2…n.

7. The impedance matching circuit for the memory according to claim 6, characterized in that, Any of the first resistance sub-units is an impedance device composed of several resistors connected in series and parallel, a polysilicon resistor, or a variable resistor. Each of the second resistance units is an impedance device composed of several resistors connected in series and parallel, a polysilicon resistor, or a variable resistor.

8. The impedance matching circuit for the memory according to claim 6, characterized in that, Any of the switching sub-units of the first resistance unit is a transistor, a MOSFET, or a field-effect transistor; Any of the switching sub-units of the second resistance unit is a transistor, MOSFET, or field-effect transistor.

9. The impedance matching circuit for the memory according to claim 1, characterized in that, The output lines of the controller are address lines or data lines.

10. The impedance matching circuit of the memory according to claim 1, characterized in that, The memory is DDR3 DRAM, and the controller is a DDR3 DRAM controller.

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