A method for forming a conductive line for improving the electrical performance of a packaged semiconductor chip package

Abstract

The present invention discloses a method for forming a conductive connection line for improving the electrical performance of a semiconductor chip package. A first dielectric layer is coated on the surface of the chip pad; a photoresist is used and exposed and developed to form grooves for each pad on the first dielectric layer, and a conductive metal is filled in the grooves to respectively form each first conductive connection line; a conductive metal is sputtered in and around each line groove to respectively form each second conductive connection line, and then a metal stripping process is performed on the surface. Then, a conductive metal is coated and wrapped on the surface of the second conductive connection line, and a second dielectric layer is coated on the first dielectric layer and each third conductive connection line; a photoresist is used to form grooves by exposure and development; the grooves are filled with a conductive metal to respectively form solder joints; therefore, the electrical performance is improved, the power consumption is reduced, the process efficiency is improved, the chip package has high density, and the overall structure is more compact.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and particularly relates to a method for forming a conductive connection line for improving the electrical properties of a semiconductor chip package in a semiconductor chip package. Background Art

[0002] Semiconductor packaging refers to the process of processing wafers that have passed testing into independent chips according to product models and functional requirements. The packaging process is as follows: wafers from the previous process of the wafer are cut into small chips (Dies) through a dicing process, and then the cut chips are attached to the islands of the corresponding substrate (lead frame) with glue. Then, ultra-fine metal (gold, tin, copper, aluminum) wires or conductive resins are used to connect the bonding pads of the chips to the corresponding pins (Leads) of the substrate to form the required circuit; then, the independent chips are encapsulated and protected with a plastic shell. After plastic encapsulation, a series of operations are also required. After packaging is completed, final product testing is carried out, usually through processes such as incoming inspection, testing, and packing. Finally, it is warehoused and shipped.

[0003] In the solution disclosed in CN201210514307: three dielectric layers are coated, and a conductive metal is introduced into the grooves to form a conductive connection line; three dielectric layers need to be coated, the process is more complicated and the working hours are more, and the thickness of the chip increases, which is not conducive to high density and small volume of the chip. In current practice, thick silver paste is also mostly used to form the intermediate layer conductive connection line, and the poor electrical properties and high resistivity also lead to more power consumption and more heat generation of the chip, unable to keep up with the current realistic requirements; and a conductive layer plated with gold needs to be plated on the conductive connection line formed by the silver paste to ensure better conductivity and fusion; and the solder joints are all formed of metal of general material to form semi-circular solder joints, which cannot meet the anisotropic conductive adhesive ACF / ACP process. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the existing defects and provide a method for forming a conductive connection line for improving the electrical properties of a semiconductor chip package in a semiconductor chip package to solve the problems raised in the above background art.

[0005] To achieve the above object, the present invention provides the following technical solution: A method for forming a conductive connection line for improving the electrical properties of a semiconductor chip package, the semiconductor chip package is mounted and combined on a substrate to be electrically connected to a plurality of solder joints arranged on the substrate, including:

[0006] A semiconductor chip having a pad surface provided with a plurality of pads;

[0007] At least one dielectric layer is coated on the pad surface of the semiconductor chip;

[0008] And at least one conductive connection line, which is disposed in the dielectric layer, and one end of each conductive connection line is electrically connected to a pad on the semiconductor chip respectively, and the other end extends outward and is exposed outside the dielectric layer to form a solder joint for electrically connecting to a solder joint pre-arranged on a substrate, so that the semiconductor chip is mounted and combined on the substrate; characterized in that the method for forming the conductive connection line comprises the following steps:

[0009] S1: Coating a first dielectric layer on the surface of the pads of the semiconductor chip;

[0010] S2: Using photoresist and by exposure and development to form grooves for each pad on the surface of the first dielectric layer, so that each pad can be exposed outward through each groove;

[0011] S3: Filling conductive metal in each line groove to respectively form each first conductive connection line;

[0012] S4: Sputtering conductive metal on the inner and outer sides of each line groove to respectively form each second conductive connection line and form new grooves;

[0013] S5: Performing a metal stripping process on the surface of the second conductive connection line and the surface of the first dielectric layer;

[0014] S6: Coating and wrapping conductive metal on the surface of the second conductive connection line to respectively form each third conductive connection line;

[0015] S7: Coating a second dielectric layer on the first dielectric layer and each third conductive connection line;

[0016] S8: Using photoresist and by exposure and development to respectively form grooves connected to one end of each third conductive connection line on the second dielectric layer;

[0017] S9: Filling conductive metal in each groove to respectively form a solder joint, and the solder joint is exposed outside the second dielectric layer for respectively electrically connecting to each pad of the chip.

[0018] Preferably, the coating method of the first and second dielectric layers is spin coating.

[0019] Preferably, in S3, when filling conductive metal, electroless nickel immersion gold is used.

[0020] Preferably, in S6, when coating conductive metal, electroless nickel immersion gold or immersion silver is used.

[0021] Preferably, the thickness of the second conductive connection line is 0.03 microns.

[0022] Preferably, the solder joints exposed outside the second dielectric layer form a hemispherical shape protruding from the outer surface of the second dielectric layer or a metal layer form with the top parallel to the second dielectric layer.

[0023] Preferably, when the solder joints are in the form of a metal layer parallel to the second dielectric layer, electroless nickel immersion gold is used to form them.

[0024] Compared with the prior art, the present invention provides a method for forming a conductive connection line for improving the electrical performance of a semiconductor chip package, and has the following beneficial effects:

[0025] 1. In the present invention, sputtering a conductive metal is used to replace the relatively traditional silver paste / silver glue process, which has a lower resistivity, better improves the electrical conduction effect, reduces the chip power consumption, and further enables the temperature during chip operation to be kept lower.

[0026] 2. In the present invention, sputtering a conductive metal is used to replace the relatively thick silver paste / silver glue process, which saves materials and reduces costs; after the chip is discarded, theoretically, part of the electronic waste is reduced.

[0027] 3. In the present invention, sputtering a conductive metal is used to replace the relatively traditional silver paste / silver glue process, which reduces the spin coating of the dielectric layer once in the process; improves the process efficiency and enhances the production capacity.

[0028] 4. In the packaging method of the present invention, the traditional wire bonding and the process of flipping the wafer onto the substrate are miniaturized, and the circuit is directly made on the wafer to minimize the circuit length and achieve the best electrical performance; moreover, the process of wire bonding is saved, and the structure of flipping the wafer onto the substrate is more optimized.

[0029] 5. The conductive connection line of the present invention is more optimized and flexible, has a larger available wiring space and higher utilization rate, avoids over-large wafer packaging, and can better achieve high-density chip packaging, a more compact overall structure, and a higher finished product qualification rate.

[0030] 6. When the solder joints of the present invention are in the form of a metal layer parallel to the second dielectric layer, electroless nickel immersion gold is used to form them, which can meet the requirements of the anisotropic conductive adhesive ACF / ACP process in the existing needs and has a wider application range. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The drawings are used to provide a further understanding of the present invention, and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation to the present invention. In the drawings:

[0032] Figure 1-2 It is a schematic diagram of S1 in the forming method proposed by the present invention;

[0033] Figure 3Schematic diagram of S2 in the formation method proposed by the present invention;

[0034] Figure 4 Schematic diagram of S3 in the formation method proposed by the present invention;

[0035] Figure 5 Schematic diagram of S4 in the formation method proposed by the present invention;

[0036] Figure 6 Schematic diagram of S6 in the formation method proposed by the present invention;

[0037] Figure 7 Schematic diagram of S7 in the formation method proposed by the present invention;

[0038] Figure 8 Schematic diagram of S8 in the formation method proposed by the present invention;

[0039] Figure 9 Schematic diagram of S9 in the formation method proposed by the present invention (hemispherical solder joint);

[0040] Figure 10 Schematic diagram of S9 in the formation method proposed by the present invention (solder joint in the form of a metal layer);

[0041] In the figure: 10. Semiconductor chip 11. Bond pad 12. Bond pad surface 20. First dielectric layer 21. Groove 211. Groove 22. First conductive line 32. Second conductive line 31. New groove 42. Third conductive line 40. Second dielectric layer 41. Groove 51. Solder joint (for details of grooves with repeated names, please refer to the legend) Detailed implementation

[0042] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0043] Please refer to Figure 1-10 , the present invention provides the following technical solutions: A method for forming a conductive line for improving the electrical performance of a semiconductor chip package, the semiconductor chip package is mounted and combined on a substrate to be electrically connected to a plurality of solder joints arranged on the substrate, including:

[0044] A semiconductor chip (Die) 10 having a bond pad surface (Die pad surface) 12, and a plurality of bond pads (Die pad) 11 are provided on the bond pad surface (Diepad surface) 12;

[0045] At least one dielectric layer is coated on the die pad surface 12 of the semiconductor die 10;

[0046] And at least one conductive line is disposed in the dielectric layer, and one end of each conductive line is electrically connected to a die pad 11 on the semiconductor die 10 respectively, and the other end extends outward and is exposed outside the dielectric layer to form a solder bump for electrically connecting to a solder bump pre-arranged on a substrate (not shown in the figure), so that the semiconductor die 10 is mounted and bonded on the substrate; Generally speaking, when there are N die pads 11 on the die pad surface 12 of the semiconductor die 10, N mutually separated conductive lines are properly arranged and formed in the dielectric layer, so that one end of the N conductive lines is electrically connected to a die pad 11 on the semiconductor die 10 respectively, and the other ends of the N conductive lines extend outward and are exposed outside the dielectric layer to form N mutually separated solder bumps for electrically connecting to N solder bumps pre-arranged on a substrate (not shown in the figure).

[0047] The semiconductor chip packaging structure of this embodiment is illustrated by taking a single semiconductor die 10 in a wafer as an example. Generally, a plurality of die pads (also called electrodes) 11 are arranged on the semiconductor die 10. In the figure of this embodiment, one die pad 11 of the semiconductor die 10 is used to represent and illustrate but not limit.

[0048] Reference Figure 1-10 As shown, wherein Figure 1 Cross-sectional view of the semiconductor die 10, a die pad 11 can be seen. The method for forming the conductive line includes the following steps:

[0049] Reference Figure 2 As shown, S1: Coat the first dielectric layer 20 on the die pad surface 12 of the semiconductor die 10; The coating method of the first dielectric layer 20 can be spin coating. Since it is a prior art, it will not be described in detail here;

[0050] Reference Figure 3As shown, S2: Then, a photo resist such as epoxy resin or other resins is used to form, by exposure and development, a groove 21 corresponding to each pad 11 on the surface of the pad 12 on the first dielectric layer 20, so that each pad 11 can be exposed outward;

[0051] Reference Figure 4 As shown, S3: Then, a conductive metal layer (ENIG plating) such as nickel-gold material is coated on each pad 11 exposed in each line groove 21 to serve as a protective layer and also a conductive layer for each pad 11; and each first connection line 22 is respectively formed;

[0052] Reference Figure 5 As shown, S4: Conductive metal (ENIG plating) such as nickel-gold material or silver paste printing and other conductive metals are sputtered in each line groove 211 and around the groove 211 to respectively form each second connection line 32, which is a uniform thin layer and a new groove 31 is formed;

[0053] S5: The surfaces of the second connection line 32 and the first dielectric layer 20 are processed by a metal lift-off technology to remove the surface film; not shown in the figure because the semiconductor film thickness is very low (nanoscale);

[0054] Reference Figure 6 As shown, S6: A conductive metal (ENIG plating) such as silver paste printing or nickel-gold material is coated and wrapped on the surface of each second connection line 32 to respectively form each third connection line 42. The upper part of each third connection line 42 is flush with the surface of the first dielectric layer 20, and each third connection line 42 completely wraps the surface of each second connection line 32;

[0055] Reference Figure 7 As shown, S7: A second dielectric layer 40 is coated on the first dielectric layer 20 and each third connection line 42. The coating method of the second dielectric layer 40 can be a spin coating method;

[0056] Reference Figure 8 As shown, S8: Then, a photo resist such as epoxy resin or other resin is used to form grooves 41 connected to one end of each third conductive line 42 on the second dielectric layer 40 by exposure and development;

[0057] Reference Figure 9 As shown, S9: Then, a conductive metal is filled into each groove 41 by various existing methods to form a solder bump 51 respectively and expose it outside the second dielectric layer 40, so that the solder bumps 51 exposed on the second dielectric layer 40 can be electrically connected to the respective die pads 11 of the semiconductor chip 10 respectively.

[0058] Preferably, if ENIG plating is used in S4, then IMAg plating is used in S6; furthermore, if IMAg plating or other conductive metal is used in S4, then ENIG plating is used in S6.

[0059] Preferably, the thickness of the second conductive line 32 is 0.03 micrometers.

[0060] The shape of the solder bump 51 is not limited and can be set according to the structural requirements or the process equipment.

[0061] Preferably, the solder bump 51 exposed outside the second dielectric layer 40 forms a hemispherical shape protruding from the outer surface of the second dielectric layer 40 or a metal layer form parallel to the second dielectric layer 40 at the top.

[0062] Preferably, when the solder bump 51 is in the form of a metal layer parallel to the second dielectric layer 40, ENIG plating is used to more fully meet the bonding with different conductive materials.

[0063] Refer again to Figure 1-9As shown, each solder joint 51 and the first, second, and third conductive lines connected thereto constitute the conductive lines provided on the pad surface 12 of the semiconductor chip 10 in the semiconductor chip packaging structure of the present invention, so that one end of each conductive line is electrically connected to a pad 11 on the chip 10, and the other end is connected to a solder point 51 that extends outward and is exposed outside the second dielectric layer 40, so that each solder point 51 exposed outside the second dielectric layer 40 can be electrically connected to each pad 11 of the semiconductor chip 10 respectively, and can be electrically connected to a solder point pre-arranged on a substrate (not shown), so that the semiconductor chip 10 is mounted and combined on the substrate; in addition, the dielectric layers in this embodiment are the first and second dielectric layers, and the thickness is not limited and can be set according to the structural requirements or the manufacturing equipment; similarly, the thicknesses of the first, second, and third conductive lines are not particularly limited either.

[0064] And the forming method described in the present invention is not affected by the X-axis direction position on the vertical cross-section of the semiconductor chip 10 where the pad 11 is located (such as Figure 1 ), and can be implemented; for example, when the area of the pad surface 12 is too small to be laid out or the manufacturing process and equipment are difficult to cooperate, and the X-axis positions of different pads 11 are different, the packaging can be carried out by the forming method of the present invention.

[0065] Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for forming a conductive connection line for improving the electrical performance of a packaged semiconductor chip. The semiconductor chip package is mounted and bonded to a substrate to be electrically connected to a plurality of solder joints disposed on the substrate, and includes: A semiconductor chip having a pad surface provided with a plurality of pads; At least one dielectric layer coated on the pad surface of the semiconductor chip; and at least one conductive connection line, which is disposed in the dielectric layer, and one end of each conductive connection line is electrically connected to a bonding pad on the semiconductor chip respectively, and the other end extends outward and is exposed outside the dielectric layer to form a solder joint for electrically connecting to a solder joint pre-arranged on a substrate, so that the semiconductor chip is mounted and bonded to the substrate; characterized in that, The method for forming the conductive connection line includes the following steps: S1: Coating a first dielectric layer on the pad surface of the semiconductor chip; S2: Using a photoresist and exposing and developing to form grooves for each pad on the pad surface on the first dielectric layer, so that each pad can be exposed outward through each groove; S3: Filling a conductive metal in each line groove to respectively form each first conductive connection line; S4: Sputtering a conductive metal in each line groove and around the groove to respectively form each second conductive connection line and form a new groove; S5: Performing a metal stripping process on the surface of the second conductive connection line and the surface of the first dielectric layer; S6: Coating and wrapping a conductive metal on the surface of the second conductive connection line to respectively form each third conductive connection line; S7: Coating a second dielectric layer on the first dielectric layer and each third conductive connection line; S8: Using a photoresist and exposing and developing to respectively form grooves connected to one end of each third conductive connection line on the second dielectric layer; S9: Filling a conductive metal in each groove to respectively form a solder joint, and the solder joint is exposed outside the second dielectric layer and can be respectively electrically connected to each pad of the chip.

2. A method for forming a conductive line for improving the electrical performance of a packaged semiconductor chip package according to claim 1, characterized in that: The coating method of the first and second dielectric layers is a spin coating method.

3. A method for forming a conductive line for improving the electrical performance of a packaged semiconductor chip package according to claim 1, characterized in that: In step S3, when filling the conductive metal, electroless nickel immersion gold is used.

4. A method for forming a conductive line for improving the electrical connection of a packaged semiconductor chip according to claim 1, characterized in that: In step S6, when coating the conductive metal, electroless nickel immersion gold or immersion silver is used.

5. A method for forming a conductive line for improving the electrical performance of a packaged semiconductor chip according to claim 1, characterized in that: The thickness of the second conductive connection line is 0.03 microns.

6. A method for forming a conductive line for improving the electrical performance of a packaged semiconductor chip package according to claim 1, characterized in that: The solder joint exposed outside the second dielectric layer forms a hemispherical shape protruding from the outer surface of the second dielectric layer or a metal layer form with the top parallel to the second dielectric layer.

7. A method for forming a conductive line for improving the electrical performance of a packaged semiconductor chip according to claim 6, characterized in that: When the solder joint has a metal layer form parallel to the second dielectric layer, it is formed by electroless nickel immersion gold.

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