Semiconductor wafer handling method and apparatus

Abstract

Embodiments of the present application relate to semiconductor wafer handling methods and apparatus. An assembly for clamping a semiconductor wafer includes a plate and an electrostatic chuck mounted on the plate. A plurality of slots extend between respective portions of the electrostatic chuck to receive arms of an end effector of a wafer handler. The arms of the end effector support semiconductor wafers placed onto and removed from the electrostatic chuck.

Description

[0001] Related application

[0002] This application is a divisional application of the application patent application with the application date of June 11, 2019, the application number of “201980037054.6”, and the invention name of “Semiconductor wafer handling method and apparatus”.

[0003] Related application

[0004] This application claims priority to U.S. Provisional Patent Application No. 62 / 687,017, filed June 19, 2018, entitled “Slotted Monolithic Mirror Plate with Electrostatic Chuck,” the entirety of which is hereby incorporated by reference for all purposes. TECHNICAL FIELD

[0005] The present invention relates to semiconductor wafer handling, and more specifically, to an electrostatic wafer chuck having slots for wafer handling. BACKGROUND

[0006] Electrostatic wafer chucks, or simply electrostatic chucks, are used in semiconductor manufacturing equipment to hold wafers. Electrostatic chucks use high voltage to generate electrostatic forces that clamp a semiconductor wafer to the chuck. Traditionally, electrostatic chucks use lift pins to load and unload wafers. When loading a wafer, the lift pins are raised from the electrostatic chuck, receive the wafer from an end effector of a wafer handler, and then lowered until the wafer rests on the chuck surface. When unloading a wafer, the lift pins are raised to lift the wafer above the chuck surface so that an end effector of a wafer handler can slide between the wafer and the chuck surface to pick up the wafer. However, the use of lift pins creates several problems. Lift pins require travel space above the wafer and require a z-shaped stage or other travel mechanism to raise the pins, which increases the weight and complexity of the system. In addition, the travel time of the lift pins reduces throughput. SUMMARY

[0007] Accordingly, there is a need for more efficient methods and systems for loading and unloading semiconductor wafers from electrostatic chucks. Such methods and systems can be achieved by slotted electrostatic chucks.

[0008] In some embodiments, an assembly for clamping a semiconductor wafer includes a plate and an electrostatic chuck mounted on the plate. A plurality of slots extend between respective portions of the electrostatic chuck to receive arms of an end effector of a wafer handler. The arms of the end effector support semiconductor wafers placed onto and removed from the electrostatic chuck.

[0009] In some embodiments, a method of handling a semiconductor wafer includes supporting the semiconductor wafer on an arm of an end effector of a wafer handler. With the semiconductor wafer supported on the arm of the end effector, the semiconductor wafer is placed onto the electrostatic chuck by positioning the arm of the end effector in a corresponding slot extending between portions of the electrostatic chuck. With the semiconductor wafer on the electrostatic chuck, the arm of the end effector is withdrawn from the corresponding slot. The semiconductor wafer is then clamped onto the electrostatic chuck. Clamping the semiconductor wafer onto the electrostatic chuck includes biasing the electrostatic chuck. Attached Figure Description

[0010] To better understand the embodiments described, please refer to the detailed implementation below in conjunction with the following figures.

[0011] Figure 1 and 2 This is a perspective view of an assembly for holding a semiconductor wafer according to some embodiments.

[0012] Figure 3 According to some embodiments Figure 2 Perspective view of the bottom of the assembly.

[0013] Figure 4 Showing assemblies according to some embodiments (e.g.) Figure 1 The cross section of (or a combination of 2).

[0014] Figure 5 This is a plan view of the end effector of a wafer processor according to some embodiments.

[0015] Figure 6 This is a flowchart illustrating a method of processing a semiconductor wafer according to some embodiments.

[0016] Throughout the diagrams and instructions, similar component symbols refer to the corresponding parts. Detailed Implementation

[0017] Various embodiments, examples of which are illustrated in the accompanying drawings, will now be described in detail. Numerous specific details are set forth in the following detailed description to provide a thorough understanding of the described embodiments. However, it will be apparent to those skilled in the art that the described embodiments can be practiced without these specific details. In other instances, well-known methods, procedures, components, circuits, and networks have not been described in detail to avoid unnecessarily obscuring aspects of the embodiments.

[0018] Figure 1This is a perspective view of an assembly 100 for holding a semiconductor wafer according to some embodiments. The assembly 100 for use in a semiconductor manufacturing apparatus includes a slotted electrostatic chuck mounted on a plate 102. The slotted electrostatic chuck includes three electrostatic chuck portions 104-1, 104-2, and 104-3 mounted on the plate 102 and separated by slots 106-1 and 106-2. Slots 106-1 and 106-2 are sized to receive the arm of an end effector of a wafer handler (e.g., ...). Figure 5 The end effector 500 has arms 502 and 504. The end effector arms are used to place semiconductor wafers onto and remove semiconductor wafers from the slotted electrostatic chuck: the arms support the wafers during loading or removal. In some embodiments, portions 104-1, 104-2, and 104-3 are dissimilar chuck surfaces; slots 106-1 and 106-2 extend completely across the electrostatic chuck, thus dividing the chuck into dissimilar portions with dissimilar surfaces. Figure 1 In this example, slot 106-1 is located between portions 104-1 and 104-2, and slot 106-2 is located between portions 104-2 and 104-3. Alternatively, one or both of the slots may extend only midway through the electrostatic chuck, such that some or all of the portions are connected. In any case, assembly 100 is a monolithic assembly because portions 104-1, 104-2, and 104-3 are mounted on plate 102. Portions 104-1, 104-2, and 104-3 are coplanar (e.g., the platform 404 on portion 104). Figure 4 The planarity of the wafers is within a specified range (e.g., within 10 micrometers) to ensure that the wafers can be uniformly placed on the electrostatic chuck. Sections 104-1, 104-2, and 104-3, along with slots 106-1 and 106-2, are sized to receive and support semiconductor wafers of a specified diameter (e.g., 300 mm). Although Figure 1 This describes an electrostatic chuck with two slots 106 and three parts 104, but the number of slots and corresponding parts can vary.

[0019] Each of the portions 104, and therefore each dissimilar surface of the electrostatic chuck, can be divided into one or more electrode regions 108 and an insulator 110. The insulator 110 surrounds each of the electrode regions 108. Figure 1 In one example, portion 104-1 includes a single electrode region 108-1 surrounded by insulator 110, portion 104-2 includes two electrode regions 108-2 and 108-3 surrounded by insulator 110, and portion 104-3 includes a single electrode region 108-4 surrounded by insulator 110. Electrode regions 108 may be divided into groups of one or more (e.g., two) electrode regions, each group of electrode regions being independently biased to clamp a semiconductor wafer.

[0020] In some embodiments, the plate 102 is a mirror plate, such that one or more of its sides are mirrors (e.g., for use in laser interferometer mirrors positioned within a piece of semiconductor manufacturing equipment). For example, the plate 102 includes a mirror surface 118 for positioning the plate 102 in a first direction (e.g., the x-direction or, alternatively, the y-direction), and / or a mirror surface 120 for positioning the plate 102 in a second direction (e.g., the y-direction or, alternatively, the x-direction).

[0021] In some embodiments, the opening 114 is positioned on a side of the plate 102 (e.g., in the mirror surface 118, which is cut to form the opening) and is sized, along with the slots 106-1 and 106-2, to accommodate an end effector. The opening 114 extends from the side of the plate to the slots 106-1 and 106-2, and also to the edge 116 of the portion 104-2, which extends between the slots 106-1 and 106-2. (Equivalently, the slots 106-1 and 106-2 can be considered to extend to the side of the plate 102 and be joined by the opening 114.) The slots 106-1 and 106-2 and the opening 114 effectively comprise a substantially U-shaped slot to receive an arm of an end effector. (The U-shaped slot is not exactly U-shaped, as, for example, the side of the plate is straight, and the angle at which the edge 116 intersects the slots 106-1 and 106-2 can be acute, but can still be recognized as a U.) The opening 114 has a depth, as measured from the top of the side of the plate 102 (e.g., the top of the mirror surface 118), that is equal to the depth of the slots 106-1 and 106-2.

[0022] In some embodiments, the groove 112 encircles the electrostatic chuck (e.g., the portions 104-1, 104-2, and 104-3). The groove 112 can intersect the opening 114, each end (or, alternatively, a single end) of the slot 106-1, and each end (or, alternatively, a single end) of the slot 106-2. In some embodiments, the groove 112 is positioned on a side of the plate 102 (e.g., in the mirror surface 118, which is cut to form the groove) and is sized, along with the slots 106-1 and 106-2, to accommodate an end effector. The groove 112 extends from the side of the plate to the slots 106-1 and 106-2, and also to the edge 116 of the portion 104-2, which extends between the slots 106-1 and 106-2. (Equivalently, the slots 106-1 and 106-2 can be considered to extend to the side of the plate 102 and be joined by the groove 112.) The groove 112 has a depth, as measured from the top of the side of the plate 102 (e.g., the top of the mirror surface 118), that is less than the depth of the slots 106-1 and 106-2. Figure 1 In instances of the plate 102, the groove 112 (i.e., the portion of the groove 112 that is distinct from the opening 114 and the slots 106-1 and 106-2) has a depth that is less than the depth of the opening 114 and the slots 106-1 and 106-2. The groove 112 can be used to identify the location of the electrostatic chuck and thus ensure that a semiconductor wafer is properly placed onto the electrostatic chuck.

[0023] The dimensions of the various elements of the assembly 100 can vary for different embodiments. In some embodiments, the depth of the slots 106-1 and 106-2 and the opening 114 is 10 mm, the width of the slots 106-1 and 106-2 is 23 mm, the depth and / or width of the groove 112 is 4 mm, and / or the groove 112 is sized to encircle a 300 mm wafer.

[0024] The arrangement of electrode regions in the respective portions of the electrostatic chuck can also vary for different embodiments. Figure 2is a top perspective view of an assembly 200 for clamping a semiconductor wafer according to some embodiments, in which electrode regions 108-2 and 108-3 of portion 104-2 are replaced with electrode regions 208-2 and 208-3. Electrode regions 208-2 and 208-3 are electrically isolated from each other and from electrode regions 108-1 and 108-4, and can be independently biased from each other. Each of electrode regions 208-2 and 208-3, like electrode regions 108, can be surrounded by insulation 110. For example, electrode regions 108-1 and 208-2 (or 108-1 and 208-3) can be electrically connected so that they can be biased to a first bias voltage, while electrode regions 208-3 and 108-4 (or 208-2 and 108-4) can be electrically connected so that they can be biased to a second bias voltage.

[0025] In assembly 200, according to some embodiments, groove 112 is replaced with a groove 212 having a depth equal to the depth of slots 106-1 and 106-2 and opening 114. Using a groove 212 of the same depth (e.g., 10 mm) as slots 106-1 and 106-2 and opening 114 avoids acute angles where groove 212 intersects slots 106-1 and 106-2, which is desirable in the high voltage environment of an electrostatic chuck.

[0026] Figure 3 is a bottom perspective view of assembly 200 according to some embodiments. An electrical connector 318 is attached to the bottom of plate 102. Wires 302 extend from electrical connector 318 to electrical contacts 304 connected to electrode regions 108-1 and 208-2 Figure 2 ). Wires 306 extend from electrical connector 318 to electrical contacts 308 connected to electrode regions 108-4 and 208-3 Figure 2 ). Wires 302 are used to apply a first bias voltage to electrode regions 108-1 and 208-2, while wires 306 are used to apply a second bias voltage to electrode regions 108-4 and 208-3. The first bias voltage and the second bias voltage are separate, independent bias voltages. Other wires 310 and 314 extend from electrical connector 318 to respective electrical contacts 312 and 316, which are connected to plate 102 and are used to bias features of plate 102. For example, wires 314 and contacts 316 are used to apply a third bias voltage to the surface of plate 102 (e.g., including opening 114, slots 106 and slots 112 / 212, Figures 1 to 2 ). The third bias voltage is different and independent from the first bias voltage and the second bias voltage.

[0027] Figure 4 shows an assembly (e.g., assembly 100 or 200, Figures 1 to 3The portion 104 of the electrostatic chuck is located adjacent to the groove 106 or recess 112 / 212. The portion 104 includes a top dielectric layer 402 (e.g., a first glass layer), a conductive layer 406 below the dielectric layer 402, and an insulating layer 408 (e.g., a second glass layer) below the conductive layer 406. In some embodiments, the dielectric layer 402 includes a mesa 404 on its surface, which supports a semiconductor wafer positioned on the electrostatic chuck. In some embodiments, the conductive layer 406 does not extend to the edge of the portion 104. Instead, the conductive layer 406 terminates before the edge (i.e., before the interface between the portion 104 and the groove 106 or recess 112 / 212). The edge region of the portion 104 (where the conductive layer 406 is absent and the dielectric layer 402 contacts the insulating portion 408) corresponds to the insulation 110. Figures 1 to 2 The electric layer 406 defines the electrode regions 108 / 208 in the portion 104. According to some embodiments, each electrode region 108 / 208 therefore includes a corresponding electric layer 406 located beneath the dielectric layer 402.

[0028] Part 104 is mounted onto plate 102 (e.g., mirror plate) using adhesive layer 410. For example, each of parts 104-1, 104-2, and 104-3 ( Figures 1 to 2 Therefore, each phase suction cup surface is individually bonded to the plate 102 using a corresponding adhesive layer 410. Conductive vias 412 (e.g., vias filled with conductive adhesive) extend through the plate 100, adhesive layer 410, and insulating layer 408 to electrically connect electrical layer 406 to contacts 304 or 308. Figure 3 Therefore, the electrical layer 406 is electrically connected to the electrical connector 318 through conductive vias 412, one or more contacts 304 or 308, and wiring 302 or 306.

[0029] Figure 5 This is a plan view of an end effector 500 of a wafer processor according to some embodiments. The end effector includes a first arm 502 and a second arm 504 that together support a semiconductor wafer. Slots 106-1 and 106-2 are sized to receive arms 502 and 504.

[0030] Figure 6 This is a flowchart illustrating a method 600 for processing a semiconductor wafer according to some embodiments. In method 600, at the end effector of the wafer processor (e.g., Figure 5 A semiconductor wafer (602) is supported on the arm of the end effector (502 and 504). With the semiconductor wafer supported on the arm of the end effector, the semiconductor wafer is placed (604) onto the electrostatic chuck. To place the semiconductor wafer onto the electrostatic chuck, the arm of the end effector is positioned on a portion of the electrostatic chuck (e.g., ...). Figures 1 to 2(e.g., portions 104-1, 104-2, and 104-3 of the electrostatic chuck 104) and / or the second group of distinct electrode regions (e.g., portions 108-1 and 208-2 of the electrode regions 108 / 208) of the electrostatic chuck 104. Figures 1 to 2 (e.g., portions 104-1, 104-2, and 104-3 of the electrostatic chuck 104) and / or the second group of distinct electrode regions (e.g., portions 108-1 and 208-2 of the electrode regions 108 / 208) of the electrostatic chuck 104. Figure 2 (e.g., portions 104-1, 104-2, and 104-3 of the electrostatic chuck 104) and / or the second group of distinct electrode regions (e.g., portions 108-1 and 208-2 of the electrode regions 108 / 208) of the electrostatic chuck 104. Figure 2 (e.g., portions 104-1, 104-2, and 104-3 of the electrostatic chuck 104) and / or the second group of distinct electrode regions (e.g., portions 108-1 and 208-2 of the electrode regions 108 / 208) of the electrostatic chuck 104. Figures 1 to 2 (e.g., portions 104-1, 104-2, and 104-3 of the electrostatic chuck 104) and / or the second group of distinct electrode regions (e.g., portions 108-1 and 208-2 of the electrode regions 108 / 208) of the electrostatic chuck 104. Figures 1 to 4 (e.g., portions 104-1, 104-2, and 104-3 of the electrostatic chuck 104) and / or the second group of distinct electrode regions (e.g., portions 108-1 and 208-2 of the electrode regions 108 / 208) of the electrostatic chuck 104.

[0031] With the semiconductor wafer on the electrostatic chuck, the arm of the end effector is extracted (610) from the respective slot. The semiconductor wafer is clamped (612) to the electrostatic chuck. Clamping the semiconductor wafer to the electrostatic chuck includes biasing the electrostatic chuck. In some embodiments, a first bias voltage is applied (614) to the electrode regions in the first group, and a second bias voltage is applied (614) to the electrode regions in the second group. In some embodiments, clamping the semiconductor wafer to the electrostatic chuck further includes applying (616) a third bias voltage to the plate. For example, the plate (e.g., the outer surface of the plate 102) is first biased (e.g., via the wiring 314 and the contact 316 Figure 3 ) to the third bias voltage (e.g., 10 kV). The electrode regions in the first and second groups are then tuned to their respective first and second bias voltages (e.g., 11.5 kV and 8.5 kV, respectively). For example, the electrode regions in the first group are biased via the wiring 302 and the contact 304, and the electrode regions in the second group are biased via the wiring 306 and the contact 308 Figure 3 ), or vice versa.

[0032] With the semiconductor wafer clamped to the electrostatic chuck, processing and / or characterization of the semiconductor wafer is performed. Once the processing and / or characterization is complete, the semiconductor wafer can be unclamped. To unclamp the semiconductor wafer, the semiconductor wafer is unclamped (618) from the electrostatic chuck. Unclamping the semiconductor wafer includes stopping biasing (618) the electrostatic chuck. In some embodiments, unclamping the semiconductor wafer further includes stopping biasing the plate. The arm of the end effector is inserted (620) into the respective slot. With the semiconductor wafer unclamped from the electrostatic chuck and the arm of the end effector inserted into the respective slot, the arm of the end effector is raised (622) to lift the semiconductor wafer off the electrostatic chuck.

[0033] The order-independent steps in the method 600 can be reordered and the steps can be combined or decomposed.

[0034] The method 600 and assembly 100 / 200 provide a number of benefits. The space above the chuck for loading and unloading the wafer can be less than the space required when using lift pins. Travel time associated with lift pins is eliminated, thus reducing wafer handling time and increasing throughput. Z-stages or other lift pin mechanisms to raise and lower the lift pins are avoided, thus reducing weight and complexity.

[0035] The foregoing description has been presented for the purpose of illustration. It is not intended to be exhaustive or to limit the claims to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching. Embodiments have been chosen and described in order to best illustrate the principles of the claims and its practical application to thereby enable one of ordinary skill in the art to best utilize the embodiments with various modifications as are suited to the particular use contemplated.

Claims

1. An assembly for chucking a semiconductor wafer, comprising: a plate; an electrostatic chuck mounted on the plate, the electrostatic chuck comprising a plurality of distinct chuck surface portions, wherein each distinct chuck surface portion is divided into one or more electrode regions and an insulator surrounding each electrode region, and each electrode region comprises a respective conductive layer; a plurality of slots extending between respective distinct chuck surface portions of the electrostatic chuck to receive arms of an end effector of a wafer handler, wherein the arms of the end effector are used to support semiconductor wafers placed onto and removed from the electrostatic chuck; and a conductive via extending through the plate to connect to the respective conductive layer of a respective electrode region of a plurality of distinct electrode regions of the plurality of distinct chuck surface portions.

2. The assembly of claim 1, wherein the respective electrode region of the plurality of distinct electrode regions further comprises: a respective dielectric layer on the respective conductive layer; and a respective insulating layer under the respective conductive layer; wherein the conductive via extends through the respective insulating layer to connect to the respective conductive layer. The conductive via extends through the gel.

3. The assembly of claim 1, further comprising glue to connect an electrostatic chuck to the plate: wherein, 4. The assembly of claim 1, further comprising: an electrical connector attached to the plate; and wiring connected to the electrical connector to apply a bias voltage to the plurality of distinct electrode regions, wherein the wiring comprises wiring that applies a respective bias voltage to the respective electrode region through the conductive via.

5. A method of handling a semiconductor wafer, comprising: supporting a semiconductor wafer on an arm of an end effector of a wafer handler; with the semiconductor wafer supported by the arm of the end effector, placing the semiconductor wafer onto an electrostatic chuck comprising a plurality of distinct chuck surface portions mounted on a plate, wherein each distinct chuck surface portion is divided into one or more electrode regions and an insulator surrounding each electrode region, and a plurality of distinct electrode regions of the plurality of distinct chuck surface portions are divided into a first group and a second group of a plurality of distinct electrode regions, including positioning the arm of the end effector in a respective slot extending between portions of the electrostatic chuck; with the semiconductor wafer on the electrostatic chuck, withdrawing the arm of the end effector from the respective slot; and biasing the electrostatic chuck to chuck the semiconductor wafer to the electrostatic chuck, including applying a first bias voltage to the electrode regions in the first group, applying a second bias voltage to the electrode regions in the second group, and applying a third bias voltage to the plate. ​ ​ ​

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