Method for manufacturing a metal zero layer

Abstract

The application discloses a manufacturing method of metal zero layer, and a forming step of metal silicide layer of bottom doped region, which comprises the following steps: step one, forming a trench of metal zero layer; step two, forming an amorphous silicon sacrificial layer, which is formed on the bottom surface of the trench and extends to the bottom part of the side surface of the trench on both sides, thus forming a bag type shape; step three, forming a first metal layer; step four, annealing to make the first metal layer and the amorphous silicon sacrificial layer or the doped region on the bottom of the amorphous silicon sacrificial layer react to form a metal silicide layer, and the amorphous silicon sacrificial layer is completely consumed, the metal silicide layer is in a bag type shape, and the shape of the metal silicide layer is determined by the shape of the amorphous silicon sacrificial layer. The application can well control the size and shape of the metal silicide layer between the metal zero layer and the bottom doped region, thus controlling the volume and contact area of the metal silicide layer, and reducing the contact resistance.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly to a method for manufacturing a metal zero layer (MO). Background Technology

[0002] As the critical dimensions of semiconductor devices continue to shrink, such as to below 7nm and 5nm, the mid-range (MOL) metal interconnect resistance becomes particularly important. The device-design-point (DDP) requirements are: RON ≈ 200–400 Ω·μm and RC ≤ RON / 10; RON represents the source-drain on-resistance of the device; RC represents the contact resistance, primarily the contact resistance formed by the metal null layer and the bottom doped region.

[0003] At the 7nm process node, CPP = 48nm. CPP represents the step size along the gate alignment direction, i.e., the sum of the gate width and gate pitch. The ρC formed by existing materials is 2 × 10⁻⁶. -9 Ω·cm 2 The resistivity of the ρC contact is no longer sufficient to meet design requirements at the 7nm process node. When CPP is scaled down to 40nm, even higher requirements are needed: ρC needs to reach 8×10⁻⁶. -10 Ω·cm 2 Therefore, new materials such as Co need to be introduced into the intermediate metal, i.e., the metal zero layer, below 7nm and 5nm to meet device requirements; at the same time, the metal silicide layer between Co and the bottom epitaxial layer is usually TiSix, i.e., titanium silicide.

[0004] Introducing titanium silicide (TiSix) and Co processes significantly complicates the manufacturing process, as the shape and size of TiSix greatly influence the resistance of the Mo0 MOSFET. Small TiSix volume results in a small contact area and high resistance. In existing processes, to increase the volume and contact area of ​​TiSix, the epitaxial layer corresponding to the doped region at the bottom of the Mo0 MOSFET needs to be etched. The epitaxial layers corresponding to the source and drain regions of PMOS and NMOS are typically SiGe and SiP epitaxial layers, respectively. When using wet and dry etching methods to etch SiGe and SiP epitaxial layers, the etching rates differ; SiP has a faster etching rate, while SiGe has a slower one. This makes the morphology and size of the etched SiP and SiGe layers uncontrollable, thus making the morphology at the bottom of the Mo0 MOSFET uncontrollable.

[0005] like Figures 1A-1B The diagram shown is a schematic cross-sectional view of the device structure in each step of the existing metal zero layer manufacturing method. In the existing metal zero layer manufacturing method, the steps for forming the metal zero layer and the metal silicide layer in the bottom doped region include:

[0006] Step 1, such as Figure 1AA trench is formed to form a metal zero layer, which passes through the interlayer film 109 and exposes the bottom doped region.

[0007] Before the trench is formed to form the metal zero layer, the forming process before the interlayer film 109 has been completed, including:

[0008] A field oxide such as a shallow trench isolation 102 is formed on a semiconductor substrate 101 such as a silicon substrate. The shallow trench isolation 102 defines each active region.

[0009] The MOS transistors on the same semiconductor substrate 101 usually include both NMOS and PMOS. Figure 1A In particular, the NMOS is formed in the region shown by the bracket 103, and the PMOS is formed in the region shown by the bracket 104.

[0010] The doped region at the bottom of the trench is the source / drain region of the MOS transistor.

[0011] The source / drain region of the PMOS is P+ doped and formed in the embedded SiGe epitaxial layer 108.

[0012] The source / drain region of the NMOS is N+ doped and formed in the embedded SiP epitaxial layer 107.

[0013] Each MOS transistor includes a gate structure 105, which is usually a high-k metal gate (HKMG) and is formed by a gate-last process. A sidewall 106 is formed on the side of the gate structure 105. In the gate-last process, a dummy gate structure is usually first formed in the region where the gate structure 105 is formed, and the sidewall 106 and the source / drain region are formed using the dummy gate structure self-alignment.

[0014] The interlayer film 109 includes a first interlayer film 109a and a second interlayer film 109b.

[0015] A contact etch stop layer (CESL) (not shown) is usually formed before the first interlayer film 109a is formed. After the first interlayer film 109a is planarized, the top surface of the first interlayer film 109a is flush with the top surface of the dummy gate structure, and then the dummy gate structure is removed and the gate structure 105 is formed in the region where the dummy gate structure is removed. Then the second interlayer film 109b is formed.

[0016] In the prior art, the trench is defined and etched in two times, which are:

[0017] The formation region of the trench at the top of the source / drain region of the NMOS is defined by a photolithography process, and then the trench at the top of the source / drain region of the NMOS is etched, Figure 1AIn the text, the trench at the top of the source and drain regions of the NMOS is separately indicated by the symbol 110a.

[0018] Subsequently, a second photolithography process is performed to define the formation region of the trench at the top of the source and drain regions of the PMOS, followed by etching to form the trench at the top of the source and drain regions of the PMOS. Figure 1A In the diagram, the trench at the top of the source and drain regions of the PMOS is separately indicated by the symbol 110b.

[0019] Step Two, as follows Figure 1B As shown, the embedded SiGe epitaxial layer 108 at the bottom of trench 110b and the embedded SiP epitaxial layer 107 at the bottom of trench 110a are etched using wet or dry etching processes. It can be seen that after etching, the top surface 111a of the embedded SiP epitaxial layer 107 and the top surface 111b of the embedded SiGe epitaxial layer 108 have different structures. This is because the etching rates of the SiGe epitaxial layer and the SiP epitaxial layer are different, which will adversely affect the control of the shape and size of the subsequently formed metal silicide layer.

[0020] Subsequently, Ti and TiN layers will be formed, and an annealing process will be performed to form TiSix at the contact between Ti and Si.

[0021] Electroplating then forms Co, which completely fills the trench, thus forming a metal zero layer. Summary of the Invention

[0022] The technical problem to be solved by the present invention is to provide a method for manufacturing a metal zero layer, which can effectively control the size and shape of the metal silicide layer between the metal zero layer and the bottom doped region, thereby controlling the volume and contact area of ​​the metal silicide layer and reducing the contact resistance.

[0023] To solve the above-mentioned technical problems, the method for manufacturing a metal null layer provided by the present invention includes the following steps for forming the metal null layer and the metal silicide layer in the bottom doped region:

[0024] Step 1: Form a trench for the metal zero layer, which penetrates the interlayer film and exposes the doped region at the bottom.

[0025] Step 2: Forming an amorphous silicon sacrificial layer, wherein the amorphous silicon sacrificial layer is formed on the bottom surface of the trench and the bottom portion of the sidewalls of the trench extending to both sides of the bottom surface of the trench makes the amorphous silicon sacrificial layer into a bag shape.

[0026] Step 3: Form a first metal layer, which covers the surface of the amorphous silicon sacrificial layer, the sides of the trench on top of the amorphous silicon sacrificial layer, and the outer surface of the trench.

[0027] Step four, annealing to cause a silicidation reaction of silicon of the first metal layer and the amorphous silicon sacrificial layer or the doped region at the bottom of the amorphous silicon sacrificial layer to form a metal silicide layer, the amorphous silicon sacrificial layer is completely consumed, the metal silicide layer is in a pocket shape and the shape of the metal silicide layer is determined by the shape of the amorphous silicon sacrificial layer.

[0028] Further improvement is that in step one, the doped region at the bottom of the trench is a source / drain region of a MOS transistor.

[0029] Further improvement is that the MOS transistor comprises a PMOS, the source / drain region of the PMOS is P+ doped and formed in an embedded SiGe epitaxial layer.

[0030] Further improvement is that the MOS transistor comprises an NMOS, the source / drain region of the NMOS is N+ doped and formed in an embedded SiP epitaxial layer.

[0031] Further improvement is that step two comprises the following sub-steps:

[0032] Step 21, depositing a first amorphous silicon layer, the first amorphous silicon layer is formed on the inner side surface of the trench and the surface of the interlayer dielectric outside the trench.

[0033] Step 22, forming a filling layer to completely fill the trench and cover the surface of the interlayer dielectric outside the trench.

[0034] Step 23, etching the filling layer to remove the filling layer outside the trench and lower the top surface of the filling layer inside the trench to be level with the top surface of the bottom part of the amorphous silicon sacrificial layer at the side of the trench.

[0035] Step 24, etching to remove the first amorphous silicon layer above the top surface of the filling layer and the amorphous silicon sacrificial layer is composed of the remaining first amorphous silicon layer.

[0036] Step 25, removing the filling layer.

[0037] Further improvement is that in step 22, the filling layer adopts a carbon coating (Spin-On-Carbon, SOC) and is formed by a coating process. SOC is a polymer with high carbon content.

[0038] Further improvement is that the metal silicide layer formed in step four comprises titanium silicide, molybdenum silicide (MoSix), nickel silicide (NiSix) or ruthenium silicide (RuSix).

[0039] Further improvement is that the metal silicide layer is titanium silicide, and the first metal layer in step three comprises a Ti layer and a TiN layer.

[0040] Further improvement is that the annealing in step four is a spike annealing.

[0041] Further improvement is that the process condition of the spike annealing comprises a temperature of 600 ℃ and a time of 3 seconds.

[0042] Further improvement is that the thickness of the amorphous silicon sacrificial layer is 1-10 nm.

[0043] Further improvement is that the height of the amorphous silicon sacrificial layer on the bottom part of the side of the trench is 1-10 nm.

[0044] Further improvement is that after step four, the following steps are included:

[0045] Step five, filling the second metal layer in the trench to form the metal zero layer.

[0046] Further improvement is that the material of the second metal layer comprises Co.

[0047] Further improvement is that the second metal layer is formed by an electroplating process.

[0048] The present application is not to form the first metal layer required by the metal silicide layer after the trench of the metal zero layer is formed, but to form an amorphous silicon sacrificial layer first and set the shape of the amorphous silicon sacrificial layer as a pocket shape. Since the pocket shape of the amorphous silicon sacrificial layer is formed by covering the bottom surface of the trench and the bottom part of the side extending to both sides with the amorphous silicon sacrificial layer, the control process of the shape and size, i.e. the thickness of the amorphous silicon sacrificial layer is simple and accurate. Then, the metal silicide layer is mainly formed by the silicidation reaction of the first metal layer and the amorphous silicon sacrificial layer, so the shape of the metal silicide layer can be determined by the shape of the amorphous silicon sacrificial layer. Therefore, the present application can well control the size and shape of the metal silicide layer between the metal zero layer and the bottom doped region, so as to increase the volume and contact area of the metal silicide layer by controlling the size and shape of the metal silicide layer, and thereby reduce the contact resistance.

[0049] The present application is particularly suitable for devices in which the size and shape of the metal silicide layer have a greater impact on the contact resistance of the metal zero layer and the bottom doped region. The contact resistance can be reduced by controlling the size and shape of the metal silicide layer, for example, the contact resistance of the metal silicide layer composed of titanium silicide and the metal zero layer composed of Co in devices with a critical dimension of 7 nm or 5 nm is greatly affected by the size and shape of the titanium silicide. The present application can well control the size and shape of the titanium silicide to reduce the contact resistance.

[0050] Moreover, after the amorphous silicon sacrificial layer is introduced, the amorphous silicon sacrificial layer can also block the diffusion of the dopant in the bottom doped region, for example, the boron dopant in the source and drain region of PMOS, which can further improve the performance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0051] The present application will be further described below in conjunction with the drawings and specific embodiments:

[0052] Figures 1A-1B is a device cross-sectional structure schematic diagram after the formation of the metal zero layer trench in the prior art method for manufacturing the metal zero layer;

[0053] Figure 1B is a device cross-sectional structure schematic diagram after the etching of the epitaxial layer of the source and drain region after the formation of the metal zero layer trench in the prior art method for manufacturing the metal zero layer;

[0054] Figure 2 is a flow chart of the embodiment of the method for manufacturing the metal zero layer of the present application;

[0055] Figures 3A-3J is a device cross-sectional structure schematic diagram in each step of the embodiment of the method for manufacturing the metal zero layer of the present application;

[0056] Figure 4A is a photo of the metal zero layer formed by the prior art method for manufacturing the metal zero layer;

[0057] Figure 4B is a photo of the metal zero layer formed by the embodiment of the method for manufacturing the metal zero layer of the present application. DETAILED DESCRIPTION

[0058] As shown in Figure 2 is a flow chart of the embodiment of the method for manufacturing the metal zero layer of the present application; as shown in Figures 3A-3J is a device cross-sectional structure schematic diagram in each step of the embodiment of the method for manufacturing the metal zero layer of the present application; in the embodiment of the method for manufacturing the metal zero layer of the present application, the formation step of the metal zero layer 214 and the metal silicide layer 213 of the bottom doped region includes:

[0059] Step one, form a trench of the metal zero layer 214, the trench passes through the interlayer film 209 and exposes the bottom doped region.

[0060] As shown in Figure 3A in the embodiment of the present application, before the formation of the trench of the metal zero layer 214, the formation process before the interlayer film 209 has been completed, including:

[0061] Form a field oxide such as a shallow trench isolation 202 on a semiconductor substrate 201 such as a silicon substrate. The shallow trench isolation 202 defines each active region.

[0062] MOS transistors on the same semiconductor substrate 201 typically include both NMOS and PMOS. Figure 3A In the diagram, an NMOS is formed in the region indicated by curly brace 203, and a PMOS is formed in the region indicated by curly brace 204.

[0063] The doped region at the bottom of the trench is the source / drain region of a MOS transistor.

[0064] The source and drain regions of the PMOS are P+ doped and formed in an embedded SiGe epitaxial layer 208.

[0065] The source and drain regions of the NMOS are N+ doped and formed in the embedded SiP epitaxial layer 207.

[0066] Each of the aforementioned MOS transistors includes a gate structure 205, which is typically a high-dielectric-constant metal gate formed using a back-gate process. Sidewalls 206 are formed on the sides of the gate structure 205. In the back-gate process, a dummy gate structure is typically formed first in the formation region of the gate structure 205, and the sidewalls 206 and the source / drain regions are formed using the dummy gate structure for self-alignment.

[0067] The interlayer membrane 209 includes a first interlayer membrane 209a and a second interlayer membrane 209b.

[0068] Before forming the first interlayer film 209a, a contact etch stop layer (not shown) is typically formed. After planarizing the first interlayer film 209a, the top surface of the first interlayer film 209a is flush with the top surface of the dummy gate structure. The dummy gate structure is then removed, and the gate structure 205 is formed in the dummy gate structure removal region. The second interlayer film 209b is then formed.

[0069] In this embodiment of the invention, the trench is defined and etched in two stages:

[0070] like Figure 3B As shown, the formation region of the trench at the top of the source and drain regions of the NMOS is defined using photolithography, and then the trench at the top of the source and drain regions of the NMOS is formed by etching. Figure 3B In the text, the trench at the top of the source and drain regions of the NMOS is separately indicated by the symbol 210a.

[0071] After that, as Figure 3C As shown, a second photolithography process is performed to define the trench formation region at the top of the source and drain regions of the PMOS, followed by etching to form the trench at the top of the source and drain regions of the PMOS. Figure 3C In the diagram, the trench at the top of the source and drain regions of the PMOS is separately indicated by the symbol 210b.

[0072] Step 2: Forming an amorphous silicon sacrificial layer 211, wherein the amorphous silicon sacrificial layer 211 is formed on the bottom surface of the trench and the bottom portion of the side of the trench extending to the bottom surface of the trench makes the amorphous silicon sacrificial layer 211 into a bag shape.

[0073] In this embodiment of the invention, step two includes the following sub-steps:

[0074] Step 21, as follows Figure 3D As shown, a first amorphous silicon layer 211a is deposited, which is formed on the inner surface of the trench and on the surface of the interlayer film 209 outside the trench.

[0075] In some embodiments, the thickness of the amorphous silicon sacrificial layer 211

[0076] Step 22, as follows Figure 3E As shown, a filling layer 212a is formed to completely fill the trench and cover the surface of the interlayer membrane 209 outside the trench.

[0077] In some preferred embodiments, the filler layer 212a is a SOC layer and is formed using a coating process.

[0078] Step 23, as follows Figure 3F As shown, etching is performed on the filling layer 212a to remove all of the filling layer 212a outside the trench and to lower the top surface of the filling layer 212a inside the trench to be flush with the top surface of the bottom portion of the amorphous silicon sacrificial layer 211 located on the side of the trench.

[0079] Figure 3F In this diagram, the filling layer after etching is separately indicated by the symbol 212. The remaining thickness of the filling layer 212 is...

[0080] Step 24, as follows Figure 3G As shown, etching is performed to remove all the first amorphous silicon layers 211a located above the top surface of the filling layer 212a, and the remaining first amorphous silicon layers 211a form the amorphous silicon sacrificial layer 211.

[0081] The thickness of the amorphous silicon sacrificial layer 211 The thickness of the amorphous silicon sacrificial layer 211 is the same as the thickness of the first amorphous silicon layer 211a.

[0082] The height of the amorphous silicon sacrificial layer 211 at the bottom portion located on the side of the trench is... The height of the amorphous silicon sacrificial layer 211 on the bottom part of the side of the trench is the thickness of the remaining filling layer 212.

[0083] Step 25, as shown in the figure, the filling layer 212a is removed. Figure 3G

[0084] Step three, as shown in the figure, a first metal layer 213a is formed, which covers the surface of the amorphous silicon sacrificial layer 211 and the side of the trench on the top of the amorphous silicon sacrificial layer 211 and the outer surface of the trench. Figure 3H

[0085] In the embodiment of the present application, the first metal layer 213a includes a Ti layer and a TiN superimposed layer.

[0086] In other embodiments, the first metal layer 213a can also be a molybdenum layer, a nickel layer or a ruthenium layer, so as to form a molybdenum silicide, a nickel silicide or a ruthenium silicide in subsequent step four.

[0087] Step four, as shown in the figure, annealing is performed to make the first metal layer 213a and the amorphous silicon sacrificial layer 211 or the silicon of the doped region at the bottom of the amorphous silicon sacrificial layer 211 silicified to form a metal silicide layer 213, the amorphous silicon sacrificial layer 211 is completely consumed, the metal silicide layer 213 is in a bag type shape and the shape of the metal silicide layer 213 is determined by the shape of the amorphous silicon sacrificial layer 211. Figure 3I

[0088] In the embodiment of the present application, the metal silicide layer 213 formed is a titanium silicide. In other embodiments, the first metal layer 213a can also be a molybdenum silicide, a nickel silicide or a ruthenium silicide.

[0089] The annealing of step four adopts a spike annealing. The process conditions of the spike annealing include: temperature 600℃, time 3 seconds.

[0090] After step four, it includes:

[0091] Step five, as shown in the figure, a second metal layer is filled in the trench to form the metal zero layer 214. Figure 3J

[0092] The material of the second metal layer includes Co.

[0093] The second metal layer is formed by an electroplating process.

[0094] In the embodiment of the present application, the metal zero layer 214 is in contact with the doped region of the active region, i.e. the source-drain region of PMOS or NMOS, so it is an active region metal zero layer (M0A). ​​​​

[0095] The embodiment of the present application forms an amorphous silicon sacrificial layer 211 after forming the trench of the metal zero layer 214, and sets the shape of the amorphous silicon sacrificial layer 211 as a pocket shape. The pocket shape of the amorphous silicon sacrificial layer 211 is formed by covering the bottom surface of the trench and the bottom part of the side surface extending to both sides with the amorphous silicon sacrificial layer 211. Therefore, the shape and size (thickness) of the amorphous silicon sacrificial layer 211 can be controlled simply and accurately. Then, the metal silicide layer 213 is mainly formed by the silicidation reaction of the first metal layer 213a and the amorphous silicon sacrificial layer 211. Therefore, the shape of the metal silicide layer 213 can be determined by the shape of the amorphous silicon sacrificial layer 211. Thus, the embodiment of the present application can control the size and shape of the metal silicide layer 213 between the metal zero layer 214 and the bottom doped region, so as to increase the volume and contact area of the metal silicide layer 213 by controlling the size and shape of the metal silicide layer 213, and thus reduce the contact resistance.

[0096] The embodiment of the present application is particularly suitable for devices in which the size and shape of the metal silicide layer 213 have a greater impact on the contact resistance of the metal zero layer 214 and the bottom doped region. The contact resistance can be reduced by controlling the size and shape of the metal silicide layer 213. For example, in devices with a critical dimension of 7 nm or 5 nm, the contact resistance between the metal silicide layer 213 composed of titanium silicide and the metal zero layer 214 composed of Co is greatly affected by the size and shape of the titanium silicide. The embodiment of the present application can well control the size and shape of the titanium silicide to reduce the contact resistance.

[0097] Furthermore, after introducing the amorphous silicon sacrificial layer 211, the amorphous silicon sacrificial layer 211 can also block the diffusion of the dopant in the bottom doped region, for example, the boron dopant in the source and drain regions of the PMOS. This can further improve the performance of the device.

[0098] As shown in FIG. 3, Figure 4B As shown in FIG. 3, Figure 4A As shown in FIG. 3, Figure 4AIn the figure, the image of the metal silicide layer of the NMOS is located in the area of the circle 301a, and the image of the metal silicide layer of the PMOS is located in the area of the circle 301b. It can be seen that the topography of the metal silicide layer in the circles 301a and 301b is the same, and the thickness is thin, the volume is small, and the actual contact area is also small. Therefore, compared with the prior art, the metal silicide volume and the contact area of the M0 bottom of the NMOS and the PMOS are both reduced. Figure 4A Compared with the prior art, the metal silicide volume and the contact area of the M0 bottom of the NMOS and the PMOS are both reduced. Figure 4A The metal silicide volume and the contact area of the M0 bottom of the NMOS and the PMOS formed by the prior art are increased.

[0099] The above has been described in detail through specific embodiments, but these do not constitute a limitation on the present application. Those skilled in the art can also make many modifications and improvements without departing from the principles of the present application, and these should also be considered as the protection scope of the present application.

Claims

1. A method of manufacturing a metal zero layer, characterized by, The forming step of the metal silicide layer of the metal zero layer and the bottom doped region includes: Step one, forming a trench of the metal zero layer, the trench passes through the interlayer film and exposes the top surface of the bottom doped region and the etching process of forming the trench does not etch the bottom doped region; Step two, forming an amorphous silicon sacrificial layer, the amorphous silicon sacrificial layer is formed on the bottom surface of the trench and is in a pocket shape by the bottom part of the trench side extending to both sides of the bottom surface of the trench; Step three, forming a first metal layer, the first metal layer covers the surface of the amorphous silicon sacrificial layer and the trench side on the top of the amorphous silicon sacrificial layer and the outside surface of the trench; Step four, annealing to make the first metal layer and the amorphous silicon sacrificial layer or the silicon of the bottom doped region of the amorphous silicon sacrificial layer silicified to form a metal silicide layer, the amorphous silicon sacrificial layer is completely consumed, the metal silicide layer is in a pocket shape and the shape of the metal silicide layer is determined by the shape of the amorphous silicon sacrificial layer.

2. The method of manufacturing a metal zero layer of claim 1, wherein: In step one, the bottom doped region of the trench is the source and drain region of a MOS transistor.

3. The method of manufacturing a metal zero layer of claim 2, wherein: The MOS transistor includes a PMOS, the source and drain region of the PMOS is P+ doped and is formed in an embedded SiGe epitaxial layer.

4. The method of manufacturing a metal zero layer of claim 2, wherein: The MOS transistor includes an NMOS, the source and drain region of the NMOS is N+ doped and is formed in an embedded SiP epitaxial layer.

5. The method of manufacturing a metal zero layer of claim 2, wherein: Step two includes the following sub-steps: Step 21, depositing a first amorphous silicon layer, the first amorphous silicon layer is formed on the inside surface of the trench and the surface of the interlayer film outside the trench; Step 22, forming a filling layer to completely fill the trench and cover the surface of the interlayer film outside the trench; Step 23, etching the filling layer to remove the filling layer outside the trench and lower the top surface of the filling layer in the trench to be level with the top end surface of the bottom part of the amorphous silicon sacrificial layer on the side of the trench; Step 24, etching to remove the first amorphous silicon layer above the top surface of the filling layer and the amorphous silicon sacrificial layer is composed of the remaining first amorphous silicon layer; Step 25, removing the filling layer.

6. The method of manufacturing a metal zero layer of claim 5, wherein: In step 22, the filling layer uses an SOC layer and is formed by a coating process.

7. The method of manufacturing a metal zero layer of claim 2, wherein: The metal silicide layer formed in step four includes titanium silicide, molybdenum silicide, nickel silicide or ruthenium silicide.

8. The method of manufacturing a metal zero layer of claim 7, wherein: When the metal silicide layer is titanium silicide, in step three, the first metal layer includes a superimposed layer of a Ti layer and a TiN layer.

9. The method of claim 2, wherein: the metal layer is a metal zero layer. The annealing in step four uses spike annealing.

10. The method of claim 9, wherein: the metal layer is a metal zero layer. The process conditions of the spike annealing include: temperature 600℃, time 3 seconds.

11. The method for manufacturing a metal layer as described in claim 1, characterized in that: The thickness of the amorphous silicon sacrificial layer is 20Å-30Å.

12. The method of claim 11, wherein: The height of the bottom part of the amorphous silicon sacrificial layer on the side of the trench is 30Å-50Å.

13. The method of claim 1, wherein: the metal layer is a zero layer. After step four, it includes: Step five, filling a second metal layer in the trench to form the metal zero layer.

14. The method of claim 13, wherein: The material of the second metal layer includes Co.

15. The method of claim 14, wherein: the metal layer is a zero layer of metal. The second metal layer is formed by an electroplating process.

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