Layout for testing contact hole resistance

Abstract

The present application provides a layout for testing contact hole resistance, comprising a first active region pattern; a first and a second gate pattern across the first active region pattern, and the first active region pattern separating the first and the second gate pattern; a first contact hole pattern arranged between the first and the second gate pattern and on the first active region pattern; a second and a third contact hole pattern arranged on both sides of the first and the second gate pattern and on the first active region pattern; a first to a third metal layer pattern arranged on the first to the third contact hole pattern respectively; a third gate pattern; a fourth contact hole pattern arranged on the third gate pattern, and a fifth and a sixth contact hole pattern arranged on both ends of the fourth contact hole pattern and on the third gate pattern; a fourth to a sixth metal layer pattern arranged on the fourth to the sixth contact hole pattern respectively. The layout of the present application can test the resistance of two types of contact holes on the active region and on the gate respectively.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a layout for testing contact hole resistance. BACKGROUND

[0002] In current 28nm and below process, the resistance of square contact hole is mainly divided into two kinds, which are the resistance of contact hole in active area and the resistance of contact hole in gate. These tests all adopt Kelvin test method. Kelvin four-terminal sensing, also known as 4T sensing, four-wire sensing or 4-point probe method, is a kind of electrical impedance measurement technology, which uses separate current-carrying and voltage-sensing electrodes to make more accurate measurements than the traditional two-terminal (2T) sensing. Kelvin four-terminal sensing is used in some ohmmeters and impedance analyzers, and in the wiring configuration of precision strain gauges and resistance thermometers. It can also be used to measure the sheet resistance of thin films. The key advantage of four-terminal sensing is the separate current and voltage electrodes, which eliminate the impedance of wiring and contact resistance. However, this test is carried out in a single contact hole pattern, and cannot reflect the resistance of the contact hole in some special layout of the chip.

[0003] Especially in SRAM (Static Random Access Memory) layout, the density of contact hole is the tightest. Currently, the test method of contact hole in WAT (Wafer Acceptance Test) test cannot fully reflect the actual resistance situation in SRAM, so the contact hole process of SRAM cannot be monitored.

[0004] In order to solve the above problems, a new layout for testing contact hole resistance is needed. SUMMARY

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a layout for testing contact hole resistance, which solves the problem in the prior art that the test method of contact hole in WAT test cannot fully reflect the actual resistance situation in SRAM in SRAM layout, so the contact hole process of SRAM cannot be monitored.

[0006] To achieve the above-mentioned purposes and other related purposes, the present application provides a layout for testing contact hole resistance, comprising:

[0007] a first active area pattern;

[0008] a first and a second gate pattern crossing the first active area pattern, and the first active area pattern separates the first and the second gate pattern;

[0009] a first contact hole pattern arranged between the first and the second gate pattern and on the first active area pattern;

[0010] Second and third contact hole patterns respectively arranged on two sides of the first and second gate patterns and on the first active region pattern;

[0011] First to third metal layer patterns respectively arranged on the first to third contact hole patterns;

[0012] A third gate pattern;

[0013] A fourth contact hole pattern arranged on the third gate pattern, and fifth and sixth contact hole patterns arranged on both ends of the fourth contact hole pattern and on the third gate pattern;

[0014] Fourth to sixth metal layer patterns respectively arranged on the fourth to sixth contact hole patterns.

[0015] Preferably, the gate patterns in the layout are equidistantly distributed in sequence.

[0016] Preferably, the first contact hole is square in shape.

[0017] Preferably, the fourth contact hole pattern is square in shape.

[0018] Preferably, the first active region pattern does not overlap with gate patterns other than the first and second gate patterns.

[0019] Preferably, the first to sixth metal layer patterns do not overlap with each other.

[0020] Preferably, a connection pattern is arranged on adjacent gate patterns in the layout.

[0021] Preferably, the second and third contact hole patterns are both rectangular in shape, and are arranged on the first active region pattern and the fourth gate pattern, and on the first active region pattern and the fifth gate pattern, respectively.

[0022] Preferably, the fifth and sixth contact hole patterns are both rectangular in shape, and are arranged on the third gate pattern and the second active region pattern, and on the third gate pattern and the third active region pattern, respectively.

[0023] Preferably, the layout is used for contact hole resistance value testing of a static random access memory.

[0024] As described above, the layout for testing contact hole resistance values of the present application has the following beneficial effects:

[0025] The device manufactured by the layout of the present application can test the resistance values of two types of contact holes on active regions and on gate electrodes, respectively. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1The diagram shows a schematic layout of the contact hole resistance values ​​in the active region for the test of this invention.

[0027] Figure 2 The diagram shows a schematic layout of the contact hole resistance values ​​on the gate for testing purposes according to the present invention.

[0028] Figure 3 The diagram shows a test device for the contact hole resistance value in the active region according to the present invention.

[0029] Figure 4 The diagram shows a test device for the contact hole resistance on the gate according to the present invention. Detailed Implementation

[0030] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0031] Please see Figure 1 and Figure 2 This invention provides a layout for testing the resistance of a contact hole, comprising:

[0032] Please see Figure 1 The partial layout shown includes the first active region graphic 01;

[0033] The first and second gate patterns (02, 03) span the first active region pattern 01, and the first active region pattern 01 separates the first and second gate patterns (02, 03), that is, the first and second gate patterns (02, 03) are divided into gate patterns that are spaced apart by upper and lower parts.

[0034] In embodiments of the present invention, the gate patterns in the layout are distributed sequentially at equal intervals.

[0035] In an embodiment of the present invention, adjacent gate patterns in the layout are provided with connection patterns.

[0036] In an embodiment of the present invention, the first active region pattern 01 does not overlap with the gate patterns other than the first and second gate patterns (02, 03).

[0037] A first contact hole pattern 04 is disposed between the first and second gate patterns (02, 03) and on the first active region pattern 01;

[0038] In an embodiment of the present invention, the first contact hole is square in shape.

[0039] The second and third contact hole patterns (05, 06) are respectively arranged on the left and right sides of the first and second gate patterns (02, 03) and on the first active area pattern 01;

[0040] In the embodiment of the present application, the shapes of the second and third contact hole patterns (05, 06) are both rectangular, which are respectively arranged on the first active area pattern 01 and the fourth gate pattern 17, and the first active area pattern 01 and the fifth gate pattern 18.

[0041] The first to third metal layer patterns (07, 08, 09) are respectively arranged on the first to third contact hole patterns, wherein the left end of the first metal layer pattern 07 and the left end of the second metal layer pattern 08 form a current test loop between the first contact hole pattern 04 and the second contact hole pattern 05; and the right end of the first metal layer pattern 07 and the right end of the third metal layer pattern 09 form a voltage test loop between the first contact hole pattern 04 and the third contact hole pattern 06.

[0042] In the embodiment of the present application, please refer to Figure 3 The device prepared can test the resistance of the contact hole on the active area.

[0043] Please refer to Figure 2 The partial layout shown includes the third gate pattern 10;

[0044] The fourth contact hole pattern 11 is arranged on the third gate pattern 10, and the fifth and sixth contact hole patterns (12, 13) are arranged on both ends of the fourth contact hole pattern 11 and on the third gate pattern 10.

[0045] In the embodiment of the present application, the fifth and sixth contact hole patterns (12, 13) are both arranged on the left side of the third gate pattern 10, the fifth and sixth contact hole patterns (12, 13) are both arranged on the third gate pattern 10, and the fifth contact hole pattern 12 is located at the upper end of the fourth contact hole pattern 11, and the sixth contact hole pattern 13 is located at the lower end of the fourth contact hole pattern 11.

[0046] In the embodiment of the present application, the shape of the fourth contact hole pattern 11 is square.

[0047] The fourth to sixth metal layer patterns (15, 14, 16) are respectively arranged on the fourth to sixth contact hole patterns (11, 12, 13), wherein the left end of the fourth metal layer pattern 15 and the left end of the sixth metal layer pattern 16 form a voltage test loop between the fourth contact hole pattern 11 and the sixth contact hole pattern 13; and the right end of the fourth metal layer pattern 15 and the right end of the fifth metal layer pattern 14 form a current test loop between the fourth contact hole pattern 11 and the fifth contact hole pattern 12.

[0048] In the embodiment of the present application, the fifth and sixth contact hole patterns (12, 13) are rectangular, and are respectively arranged on the third gate pattern 10 and the second active area pattern 19, and on the third gate pattern 10 and the third active area pattern 20.

[0049] In the embodiment of the present application, referring to Figure 4 The device manufactured by the layout can test the resistance of the contact hole on the gate.

[0050] In the embodiment of the present application, the first to sixth metal layer patterns do not overlap with each other.

[0051] In the embodiment of the present application, the layout is used for testing the resistance of the contact hole of the static random access memory.

[0052] It is to be noted that the drawings provided in the embodiments only schematically illustrate the basic concept of the present application, and only the components related to the present application are shown in the drawings, rather than the number, shape and size of the components in actual implementation. The type, number and proportion of the components in actual implementation can be arbitrarily changed, and the layout type of the components can be more complicated.

[0053] In summary, the device manufactured by the layout of the present application can test the resistance of two types of contact holes, i.e. the contact hole on the active area and the contact hole on the gate. Therefore, the present application effectively overcomes the disadvantages of the prior art and has high industrial utilization value.

[0054] The above embodiments only illustratively explain the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought of the present application should be covered by the claims of the present application.

Claims

1. A layout structure for testing resistance of a contact hole, characterized by, At least comprising: a first active region pattern; a first and a second gate pattern across the first active region pattern, and the first active region pattern separates the first and the second gate pattern; a first contact hole pattern provided between the first and the second gate pattern, and on the first active region pattern; a second and a third contact hole pattern provided on both sides of the first and the second gate pattern, and on the first active region pattern; a first to a third metal layer pattern provided on the first to the third contact hole pattern respectively, wherein the first metal layer pattern and the second metal layer pattern form a current test loop between the first contact hole pattern and the second contact hole pattern, and the first metal layer pattern and the third metal layer pattern form a voltage test loop between the first contact hole pattern and the third contact hole pattern; a third gate pattern; a fourth contact hole pattern provided on the third gate pattern, and a fifth and a sixth contact hole pattern provided on both ends of the fourth contact hole pattern, and on the third gate pattern; a fourth to a sixth metal layer pattern provided on the fourth to the sixth contact hole pattern respectively, wherein the fourth metal layer pattern and the fifth metal layer pattern form a current test loop between the fourth contact hole pattern and the fifth contact hole pattern, and the fourth metal layer pattern and the sixth metal layer pattern form a voltage test loop between the fourth contact hole pattern and the sixth contact hole pattern.

2. The test contact hole resistance value layout structure according to claim 1, wherein: The gate patterns in the layout are distributed equidistantly in sequence.

3. The test contact hole resistance value layout structure according to claim 1, wherein: The shape of the first contact hole is square.

4. The test contact hole resistance value layout structure according to claim 3, wherein: The shape of the fourth contact hole pattern is square.

5. The test contact hole resistance value layout structure according to claim 1, wherein: The first active region pattern does not overlap with gate patterns other than the first and the second gate pattern.

6. The test contact hole resistance value layout structure according to claim 1, wherein: The first to the sixth metal layer patterns do not overlap with each other.

7. The test contact hole resistance value layout structure according to claim 1, wherein: A connection pattern is provided on adjacent gate patterns in the layout.

8. The test contact hole resistance value layout structure according to claim 1, wherein: The shapes of the second and the third contact hole pattern are both rectangular, and they are provided on the first active region pattern and the fourth gate pattern, and on the first active region pattern and the fifth gate pattern respectively.

9. The test contact hole resistance value layout structure according to claim 1, wherein: The shapes of the fifth and the sixth contact hole pattern are both rectangular, and they are provided on the third gate pattern and the second active region pattern, and on the third gate pattern and the third active region pattern respectively.

10. The test contact hole resistance value layout structure according to claim 1, wherein: The layout is used for contact hole resistance value test of static random access memory.

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