semiconductor devices

Abstract

The present invention provides a semiconductor device, which can integrate a rectifier element into a gate driver IC and is less likely to cause adverse conditions such as increased leakage current, reduced withstand voltage, and element damage. The semiconductor device comprises: a semiconductor substrate (110) having a p-type substrate (111) and an n-type first semiconductor layer (112); a first electrode (120); a second electrode (130); an element separation film (140); an insulating film (150); and a third electrode (160) arranged on the insulating film (150), wherein the first electrode (120) is electrically connected to a first circuit C1 connected to a first power source Vin, and the second electrode (130) is electrically connected to a second circuit C2 connected to a second power source Vcc. The semiconductor substrate (110) further comprises a p-type back gate region (113), which is formed in a region opposite to the third electrode (160) at a depth that reaches the substrate (111) at least through the insulating film (150) and has an impurity concentration of 1×10 10 cm ‑3 ~1×10 15 cm ‑3 within the range.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] A known power conversion circuit (e.g., an inverter) includes a high-side switch connected to a high-voltage power supply (DC input power supply Vin) and a low-side switch connected to the high-side switch. In such a power conversion circuit (hereinafter referred to as a conventional power conversion circuit), when an n-channel transistor with low on-resistance is used as the high-side switch, a gate voltage exceeding a threshold voltage Vgs (Vth) must be applied between the gate and source of the high-side switch to turn on the high-side switch. This causes the source voltage to rise to the voltage of the DC input power supply Vin. Therefore, a gate voltage higher than the voltage of the DC input power supply Vin must be applied. To generate such a high gate voltage, a bootstrap circuit is generally required (see, for example, Patent Document 1).

[0003] Figure 8 1 is a circuit diagram showing a conventional power conversion circuit 9 .

[0004] like Figure 8 As shown, the conventional power conversion circuit 9 includes a high-side switch Q1 , a low-side switch Q2 , a gate driver IC 10 (IC: integrated circuit), and a bootstrap circuit 20 .

[0005] The bootstrap circuit 20 has a capacitor 22 (bootstrap capacitor) and a bootstrap diode 24 as a rectifying element. One electrode of the capacitor 22 is connected to the connection point N between the high-side switch Q1 and the low-side switch Q2, and the other electrode is connected to the high-side drive circuit 11 of the gate driver IC10. The anode of the bootstrap diode 24 is connected to the driving power supply Vcc as a low voltage source, and the cathode is connected to the capacitor 22 and the high-side drive circuit 11. The high-side switch Q1 and the low-side switch Q2 are configured in a high-voltage area, and the low-side drive circuit 12 of the gate driver IC10 is configured in a lower voltage area. In addition, the capacitor 22 and the bootstrap diode 24 of the bootstrap circuit 20 are generally installed as external components of the gate driver IC10.

[0006] In the conventional bootstrap circuit 20, when the high-side switch Q1 is off and the low-side switch Q2 is on, the capacitor 22 is charged from the driving power supply Vcc via the bootstrap diode 24. Then, when the low-side switch Q2 is turned off, the voltage Vs at the connection point N between the high-side and low-side switches Q1 and Q2 (the source voltage of the high-side switch Q1) rises to the output voltage of the DC input power supply Vin. A voltage resulting from the superposition of the voltage of the capacitor 22 on the voltage at the connection point N is applied to the high-side drive circuit 11. This allows a gate voltage higher than the voltage of the DC input power supply Vin to be applied to the high-side switch Q1, turning on the high-side switch Q1.

[0007] Furthermore, the bootstrap diode 24 as a rectifying element allows current to flow from the driving power supply Vcc to the capacitor 22 (forward bias) when the high-side switch Q1 is off and the low-side switch Q2 is on. The voltage of the capacitor 22 is controlled by the high-side driving circuit 11 .

[0008]

Prior Technical Literature

[0009] [Patent Document 1] Japanese Patent Application Laid-Open No. 9-65571

[0010] However, with the recent demand for miniaturization of electrical equipment, there is a demand for integrating rectifier elements, which were once external components, into the gate driver IC 10. In this case, miniaturization is preferably achieved by integrating the rectifier elements with the semiconductor substrate. Therefore, it is considered possible to form the bootstrap diode 24 on the semiconductor substrate by using a semiconductor device with the following structure (hereinafter referred to as the background semiconductor device 900).

[0011] Figure 9 This is a cross-sectional view shown for explaining a semiconductor device 900 according to the background art.

[0012] The semiconductor device 900 of the related art is as follows Figure 9 As shown, it includes: a semiconductor substrate 910, having a p-type (p-type) substrate 911, an n-type (n-type) first semiconductor layer 912, an n-type (n+ type) first contact region CR1, and a p-type (p+ type) anode region 919; a first electrode 920 arranged above the semiconductor substrate 910 and in contact with the semiconductor substrate 910; a second electrode 930 arranged at a position separated from the first electrode 920 above the semiconductor substrate 910 and in contact with the semiconductor substrate 910; an element separation film 940 formed on the area between the first electrode 920 and the second electrode 930 on the surface of the semiconductor substrate 910; an insulating film 950 arranged between the second electrode 930 and the element separation film 940 on the surface of the semiconductor substrate 910; and a third electrode 960 arranged on the insulating film 950, wherein the bootstrap diode 24 is composed of the p-type anode region 919 and the n-type first semiconductor layer 912.

[0013] However, in the semiconductor device 900 of the background technology, there is a problem that after the parasitic transistor composed of the p-type anode region 919, the n-type first semiconductor layer 912 and the p-type substrate 911 is turned on, a parasitic current flows between the second electrode 930 and the substrate 911, resulting in an increase in leakage current and a decrease in withstand voltage, damage to the component and other adverse conditions, making it difficult to form a bootstrap diode as a rectifying element on the semiconductor substrate.

[0014] In view of this situation, the object of the present invention is to provide a semiconductor device that is not prone to causing adverse conditions such as increased leakage current, reduced withstand voltage, and component damage even if a rectifier element is formed on a semiconductor substrate, and that can form a rectifier element on a semiconductor substrate and can integrate the rectifier element into a gate driver IC. Summary of the Invention

[0015] The semiconductor device of the present invention is characterized by comprising: a semiconductor base having a substrate of a first conductivity type and a first semiconductor layer of a second conductivity type formed on the substrate; a first electrode arranged above the semiconductor base and in contact with the semiconductor base; a second electrode arranged at a position above the semiconductor base separated from the first electrode and in contact with the semiconductor base; an element separation film formed in a region between the first electrode and the second electrode on the surface of the semiconductor base; an insulating film arranged between the second electrode and the element separation film on the surface of the semiconductor base; and a third electrode arranged on the insulating film, wherein the first electrode is electrically connected to a first circuit connected to a first power supply, and the second electrode is electrically connected to a second circuit connected to a second power supply, and the semiconductor base further has a back gate region of the first conductivity type, the back gate region being formed in a region opposite to the third electrode at a depth that reaches the substrate at least through the insulating film, and having an impurity concentration of 1×10 10 cm -3 ~1×10 15 cm -3 within the range.

[0016] According to the semiconductor device of the present invention, since the semiconductor substrate includes a back-gate region of the first conductivity type extending to a depth reaching the substrate, at least in the region opposite the third electrode across the insulating film, a field-effect transistor can be formed by the second electrode, the back-gate region, the first semiconductor layer, the insulating film, and the third electrode. Therefore, when the voltage Vcc of the second electrode is greater than the voltage Vb of the first electrode, the third electrode can be turned on, allowing current to flow from the second electrode to the first electrode to charge the capacitor. When the voltage Vcc of the second electrode is less than the voltage Vb of the first electrode, the third electrode can be turned off, cutting off the current. This allows the device to function as a rectifier, similar to a conventional bootstrap diode.

[0017] However, in a bootstrap circuit, when a bootstrap diode is used as a rectifying element, a voltage drop corresponding to the feedforward voltage, which is a characteristic of a diode, occurs. This causes a drop in the voltage applied to the capacitor from the driving power supply Vcc, making it difficult to charge the capacitor to a voltage close to the driving power supply Vcc. In contrast, the semiconductor device according to the present invention uses a field effect transistor composed of a second electrode, a back gate region, a first semiconductor layer, an insulating film, and a third electrode as a rectifying element. Therefore, unlike when a bootstrap diode is used, a voltage drop corresponding to the feedforward voltage does not occur, thereby enabling the capacitor to be charged to a voltage close to the driving power supply Vcc (see FIG. 1 ). Figure 5 ).

[0018] However, in order to turn on the field effect transistor, a voltage higher than the source electrode needs to be applied between the gate and the source. Therefore, in the bootstrap circuit, when the field effect transistor is used as a rectifier, a voltage higher than the driving power supply Vcc needs to be applied to the gate electrode (third electrode). Otherwise, the field effect transistor cannot be turned on. Moreover, when it is necessary to reduce the voltage applied to the substrate, the threshold voltage becomes higher due to the substrate bias effect, so it is necessary to further increase the voltage applied to the gate electrode (third electrode). According to the semiconductor device of the present invention, since the impurity concentration of the back gate region is 1×10 10 cm -3 ~1×10 15 cm -3 The threshold voltage is extremely low (close to 0V), making channel formation easier. Furthermore, since the electric field diffused into the back gate region is reduced, the effects of substrate bias are reduced. This eliminates the need to apply an unnecessary high voltage to the third electrode to turn on the semiconductor device, allowing the semiconductor device to be turned on and off with an appropriate voltage.

[0019] According to the semiconductor device of the present invention, the semiconductor substrate has a back gate region of the first conductivity type reaching the depth of the substrate at least in the region opposite to the third electrode across the insulating film, and a field effect transistor is formed by the second electrode, the back gate region, the first semiconductor layer, the insulating film, and the third electrode. Therefore, it is not easy to form a parasitic transistor that is the cause of the parasitic current flowing between the second electrode 130 and the substrate. In this way, it is not easy to produce adverse conditions such as an increase in leakage current, a decrease in withstand voltage, and damage to components due to parasitic current, and a rectifier element can be formed on the semiconductor substrate. As a result, the rectifier element can be built into the gate driver IC.

[0020] In addition, in the semiconductor device according to the present invention, since there is an element isolation film in the region between the first electrode and the second electrode formed on the surface of the semiconductor substrate, and a surface electric field reduction structure is formed by the substrate of the semiconductor substrate, the first semiconductor layer, and the element isolation film, the voltage applied to the first electrode with a relatively high voltage can be reduced so as to approach the voltage of the second electrode connected to a circuit with a lower voltage. In this way, a region with a relatively high voltage and a region with a relatively low voltage can be formed on the same semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a circuit diagram for explaining the power conversion circuit 1 in Embodiment 1.

[0022] Figure 2 is a cross-sectional view of the semiconductor device 100 according to Embodiment 1.

[0023] Figure 3 is a cross-sectional view for explaining the state of the semiconductor device 100 according to Embodiment 1 during conduction (during charging, Vcc > Vb).

[0024] Figure 4 is a cross-sectional view for explaining the state of the semiconductor device 100 according to Embodiment 1 during non-conduction (during reverse bias, Vcc < Vb).

[0025] Figure 5 is a graph showing the relationship between the voltage Vb on the side of the first electrode 120 and the charging current Ib during conduction (charging) and non-conduction (reverse bias).

[0026] Figure 6 is a cross-sectional view for explaining the semiconductor device 101 according to Embodiment 2.

[0027] Figure 7 is a cross-sectional view for explaining the semiconductor device 102 according to Embodiment 3.

[0028] Figure 8 is a circuit diagram for explaining the existing power conversion circuit 9.

[0029] Figure 9 is a cross-sectional view of the semiconductor device 900 for explaining the background art. In the figure, the symbol 922 represents the first field plate, the symbol 962 represents the second field plate, and the symbol 964 represents the external connection portion. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] Hereinafter, the semiconductor device of the present invention will be described with reference to the drawings. In addition, each drawing is a schematic diagram and does not strictly reflect the actual dimensions.

[0031]

Embodiment 1

[0032] 1. Structure of the Power Conversion Circuit 1 in Embodiment 1

[0033] First, a power conversion circuit 1 according to the first embodiment, which includes a bootstrap FET (semiconductor device 100 according to the first embodiment) as a semiconductor device of the present invention, will be described. Figure 1 1 is a circuit diagram for explaining the power conversion circuit 1 in the first embodiment. Figure 1 As shown, the power conversion circuit 1 in the first embodiment includes a high-side switch Q1 , a low-side switch Q2 , a capacitor 22 , and a gate driver IC 10 .

[0034] The high-side switch Q1 is connected to the DC input power supply Vin. One end of the low-side switch Q2 is connected to the high-side switch Q1, and the other end is connected to a reference potential. Suitable switching elements can be used as the high-side switch Q1 and the low-side switch Q2. In the first embodiment, MOSFETs (metal-oxide-semiconductor field-effect transistors) are used.

[0035] The high-side switch Q1 and the low-side switch Q2 form part of a main circuit C1 as a first circuit, and the output terminal OUT is connected to a connection point N between the high-side switch Q1 and the low-side switch Q2. The main circuit C1 is connected to a DC input power supply Vin (first power supply).

[0036] One electrode of the capacitor 22 is connected to the connection point N between the high-side switch Q1 and the low-side switch Q2, and the other electrode is connected to the high-side drive circuit 11 of the gate driver IC 10. The capacitor 22 is mounted as an external component of the gate driver IC 10.

[0037] The gate driver IC 10 includes a high-side drive circuit 11 , a low-side drive circuit 12 , a bootstrap FET (the semiconductor device 100 according to the first embodiment), and a plurality of terminals (a terminal Vb, a terminal Vs, a terminal HO, a terminal LO, and a terminal GND).

[0038] The high-side driver circuit 11 controls the on / off switching of the high-side switch Q1. The high-side driver circuit 11 is connected to the connection point N between the high-side switch Q1 and the low-side switch Q2 via the Vs terminal. Furthermore, the high-side driver circuit 11 is connected to the bootstrap FET (the semiconductor device 100 of the first embodiment) and to the capacitor 22 via the Vb terminal. Furthermore, the high-side driver circuit 11 is connected to the gate electrode of the high-side switch Q1 via the output terminal HO.

[0039] The low-side driver circuit 12 controls the on / off switching of the low-side switch Q2. The low-side driver circuit 12 forms part of the second circuit C2 and is connected to the drive power supply Vcc (second power supply). It is also connected to the ground potential via the GND terminal and to the gate electrode of the low-side switch Q2 via the output terminal LO. Furthermore, the second power supply voltage, which is the output voltage of the drive power supply Vcc (second power supply), is lower than the first power supply voltage, which is the output voltage of the DC input power supply Vin (first power supply).

[0040] One electrode of the bootstrap FET (semiconductor device 100 according to the first embodiment) is connected to the low-side drive circuit 12 and the drive power supply Vcc, while the other electrode is connected to the capacitor 22 and the high-side drive circuit 11. The gate of the bootstrap FET (semiconductor device 100 according to the first embodiment) is connected to the electrode (one electrode) on the drive power supply Vcc side, and the back gate BG is connected to a reference potential. The bootstrap FET (semiconductor device 100 according to the first embodiment) and capacitor 22 constitute the bootstrap circuit 20.

[0041] As the bootstrap FET of the present invention, field effect transistors of various structures can be used, but in embodiment one, in order to be able to be built into the gate driver IC, a semiconductor device 100 involved in embodiment one formed on the same semiconductor substrate as the high-side drive circuit 11 and the low-side drive circuit 12 can be used as a field effect transistor.

[0042] 2. Structure of the Semiconductor Device 100 According to the First Embodiment

[0043] Figure 2 1 is a cross-sectional view for explaining the semiconductor device 100 according to the first embodiment. Figure 2 As shown, the semiconductor device 100 according to the first embodiment includes a semiconductor substrate 110, a first electrode 120, a first field plate 122, a second electrode 130, an element isolation film 140, insulating films 150 and 152, a third electrode 160, a second field plate 162, a connecting portion 164, and a fourth electrode 170. Although not shown, the semiconductor device 100 according to the first embodiment is formed on the same semiconductor substrate as at least a portion of the high-side driver circuit 11 and the low-side driver circuit 12, and is incorporated into the gate driver IC 10.

[0044] The semiconductor base 110 is composed of a predetermined semiconductor material. A p-type (p-type) substrate 111 is formed over the entire lower portion of the semiconductor base 110. An n-type (n-type) first semiconductor layer 112 is formed in a predetermined region on the substrate 111, and a p-type (p-type) back gate region 113 is formed in a region of the substrate 111 adjacent to the first semiconductor layer 112. Furthermore, the boundary between the first semiconductor layer 112 and the back gate region 113 is located at a position opposing a third electrode 160 (described later) across an insulating film 150 formed on the surface of the semiconductor base 110. A portion of the back gate region 113 is formed in a region opposing the third electrode 160 across the insulating film 150.

[0045] The back gate region 113 has the same composition as the substrate 111 and is formed continuously with the substrate 111. The back gate region 113 is formed to a depth from the surface of the semiconductor body 110 to the substrate 111. The impurity concentration of the substrate 111 and the back gate region 113 is between 1×10 10 cm -3 ~1×10 15 cm -3 The concentration is lower than that in the general back gate region.

[0046] In the region where the first semiconductor layer 112 is formed, an n-type (n+-type) first contact region CR1 is formed on a portion of the surface of the first semiconductor layer 112 in a region opposite to the back gate region 113. In other words, the first contact region CR1 is formed on the surface of the first semiconductor layer 112 on the side opposite to the back gate region 113 across the element isolation film 140 (described later). The impurity concentration in the first contact region CR1 is higher than that in the first semiconductor layer 112.

[0047] In the region where the back gate region 113 is formed, an n-type (n+ type) second contact region CR2 is formed on a portion of the surface of the back gate region 113. Furthermore, a p-type (p+ type) third contact region CR3 is formed on a portion of the surface of the back gate region 113 at a position farther from the first semiconductor layer 112 than the second contact region CR2. The impurity concentration of the second contact region CR2 is higher than that of the first semiconductor layer 112, and the impurity concentration of the third contact region CR3 is higher than that of the substrate 111.

[0048] An element separation film 140 is formed on the surface of the central region of the first semiconductor layer 112. An insulating film 152 is formed on the surface of the semiconductor substrate 110 (first semiconductor layer 112) on the side opposite to the back gate region 113 relative to the element separation film 140. An insulating film 150 is formed on the surface of the semiconductor substrate 110 (first semiconductor layer 112 and back gate region 113) on the back gate region 113 side relative to the element separation film 140. The element separation film 140 is a LOCOS film composed of SiO2, and approximately half of its thickness is buried in the semiconductor substrate 110. In addition, a structure for reducing the surface electric field is formed by the element separation film 140, the substrate 111 of the semiconductor substrate 110, and the first semiconductor layer 112. The insulating films 150 and 152 are thermal oxide films.

[0049] The first electrode 120 is disposed above the semiconductor substrate 110 at a position opposite to the side of the element isolation film 140 where the back gate region 113 is formed. The first electrode 120 contacts the first contact region CR1 of the semiconductor substrate 110 via an opening formed in the insulating film 152. The first electrode 120 is connected to the high-side drive circuit 11 and the capacitor 22 and is electrically connected to the main circuit C1 via the capacitor 22 (see FIG. 1 ). Figure 1 ). The first electrode 120 is made of metal (eg, aluminum).

[0050] The first field plate 122 covers the insulating film 152 and the element isolation film 140 from the surface of the insulating film 152 to the surface of the element isolation film 140 and is connected to the first electrode 120. In the first embodiment, the first field plate 122 is made of polysilicon, but may also be made of a metal (e.g., aluminum) or a silicide (e.g., aluminum silicide (AlSi), nickel silicide (NiSi), or other metal silicide.

[0051] The second electrode 130 is disposed above the semiconductor substrate 110 at a position opposite the first electrode 120 across the element isolation film 140 (thus, the element isolation film 140 is formed in the region between the first electrode 120 and the second electrode 130). The second electrode 130 is electrically connected to the external drive power supply Vcc and the low-side drive circuit 12. The second electrode 130 contacts the second contact region CR2 of the semiconductor substrate 110 through an opening formed in the insulating film 150. The second electrode 130 is made of metal (e.g., aluminum).

[0052] The third electrode 160 is a film-like member disposed on the insulating film 150 at a position in contact with the element isolation film 140. While the third electrode 160 is a film-like member in the first embodiment, a non-film-like member may also be used. The third electrode 160 is disposed opposite a portion of the back gate region 113 and a portion of the first semiconductor layer 112 via the insulating film 150.

[0053] The second field plate 162 is connected to the third electrode 160 and formed on the surface of the element isolation film 140. The second field plate 162 is integrated with the third electrode 160. In the first embodiment, although the third electrode 160 and the second field plate 162 are made of polysilicon, they may also be made of a metal (such as aluminum), a silicide (such as aluminum silicide (AlSi), nickel silicide (NiSi, etc. metal silicides)) or other suitable conductors.

[0054] One side of the connecting portion 164 is connected to the second electrode 130, and the other side extends on the second field plate 162 and is connected to the second field plate 162. The connecting portion 164 is made of a metal (such as aluminum).

[0055] The fourth electrode 170 is connected to the third contact region CR3 and the back gate region 113 of the semiconductor substrate 110 via an opening formed in the insulating film 150. Since the fourth electrode 170 is connected to an external reference potential, the potentials of the substrate 111 and the back gate region 113 are the reference potential.

[0056] 3. Operation of the semiconductor device 100 according to the first embodiment

[0057] Next, the function of the rectifying element as a bootstrap circuit included in the semiconductor device 100 according to the first embodiment will be described. Figure 3 It is a cross-sectional view for explaining the state of the semiconductor device 100 according to the first embodiment during conduction (during charging, Vcc > Vb). Figure 4 It is a cross-sectional view for explaining the state of the semiconductor device 100 according to the first embodiment during non-conduction (during reverse bias, Vcc < Vb).

[0058] (1) During conduction (during charging, Vcc > Vb)

[0059] When the low-side switch Q2 is turned on, the driving power supply voltage Vcc becomes larger than the voltage Vb on the capacitor 22 side. In the semiconductor device 100 of the first embodiment, the first electrode 120 is connected to the capacitor 22, and the second electrode 130 is connected to the driving power supply Vcc. Therefore, the semiconductor device 100 of the first embodiment has the same structure as an n-channel MOS with the first electrode 120 as the source electrode, the second electrode 130 as the drain electrode, and the third electrode 160 as the gate electrode (refer to Figure 3). Furthermore, the third electrode 160, serving as the gate electrode, is connected to the second electrode 130, serving as the drain electrode. This generates a gate-source voltage, causing the gate electrode to be conductive, and the channel region 113 is formed facing the third electrode 160 via the insulating film 150. Consequently, current flows from the driving power supply Vcc through the second electrode 130, the channel region 113', the first semiconductor layer 112, the first contact region CR1, and the first electrode 120 to the capacitor 22, thereby charging the capacitor 22.

[0060] (2) When non-conducting (when the body diode is reverse biased, Vcc <Vb)

[0061] When the low-side switch Q2 is turned off, the voltage Vs at the connection point N between the high-side switch Q1 and the low-side switch Q2 increases, and accordingly, the voltage Vb also increases. After a while, the voltage Vcc of the driving power supply becomes lower than the voltage Vb on the capacitor 22 side. Therefore, the semiconductor device 100 according to the first embodiment has the same structure as an n-channel MOS having the first electrode 120 as a drain electrode, the second electrode 130 as a source electrode, and the third electrode 160 as a gate electrode (see Figure 4 ). Furthermore, since the third electrode 160 serving as the gate electrode is connected to the second electrode 130 serving as the source electrode, the gate-source voltage is zero, and no channel region 113' is formed in the back gate region 113, and the semiconductor device 100 is in a non-conducting state (the body diode formed by the p-type back gate region 113 and the n-type first semiconductor layer 112 is reverse biased). Therefore, when the voltage of the capacitor 22 is superimposed on the high-side drive circuit 11, current does not flow from the capacitor 22 to the drive power supply Vcc, thereby preventing current from flowing back from the capacitor 22 to the drive power supply Vcc.

[0062] Next, the relationship between the voltage Vb and the charging current Ib flowing through the semiconductor device 100 will be described. Figure 5 is a graph showing the relationship between the voltage Vb and the charging current Ib flowing through the semiconductor device 100 .

[0063] like Figure 5 As shown, when voltage Vb is low, since voltage Vcc of the driving power supply is higher than voltage Vb on the capacitor 22 side, semiconductor device 100 is turned on, and charging current Ib flows from driving power supply Vcc to capacitor 22. Then, as capacitor 22 is charged, voltage Vb gradually increases. As the difference between voltage Vcc of driving power supply Vcc and voltage Vb of capacitor 22 decreases, charging current Ib gradually decreases.

[0064] Since the semiconductor device according to the first embodiment, which is a field-effect transistor, is used as the rectifying element, a voltage drop similar to that of a bootstrap diode is less likely to occur. Therefore, charging current Ib flows until voltage Vb reaches a voltage close to voltage Vcc. In semiconductor device 100 according to the first embodiment, the impurity concentration in back gate region 113 is very low, resulting in a very low threshold voltage. Even when voltage Vb approaches voltage Vcc, charging current Ib maintains a predetermined current value.

[0065] When the voltage Vcc of the second electrode becomes approximately the same as the voltage Vb of the first electrode, the charging current Ib drops sharply and flows almost to zero. If the voltage Vcc of the second electrode is lower than the voltage Vb of the first electrode, the channel region of the semiconductor device 100 disappears and is reverse biased, and the charging current Ib flows almost to zero.

[0066] As described above, the semiconductor device 100 according to the first embodiment functions as a rectifying element that controls charging and discharging of a capacitor.

[0067] 4. Effects of the Semiconductor Device 100 According to the First Embodiment

[0068] According to the semiconductor device 100 of the first embodiment, the semiconductor base 110 includes an n-type back gate region 113 extending to a depth reaching the substrate 111, at least in a region facing the third electrode 160 via the insulating film 150. Furthermore, a field-effect transistor is formed by the second electrode 130, the back gate region 113, the first semiconductor layer 112, the insulating film 150, and the third electrode 160. Therefore, when the voltage Vcc of the second electrode 130 is greater than the voltage Vb of the first electrode 120, the third electrode 160 is turned on, allowing current to flow from the second electrode 130 to the first electrode 120, charging the capacitor. When the voltage Vcc of the second electrode 130 is less than the voltage Vb of the first electrode 120, the third electrode 160 is turned off, blocking the current. This allows the device to function as a rectifying element, similar to a conventional bootstrap diode.

[0069] In a bootstrap circuit, when a bootstrap diode is used as a rectifying element, a voltage drop corresponding to the feedforward voltage will be generated due to the characteristics of the diode, so the voltage applied from the driving power supply Vcc to the capacitor will drop, making it difficult to charge the capacitor to a voltage close to the driving power supply Vcc. In contrast, according to the semiconductor device 100 of the first embodiment, since the field effect transistor composed of the second electrode 130, the back gate region 113, the first semiconductor layer 112, the insulating film 150 and the third electrode 160 is used as a rectifying element, a voltage drop corresponding to the feedforward voltage will not be generated as when a bootstrap diode is used. As a result, the capacitor 22 can be charged to a voltage close to the driving power supply Vcc (see Figure 5 ).

[0070] However, in order to turn on the field effect transistor, a voltage higher than the source electrode needs to be applied between the gate and the source. Therefore, in the bootstrap circuit, when the field effect transistor is used as a rectifier element, a voltage higher than the driving power supply Vcc needs to be applied to the gate electrode (third electrode) to turn on the field effect transistor. In addition, when the voltage applied to the substrate is to be reduced, the threshold voltage becomes higher due to the substrate bias effect, so the voltage applied to the gate electrode (third electrode) needs to be further increased. However, according to the semiconductor device 100 of the first embodiment, since the impurity concentration of the back gate region 113 is 1×10 10 cm -3 ~1×10 15 cm -3 The threshold voltage is extremely low (close to 0V), making it easier to form the channel region 113'. Furthermore, since the electric field extending to the back gate region 113 is reduced, the influence of the substrate bias effect can be reduced. This eliminates the need to apply an unnecessary high voltage to the third electrode 160 to turn on the semiconductor device, allowing the semiconductor device to be turned on and off with an appropriate voltage.

[0071] In addition, the reason why the impurity concentration of the back gate region 113 is set to 1×10 10 cm -3 The above is because the impurity concentration of the back gate region 113 is less than 1×10 10 cm -3 In the case of reverse bias, the pn junction between the back gate region 113 and the first semiconductor layer 112 cannot fully form a potential barrier. In the case of reverse bias, reverse current may flow between the first electrode 120 and the second electrode 130, making it difficult to maintain its function as a rectifying element. In addition, the impurity concentration of the back gate region 113 is set to 1×10 15 cm -3 The following is because when the impurity concentration of the back gate region 113 exceeds 1×10 15 cm -3 In this case, the threshold voltage becomes high, making it difficult to form the channel region 113 ′, and therefore it is necessary to apply a relatively high voltage to the third electrode 160 .

[0072] Furthermore, according to the semiconductor device 100 of the first embodiment, the semiconductor substrate 110 includes a p-type back gate region 113 extending deep to the substrate 111, at least in the region facing the third electrode 160 via the insulating film 150. This reduces the likelihood of the formation of parasitic transistors, which are the primary cause of parasitic currents flowing between the second electrode 130 and the substrate 111. Consequently, the occurrence of problems such as increased leakage current, reduced withstand voltage, and device damage caused by parasitic currents is minimized, allowing the formation of rectifier elements within the semiconductor substrate. This allows the rectifier elements to be integrated into the gate driver IC.

[0073] Furthermore, according to the semiconductor device 100 of the first embodiment, since the element isolation film 140 is formed in the region between the first electrode 120 and the second electrode 130 on the surface of the semiconductor substrate 110, and the substrate 111 of the semiconductor substrate 110, the first semiconductor layer 112, and the element isolation film 140 form a surface electric field reduction structure, the voltage applied to the first electrode 120, which has a relatively high voltage, can be reduced, thereby approaching the voltage of the second electrode 130 connected to a circuit having a relatively low voltage. This allows the formation of a relatively high voltage region and a relatively low voltage region on the same substrate.

[0074] Furthermore, according to the semiconductor device 100 of the first embodiment, since the third electrode 160 is connected to the second electrode 130, even without a switching driver circuit, the third electrode 160 is forward biased when the voltage Vcc of the second electrode 130 is greater than the voltage Vb of the first electrode 120, and is reverse biased when the voltage Vcc of the second electrode 130 is less than the voltage Vb of the first electrode 120. Therefore, the semiconductor device 100 has a simple structure and functions as a rectifying element.

[0075] Furthermore, according to the semiconductor device 100 of the first embodiment, since the substrate 111 is connected to a reference potential, even when a low voltage is applied to the third electrode 160, the channel region 113' is easily formed in the back gate region 113. Furthermore, since the electric field diffused into the back gate region 113 is reduced, the influence of the substrate bias effect can be further reduced.

[0076] In addition, according to the semiconductor device 100 of embodiment 1, since the first electrode 120 is electrically connected to the drive circuit (high-side drive circuit 11) that controls the on / off state of the high-side switch Q1 of the main circuit C1 and the capacitor 22, and the second electrode 130 is electrically connected to the drive power supply Vcc, it is a semiconductor device that functions as a rectifier element of a bootstrap circuit.

[0077] In addition, according to the semiconductor device 100 of embodiment one, since the semiconductor device 100 is formed on the same semiconductor substrate as the high-side drive circuit 11 and the low-side drive circuit 12 that control the on / off of the switches Q1 and Q2 of the first circuit, the semiconductor device 100 as a rectifying element can be built into the gate driver IC, thereby being able to meet the demand for miniaturization of electronic equipment.

[0078] In addition, according to the first embodiment of the semiconductor device 100, since the semiconductor base 110 has an n-type second contact region CR2 with a higher concentration than the first semiconductor layer 112 in the region connected to the second electrode 130, and the back gate region 113 is also formed in the region between the second contact region CR2 and the substrate 111, the semiconductor base 110 can be formed by only forming the n-type first semiconductor layer 112, the first contact region CR1, the second contact region CR2 and the third contact region CR3 on the p-type semiconductor substrate. This is a semiconductor device with a simple structure and the above-mentioned effects.

[0079] [Implementation Method 2]

[0080] Figure 6 This is a cross-sectional view for explaining a semiconductor device 101 according to a second embodiment.

[0081] The semiconductor device 101 according to the second embodiment basically has the same structure as the semiconductor device 100 according to the first embodiment, but differs from the semiconductor device 100 according to the first embodiment in that the fourth electrode 170 is not provided and the n-type semiconductor region 118 is further provided. That is, in the semiconductor device 101 according to the second embodiment, Figure 6 As shown, the semiconductor body 110 includes an n-type semiconductor region 118 having a lower impurity concentration than the second contact region CR2 . The n-type semiconductor region 118 has an impurity concentration lower than that of the first semiconductor layer 112 .

[0082] In the semiconductor device 101 of the second embodiment, the fourth electrode 170 of the first embodiment is not formed, but the substrate 111 is connected to the reference potential. In addition, the second electrode 130 is not connected to the third electrode 160, and a voltage can be applied to the third electrode 160 to form a channel in the back gate region 113a.

[0083] Although the semiconductor device 101 according to the second embodiment differs from the semiconductor device 100 according to the first embodiment in that it lacks the fourth electrode 170 and further includes the n-type semiconductor region 118, similarly to the semiconductor device 100 according to the first embodiment, since the semiconductor base 110 includes a p-type back gate region 113a extending deep enough to reach the substrate 111 at least in the region facing the third electrode 160 via the insulating film 150, it is less likely to form a parasitic transistor that could be the primary cause of parasitic current flowing between the second electrode 130 and the substrate 111. Consequently, problems such as increased leakage current, reduced withstand voltage, and device damage caused by parasitic current are less likely to occur, allowing the rectifier element to be formed on the semiconductor base. This allows the rectifier element to be integrated into the gate driver IC.

[0084] In addition, according to the second embodiment of the semiconductor device 101, since the semiconductor base 110 has, in the area connected to the second electrode 130, an n-type second contact region CR2 having a higher concentration than that of the first semiconductor layer 112, and an n-type semiconductor region 118 formed in the area surrounding the second contact region CR2 and having a lower concentration than that of the second contact region CR2, the withstand voltage between the third electrode 160 serving as the gate electrode and the second electrode 130 serving as the source electrode can be ensured when reverse biased.

[0085] Furthermore, the semiconductor device 101 of the second embodiment has the same structure as the semiconductor device 100 of the first embodiment except that the fourth electrode 170 is not provided and the n-type semiconductor region 118 is further provided. Therefore, the semiconductor device 101 of the second embodiment also has the corresponding effects of the semiconductor device 100 of the first embodiment.

[0086] [Implementation Method 3]

[0087] Figure 7 This is a cross-sectional view for explaining the semiconductor device 102 according to the third embodiment.

[0088] The semiconductor device 102 of the third embodiment has basically the same structure as the semiconductor device 101 of the second embodiment, but differs from the semiconductor device 101 of the second embodiment in that the n-type semiconductor region 118a is in contact with the substrate (see FIG. Figure 7 That is, in the semiconductor device 102 of the third embodiment, the n-type semiconductor region 118 a is formed in a region in contact with the second electrode 130 at a depth reaching the substrate 111 and in contact with the substrate 111 .

[0089] The n-type semiconductor region 118a and the back gate region 113b can be formed using appropriate methods. In the third embodiment, a semiconductor substrate comprising a laminated substrate 111 and an n-type semiconductor layer is prepared, and a columnar (pillar-shaped when viewed in cross section) back gate region is formed on the n-type semiconductor layer. This separates the n-type semiconductor layer to form the n-type first semiconductor layer 112 and the n-type semiconductor region 118a. Therefore, the impurity concentration of the n-type semiconductor region 118a is the same as that of the first semiconductor layer 112, and the back gate region 113b is formed as a columnar region with a depth reaching the substrate 111 through the insulating film 150.

[0090] As described above, while the semiconductor device 102 of the third embodiment differs from the semiconductor device 101 of the second embodiment in that the n-type semiconductor region contacts the substrate, similarly to the semiconductor device 101 of the second embodiment, since the semiconductor substrate 110 includes a p-type back gate region 113b extending to a depth reaching the substrate 111 at least in the region facing the third electrode 160 via the insulating film 150, the formation of a parasitic transistor, which is a major cause of parasitic current flowing between the second electrode 130 and the substrate 111, is less likely to occur. Consequently, problems such as increased leakage current, reduced withstand voltage, and device damage caused by parasitic current are less likely to occur, allowing the formation of a rectifier element on the semiconductor substrate. This allows the rectifier element to be integrated into the gate driver IC.

[0091] Furthermore, according to the semiconductor device 102 of the third embodiment, since the impurity concentration of the n-type semiconductor region 118a is the same as the impurity concentration of the first semiconductor layer 112, the n-type semiconductor layer can be separated into the n-type first semiconductor layer 112 and the n-type semiconductor region 118a by forming a pillar-shaped back gate region on the n-type semiconductor layer. This eliminates the need for a new process to form the n-type semiconductor region 118a, allowing the semiconductor device to be manufactured using a simple method.

[0092] Furthermore, since the semiconductor device 102 of the third embodiment has the same structure as the semiconductor device 101 of the second embodiment except that the n-type semiconductor region is in contact with the substrate, it also has the corresponding effects of the semiconductor device 101 of the second embodiment.

[0093] While the present invention has been described above based on the above-mentioned embodiment, the present invention is not limited to the above-mentioned embodiment and can be implemented in various forms without departing from the gist of the invention. For example, the following modifications are also possible.

[0094] (1) The number, material, shape, position, size, etc. of the components described in the above embodiments are merely examples and may be modified within a range that does not impair the effects of the present invention.

[0095] (2) In the first embodiment described above, a fourth electrode is provided to connect the substrate 111 to a reference potential, but the present invention is not limited to this. The fourth electrode may be omitted and the potential of the substrate 111 may be used as the reference potential, or the substrate 111 may not be connected to the reference potential. Furthermore, in the second and third embodiments, a fourth electrode is omitted, but the present invention is not limited to this. The fourth electrode may be provided to connect the substrate 111 to a reference potential, or a potential other than the reference potential may be connected.

[0096] (3) In the first embodiment described above, the third electrode is connected to the second electrode, but the present invention is not limited to this. Instead of connecting the third electrode to the second electrode, a voltage may be applied to the third electrode to turn the semiconductor device on and off. Furthermore, in the second and third embodiments, instead of connecting the third electrode to the second electrode, a voltage may be applied to the third electrode to turn the semiconductor device on and off, but the present invention is not limited to this. The third electrode may also be connected to the second electrode.

[0097] (4) In the above embodiments, the back gate region is connected to the substrate 111, but the present invention is not limited thereto. The back gate region may not be connected to the substrate 111. Furthermore, the impurity concentration of the substrate 111 and the impurity concentration of the back gate region may be different.

[0098] (5) In each of the above embodiments, the semiconductor device is used as a rectifier element of the bootstrap circuit, but the present invention is not limited thereto and can be used as a rectifier element other than the rectifier element of the bootstrap circuit.

[0099]

Explanation of symbols

[0100] 10…high-side drive circuit; 20…low-side drive circuit; 22…capacitor; 100, 101, 102…semiconductor device; 110…semiconductor base; 111…substrate; 112…first semiconductor layer; CR1…first contact region; CR2…second contact region; CR3…third contact region; 113, 113a, 113b…back gate region; 118, 118a…n-type semiconductor region; 120…first electrode; 130…second electrode; 140…element separation film; 150, 152…insulating film; 160…third electrode; 170…fourth electrode; C1…first circuit; C2…second circuit.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor substrate having a substrate of a first conductivity type, a first semiconductor layer of a second conductivity type formed on the substrate, and a back gate region of the first conductivity type formed on the substrate and adjacent to the first semiconductor layer; A first electrode is disposed above the semiconductor substrate and in contact with the semiconductor substrate; a second electrode disposed above the semiconductor substrate at a position separated from the first electrode and in contact with the semiconductor substrate; an element separation film formed in a region between the first electrode and the second electrode on the surface of the semiconductor substrate; an insulating film disposed between the second electrode and the element isolation film on the surface of the semiconductor substrate; as well as A third electrode is disposed on the insulating film. The first electrode is arranged above the semiconductor substrate at a position on the side of the element isolation film opposite to the side where the back gate region is formed. The second electrode is arranged at a position opposite to the first electrode across the element separation film. The element isolation film is arranged on the surface of the central region of the first semiconductor layer. The third electrode is arranged on the insulating film at a position in contact with the element isolation film, and is arranged to face a portion of the back gate region and a portion of the first semiconductor layer via the insulating film. The first electrode is electrically connected to a first circuit connected to a first power source, The second electrode is electrically connected to a second circuit connected to a second power source, The back gate region is formed in a region facing the third electrode at a depth that reaches the substrate at least through the insulating film, and the impurity concentration thereof is 1×10 10 cm -3 ~1×10 15 cm -3 Within the range, The semiconductor substrate further comprises: a second conductivity type contact region formed in a region connected to the second electrode and having an impurity concentration higher than that of the first semiconductor layer; and a second conductivity type semiconductor region formed in a region surrounding the contact region and having an impurity concentration lower than that of the contact region. The back gate region is also formed between the second conductive type semiconductor region and the substrate.

2. The semiconductor device according to claim 1, wherein: in, The second power supply voltage, which is the output voltage of the second power supply, is lower than the first power supply voltage, which is the output voltage of the first power supply.

3. The semiconductor device according to claim 1 or 2, wherein: in, The third electrode is electrically connected to the second electrode.

4. The semiconductor device according to claim 1 or 2, wherein: in, A predetermined voltage is applied to the third electrode according to the signal.

5. The semiconductor device according to claim 1 or 2, wherein: in, The substrate is connected to a reference potential.

6. The semiconductor device according to claim 1 or 2, wherein: in, The first electrode is electrically connected to a drive circuit for controlling on / off of a switch element of the first circuit and a capacitor connected to the drive circuit. The second electrode is electrically connected to a driving power source serving as the second power source, and the semiconductor device and the driving circuit are formed on the same semiconductor substrate.

7. The semiconductor device according to claim 1 or 2, wherein: in, The semiconductor substrate further includes a second conductive type contact region, which is formed on a region connected to the second electrode and has a higher impurity concentration than the first semiconductor layer. The back gate region is also formed on a region between the contact region and the substrate.

8. The semiconductor device according to claim 1 or 2, wherein: in, The semiconductor substrate further comprises: a second conductive type contact region formed in a region connected to the second electrode and having an impurity concentration higher than that of the first semiconductor layer; and a second conductive type semiconductor region formed in a region surrounding the contact region and having an impurity concentration lower than that of the contact region. The second conductive type semiconductor region is in contact with the substrate.

9. The semiconductor device according to claim 1, wherein: in, The impurity concentration of the second conductive type semiconductor region is the same as the impurity concentration of the first semiconductor layer.

10. The semiconductor device according to claim 1, wherein: in, The impurity concentration of the second conductive type semiconductor region is lower than the impurity concentration of the first semiconductor layer.

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