Flash memory structure and method of forming the same

Abstract

A flash memory structure and a method for forming the same, the method comprising: two initial control gate structures located on a surface of a floating gate material layer, each initial control gate structure comprising an initial control gate, a sacrificial layer on the initial control gate, and a first sidewall, the initial control gates having a control gate opening therebetween, the sacrificial layers having a sacrificial opening exposing the control gate opening therebetween, the first sidewalls located on sidewalls of the sacrificial opening; forming an initial second sidewall on sidewalls of the initial control gate structures exposed by the control gate opening and the sacrificial opening, and a first dielectric layer on sidewalls of the initial second sidewall; etching the initial second sidewall until a top surface of the initial second sidewall is lower than a top surface of the initial control gate structure to form a second sidewall; after forming the second sidewall, etching the floating gate material layer until a substrate is exposed to form a transition floating gate, the transition floating gate having a floating gate opening therebetween, and forming an erase gate structure in the control gate opening, the sacrificial opening, and the floating gate opening, thereby improving a process window.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a flash memory structure and a forming method thereof. BACKGROUND

[0002] Flash memory is a kind of non-volatile memory, which can keep data for a long time even without power supply, i.e. the data will not be lost after power-off. According to the structure, flash memory can be divided into NOR flash memory and NAND flash memory. Among them, NOR flash memory has the characteristics of direct code execution, strong reliability and fast reading speed, so it becomes the mainstream non-volatile memory in flash memory technology and is widely used in fields such as mobile phones or motherboards which need to record system codes.

[0003] With the continuous development of semiconductor technology, it is inevitable to reduce the size of the storage unit of NOR flash memory. However, the problems such as reliability failure and low programming efficiency caused by size reduction will become more and more prominent.

[0004] Therefore, the performance of the NOR flash memory structure formed by the prior art needs to be further improved. SUMMARY

[0005] The technical problem solved by the present application is to provide a flash memory structure and a forming method thereof to improve the performance of the formed flash memory structure.

[0006] To solve the above technical problems, the technical scheme of the present application provides a flash memory structure, comprising: a substrate; two storage gate structures located on the surface of the substrate and separated from each other, each storage gate structure comprising a floating gate, a control gate structure located on the floating gate, the control gate structure comprising a control gate and a first side wall located on the surface of the control gate; an erase gate structure located between the two storage gate structures; a first side wall located between the side wall of the control gate structure and the erase gate structure, the top surface of the first side wall being lower than the top of the control gate structure.

[0007] Optionally, the top of the erase gate structure between the floating gates has a first size, and the bottom of the erase gate structure between the control gate structures has a second size, the first size being smaller than the second size.

[0008] Optionally, the erase gate structure comprises an erase gate dielectric layer and an erase gate layer located on the erase gate dielectric layer.

[0009] Optionally, the control gate structure further comprises a floating gate oxide layer located between the floating gate and the substrate.

[0010] Optionally, the control gate structure further comprises a control gate dielectric layer between the floating gate and the control gate.

[0011] Accordingly, the technical scheme of the present application further provides a forming method of the flash memory structure, comprising: providing a substrate; forming a floating gate material layer on the surface of the substrate, two initial control gate structures on the surface of the floating gate material layer and separated from each other, each initial control gate structure comprising an initial control gate, a sacrifice layer on the initial control gate and a first sidewall, the initial control gates having a control gate opening therebetween, the sacrifice layers having a sacrifice opening exposing the control gate opening, the first sidewall being on the sidewall of the sacrifice opening; forming an initial second sidewall and a first dielectric layer on the sidewall of the initial control gate structure exposed by the control gate opening and the sacrifice opening, the first dielectric layer and the initial second sidewall being of different materials; etching the initial second sidewall until the top surface of the initial second sidewall is lower than the top surface of the initial control gate structure to form a second sidewall; after forming the second sidewall, etching the floating gate material layer until the substrate is exposed to form a transition floating gate, the transition floating gate having a floating gate opening therebetween; forming an erase gate structure in the control gate opening, the sacrifice opening and the floating gate opening.

[0012] Optionally, the etching process of the initial second sidewall comprises a wet etching process.

[0013] Optionally, the process parameters of the wet etching process comprise: the etching solution comprises a phosphoric acid solution, the etching temperature ranges from 120 to 180 ℃, and the etching solution concentration ranges from 80 to 90%.

[0014] Optionally, after forming the floating gate opening and before forming the erase gate structure, the first dielectric layer is removed.

[0015] Optionally, after forming the erase gate structure, the method further comprises: removing the sacrifice layer; after removing the sacrifice layer, etching the initial control gate and the transition floating gate with the first sidewall as a mask until the surface of the substrate is exposed to form two storage gate structures separated from each other on the substrate, each storage gate structure comprising a floating gate and a control gate structure on the floating gate, the control gate structure comprising a control gate and the first sidewall, the transition floating gate forming the floating gate, and the initial control gate forming the control gate.

[0016] Optionally, the control gate structure further comprises a floating gate oxide layer between the floating gate and the substrate; the forming method of the floating gate oxide layer comprises: forming a floating gate oxide material layer on the surface of the substrate before forming the floating gate material layer; and the floating gate oxide material layer is etched to form the floating gate oxide layer.

[0017] Optionally, the forming method of the initial second sidewall and the first dielectric layer comprises: forming a second sidewall material layer on the surface of the floating gate material layer and the surface of the two initial control gate structures; etching back the second sidewall material layer until the surface of the floating gate material layer is exposed to form the initial second sidewall; after forming the initial second sidewall, forming a first dielectric material layer on the surface of the two initial control gate structures; etching back the first dielectric material layer until the surface of the floating gate material layer is exposed to form the first dielectric layer.

[0018] Optionally, the initial control gate structure sidewall and the initial second sidewall further have a second dielectric layer therebetween, the material of the second dielectric layer is different from the material of the initial second sidewall; the forming method of the second dielectric layer comprises: before forming the second sidewall material layer, forming a second dielectric material layer on the surface of the floating gate material layer and the surface of the two initial control gate structures; the second dielectric material layer is etched to form the second dielectric layer.

[0019] Optionally, the material of the second dielectric layer comprises a dielectric material, and the dielectric material comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

[0020] Optionally, the etching back process of the second sidewall material layer comprises a dry etching process.

[0021] Optionally, the forming method of the two initial control gate structures comprises: forming a control gate material layer on the floating gate material layer; forming a sacrificial material layer on part of the control gate material layer; etching the sacrificial material layer to form the sacrificial layer and the sacrificial opening; forming the first sidewall on the sidewall of the sacrificial opening; after forming the first sidewall, etching the control gate material layer exposed at the bottom of the sacrificial opening to form two initial control gates.

[0022] Optionally, the control gate structure further comprises a control gate dielectric layer between the floating gate and the control gate; the forming method of the control gate dielectric layer comprises: before forming the control gate material layer, forming a control gate dielectric material layer on the floating gate material layer; the control gate dielectric material layer is etched to form the control gate dielectric layer.

[0023] Optionally, the erase gate structure comprises an erase gate layer; the forming method of the erase gate structure comprises: forming an erase gate material layer in the control gate opening, the sacrificial opening and the floating gate opening, and on the surface of the initial control gate structure; planarizing the erase gate material layer until the top surface of the initial control gate structure is exposed to form the erase gate layer with the erase gate material layer.

[0024] Optionally, the erase gate structure further comprises an erase gate dielectric layer, and the erase gate layer is located on a surface of the erase gate dielectric layer.

[0025] Optionally, a depth range of the second sidewall top surface below the initial control gate structure top surface is 500A to 1000A.

[0026] Optionally, a material of the second sidewall comprises a dielectric material, and the dielectric material comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride; a material of the first dielectric layer comprises a dielectric material, and the dielectric material comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

[0027] Compared with the prior art, the technical scheme of the embodiment of the present application has the following beneficial effects:

[0028] In the forming method of the flash memory structure provided by the technical scheme, the initial second sidewall has a first dielectric layer, in the process of etching the initial second sidewall to form a second sidewall, an etching process with a large etching selectivity ratio to the initial second sidewall and the first dielectric layer is selected, and etching process parameters (such as time) are controlled, so that the initial second sidewall top surface is lower than the initial control gate structure top surface, and the etching damage of the initial second sidewall to the initial control gate sidewall is reduced; in the planarization process of forming the erase gate structure, the initial control gate structure top surface is exposed, and since the second sidewall top surface is lower than the initial control gate structure top surface, the second sidewall top surface is not exposed, and thus in the subsequent etching process, the device performance is not affected by etching the second sidewall, and thus the process window and the stability of the device performance are improved.

[0029] Further, after forming the floating gate opening and before forming the erase gate structure, the first dielectric layer is removed, so that the part of the floating gate deep into the erase gate structure in the formed erase gate structure is increased, and the wrapped structure between the floating gate and the erase gate structure is beneficial to the tunneling of the electrons in the floating gate into the erase gate, and the erasing efficiency of the formed flash memory structure is improved. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figures 1 to 4 is a structural schematic diagram of a flash memory structure forming process;

[0031] Figures 5 to 15 is a structural schematic diagram of each step of the forming method of the flash memory structure in the embodiment of the present application. DETAILED DESCRIPTION

[0032] It should be noted that the "surface", "upper" in the specification are used to describe the relative position relationship of space, and are not limited to whether they are in direct contact.

[0033] As described in the background, the performance of the flash memory structure formed by the prior art or the non-type flash memory structure needs to be further improved. The present application will be described and analyzed in combination with a flash memory structure.

[0034] Figures 1 to 4 A structural schematic diagram of a flash memory structure forming process.

[0035] Referring to Figure 1 , a substrate 100 is provided; a floating gate oxide material layer 101 is formed on the surface of the substrate 100, a floating gate material layer 102 is formed on the surface of the floating gate oxide material layer 101, two initial control gate structures are formed on the surface of the floating gate material layer 102 and are separated from each other, and an initial opening 107 is formed between the two initial control gate structures, each initial control gate structure includes an initial gate dielectric layer 103, an initial control gate 104 on the initial gate dielectric layer 103, a sacrificial layer 105 on the initial control gate 104, and a first sidewall 106 on the sidewall of the sacrificial layer 105, and the initial opening 107 exposes the first sidewall 106; a protective material layer 108 is formed on the surface of the two initial control gate structures, and a second sidewall material layer 109 is formed on the surface of the protective material layer 108.

[0036] Referring to Figure 2 , the protective material layer 108 and the second sidewall material layer 109 are etched back until the surface of the floating gate material layer 102 is exposed, the protective material layer 108 forms a protective layer 110, and the second sidewall material layer 109 forms a second sidewall 111; after the second sidewall 111 is formed, the floating gate material layer 102 and the floating gate oxide material layer 101 are etched until the surface of the substrate 100 is exposed, the floating gate material layer 102 forms a transition floating gate layer 112, the floating gate oxide material layer 101 forms a transition floating gate oxide layer 113, and the initial opening 107 forms an opening 114.

[0037] Referring to Figure 3 , an erase gate dielectric material layer (not shown in the figure) and an erase gate material layer (not shown in the figure) on the erase gate dielectric material layer are formed in the opening 114 and on the surface of the initial control gate structure; the erase gate material layer and the erase gate dielectric material layer are planarized until the top surface of the initial control gate structure is exposed, and the erase gate material layer and the erase gate dielectric material layer form an erase gate 115.

[0038] Referring to Figure 4After forming the erase gate 115, the sacrificial layer 105 is removed. After removing the sacrificial layer 105, the initial control gate 104, the initial gate dielectric layer 103, the transition floating gate layer 112, and the transition floating gate oxide layer 113 are etched using the first sidewall 106 as a mask. The initial control gate 104 forms the control gate 116, the initial gate dielectric layer 103 forms the gate dielectric layer 117, the transition floating gate layer 112 forms the floating gate layer 118, and the transition floating gate oxide layer 113 forms the floating gate oxide layer 119.

[0039] The above method is used to form a NOR flash memory structure. The second sidewall 111 is used to isolate the erase gate 115 and the control gate 116. The sacrificial layer 105 and the second sidewall 111 are both made of silicon nitride. The second sidewall 111 is obtained by etching back the second sidewall material layer 109, and the etching back process is a dry etching process.

[0040] There are two scenarios in the formation process of the second sidewall 111. In one scenario, the amount of etchback of the second sidewall material layer 109 is less: after planarizing the erased gate material layer, the top surface of the second sidewall 111 is exposed (e.g., Figure 3 As shown), the process of removing the sacrificial layer 105 involves etching with a phosphoric acid solution. Since the top surface of the second sidewall 111 is exposed and its material is the same as the sacrificial layer 105, it is easy for the second sidewall 111 to be simultaneously etched to form a groove A (as shown). Figure 4 As shown in the diagram, this can even cause the etching solution to enter the flash memory structure along the groove A, affecting device performance and even causing device failure. In another case, the amount of etching back of the second sidewall material layer 109 is too large: because the initial control gate 104 has a corner B, the second sidewall material layer 109 on the surface of the corner B is more likely to bulge out compared to other positions. In the case of over-etching, the formed second sidewall 111 is prone to break off from this point, resulting in leakage current and even causing the formed flash memory device to fail. In summary, the formation process window of the second sidewall 111 is small, which is not conducive to the stability of device performance.

[0041] In order to solve the above problems, the application provides a flash memory structure and a forming method thereof, wherein the initial second sidewall has a first dielectric layer, in the process of etching the initial second sidewall to form a second sidewall, an etching process with a large etching selectivity ratio for the initial second sidewall and the first dielectric layer is selected, and the etching process parameters (such as time) are controlled, so that the top surface of the initial second sidewall is lower than the top of the initial control gate structure, and the etching damage of the initial second sidewall to the initial control gate sidewall is reduced; in the planarization process of forming an erase gate structure, the top surface of the initial control gate structure is exposed, and since the top surface of the second sidewall is lower than the top surface of the initial control gate structure, the top surface of the second sidewall is not exposed, so that in the subsequent etching process, the device performance is not affected by etching the second sidewall, and the process window and the stability of the device performance are improved.

[0042] In order to make the above-mentioned purposes, features and benefits of the application more obvious and easy to understand, the specific embodiments of the application will be described in detail below with reference to the drawings.

[0043] Figures 5 to 15 is a structural schematic diagram of each step of the forming method of the flash memory structure in the embodiment of the application.

[0044] Please refer to Figure 5 , a substrate 200 is provided.

[0045] In the embodiment, the material of the substrate 200 includes silicon. In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of III-V group elements, silicon-on-insulator (SOI) or germanium-on-insulator (GOI). The multi-element semiconductor material composed of III-V group elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0046] Subsequently, a floating gate material layer is formed on the surface of the substrate 200, and two initial control gate structures are formed on the surface of the floating gate material layer and are separated from each other, each initial control gate structure includes an initial control gate, a sacrifice layer on the initial control gate and a first sidewall, the initial control gates have a control gate opening therebetween, the sacrifice layers have a sacrifice opening exposing the control gate opening therebetween, and the first sidewall is located on the sidewall of the sacrifice opening.

[0047] The forming method of the floating gate material layer and the two initial control gate structures is described in detail in Figures 6 to 7 .

[0048] Please refer to Figure 6forming a floating gate material layer 202 on the substrate 200; forming a control gate material layer 204 on the floating gate material layer 202; forming a sacrificial material layer (not shown) on part of the control gate material layer 204; etching the sacrificial material layer to form the sacrificial layer 205 and the sacrificial opening 207; forming the first sidewall 206 on the sidewall of the sacrificial opening 207.

[0049] In this embodiment, a floating gate oxide material layer 201 is formed on the substrate 200 before the floating gate material layer 202 is formed. The floating gate oxide material layer 201 is used to form a floating gate oxide layer.

[0050] In this embodiment, a control gate dielectric material layer 203 is formed on the floating gate material layer 202 before the control gate material layer 204 is formed. The control gate dielectric material layer 203 is used to form a control gate dielectric layer.

[0051] In this embodiment, the control gate dielectric material layer 203 includes a first dielectric material layer (not shown), a second dielectric material layer (not shown) on the first dielectric material layer, and a third dielectric material layer (not shown) on the second dielectric material layer. Specifically, the material of the first dielectric material layer is silicon oxide; the material of the second dielectric material layer is silicon nitride; and the material of the third dielectric material layer is silicon oxide.

[0052] Please refer to Figure 7 After the first sidewall 206 is formed, the control gate material layer 204 exposed by the bottom of the sacrificial opening 207 is etched to form two initial control gates 208.

[0053] Each initial control gate structure includes an initial control gate 208, a sacrificial layer 205 on the initial control gate 208, and a first sidewall 206, and the initial control gates 208 have a control gate opening 210 therebetween.

[0054] In this embodiment, the control gate opening 210 is also located in the control gate dielectric material layer 203.

[0055] Subsequently, an initial second sidewall and a first dielectric layer on the sidewall of the initial second sidewall are formed on the sidewall of the initial control gate structure exposed by the control gate opening 210 and the sacrificial opening 207, and the material of the first dielectric layer is different from that of the initial second sidewall. In this embodiment, the formation method of the initial second sidewall and the first dielectric layer is described in Figures 8 to 10 .

[0056] Please refer to Figure 8 A second sidewall material layer 211 is formed on the surface of the floating gate material layer 202 and the surface of the two initial control gate structures.

[0057] The second sidewall material layer 211 is used to form an initial second sidewall, and further form a second sidewall.

[0058] The material of the second sidewall material layer 211 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride; the material of the first dielectric layer includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the second sidewall material layer 211 is silicon nitride.

[0059] In this embodiment, before forming the second sidewall material layer 211, a second dielectric material layer 212 is formed on the surface of the floating gate material layer 202 and the surfaces of the two initial control gate structures.

[0060] The material of the second dielectric material layer 212 is different from that of the second sidewall material layer 211. The second dielectric material layer 212 is used to form a second dielectric layer. When etching the second sidewall material layer 211, the second dielectric material layer plays a role of protecting the floating gate material layer 202 and the initial control gate 208.

[0061] The material of the second dielectric material layer 212 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the second dielectric material layer 212 is silicon oxide.

[0062] Please refer to Figure 9 , the second sidewall material layer 211 is etched back until the surface of the floating gate material layer 202 is exposed, forming the initial second sidewall 213.

[0063] The process of etching back the second sidewall material layer 211 includes a dry etching process. Controlling the etching back process time of the second sidewall material layer 211 can prevent over-etching, reduce the etching damage to the formed initial second sidewall 213, and thus improve the isolation ability of the subsequently formed second sidewall 213 between the control gate and the erase gate structure.

[0064] In this embodiment, the second dielectric material layer 212 is etched to form the second dielectric layer 214.

[0065] Specifically, the initial control gate structure sidewall and the initial second sidewall 213 further have a second dielectric layer 214 therebetween, and the material of the second dielectric layer 214 is different from that of the initial second sidewall 213.

[0066] The material of the second dielectric layer 214 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the second dielectric layer 214 is silicon oxide.

[0067] Please refer to Figure 10 After the initial second sidewall 213 is formed, a first dielectric material layer (not shown in the figure) is formed on the surfaces of the two initial control gate structures; the first dielectric material layer is etched back until the surface of the floating gate material layer 202 is exposed, forming the first dielectric layer 215.

[0068] The material of the first dielectric layer 215 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the first dielectric layer 215 is silicon oxide.

[0069] The first dielectric layer 215 is used as a mask to etch the floating gate material layer 202, forming a floating gate opening in the floating gate material layer 202.

[0070] Please refer to Figure 11 The initial second sidewall 213 is etched until the top surface of the initial second sidewall 213 is lower than the top surface of the initial control gate structure, to form a second sidewall 216.

[0071] The sidewall of the initial second sidewall 213 has a first dielectric layer 215. In the process of etching the initial second sidewall 213 to form the second sidewall 216, an etching process with a large etching selectivity ratio for the initial second sidewall 213 and the first dielectric layer 215 is selected, and the etching process parameters (such as time) are controlled, so that the top surface of the initial second sidewall 213 is lower than the top surface of the initial control gate structure, while reducing the etching damage of the initial second sidewall 213 to the sidewall of the initial control gate.

[0072] The process of etching the initial second sidewall 213 includes a wet etching process.

[0073] The process parameters of the wet etching process include: the etching solution includes a phosphoric acid solution, the etching temperature ranges from 120°C to 180°C, and the etching solution concentration ranges from 80% to 90%.

[0074] The depth of the top surface of the second sidewall 216 being lower than the top surface of the initial control gate structure ranges from 500A to 1000A.

[0075] The material of the second sidewall 216 includes a dielectric material including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride; the material of the first dielectric layer includes a dielectric material including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the second sidewall 216 is silicon nitride.

[0076] After the second sidewall 216 is formed, the floating gate material layer 202 is etched until the substrate 200 is exposed to form a transition floating gate 217, and the transition floating gate 217 has a floating gate opening 218 therebetween. Figure 12

[0077] In this embodiment, the floating gate opening 218 is also located in the floating gate oxide material layer 201.

[0078] Subsequently, an erase gate structure is formed in the control gate opening 210, the sacrifice opening 207, and the floating gate opening 218.

[0079] In this embodiment, after the floating gate opening 218 is formed and before the erase gate structure is formed, please refer to Figure 13 .

[0080] After the floating gate opening 218 is formed and before the erase gate structure is formed, the first dielectric layer 215 is removed. Figure 13 The process of removing the first dielectric layer 215 includes a wet etching process.

[0081] After the first dielectric layer 215 is removed, the portion of the floating gate that is deep into the erase gate structure is increased in the subsequently formed erase gate structure, and the wrapping structure between the floating gate and the erase gate structure is beneficial to the tunneling of electrons in the floating gate into the erase gate, thereby improving the erase efficiency of the formed flash memory structure.

[0082] After the floating gate opening 218 is formed and before the erase gate structure is formed, the first dielectric layer 215 is removed.

[0083] Figure 14 The erase gate structure includes an erase gate layer 220.

[0084] In this embodiment, the erase gate structure includes an erase gate layer 220.

[0085] ​​In this embodiment, the top of the erase gate structure between the transition floating gates 217 has a first size, and the bottom of the erase gate structure between the control gate structures has a second size, the first size being smaller than the second size. Specifically, the number of parts of the floating gates formed later into the erase gate structure can be increased, and the wrap structure between the floating gates and the erase gate structure is conducive to the tunneling of electrons in the floating gates into the erase gate, thereby improving the erase efficiency of the formed flash memory structure.

[0086] The method for forming the erase gate structure includes: forming an erase gate material layer (not shown in the figure) in the control gate opening 210, the sacrifice opening 207, and the floating gate opening 218, and on the surface of the initial control gate structure; planarizing the erase gate material layer until the top surface of the initial control gate structure is exposed, so that the erase gate layer 220 is formed from the erase gate material layer.

[0087] During the planarization process of forming the erase gate structure, the top surface of the initial control gate structure is exposed, and the top surface of the second sidewall 216 is not exposed because the top surface of the second sidewall 216 is lower than the top surface of the initial control gate structure. Therefore, in the subsequent etching process, the device performance will not be affected by etching the second sidewall 216, thereby improving the process window and the stability of the device performance.

[0088] The erase gate structure further includes an erase gate dielectric layer 219, and the erase gate layer 220 is located on the surface of the erase gate dielectric layer 219.

[0089] Please refer to Figure 15 After the erase gate structure is formed, the sacrifice layer 205 is removed, and then the initial control gate 208 and the transition floating gate 217 are etched using the first sidewall 206 as a mask until the surface of the substrate 200 is exposed, thereby forming two separate storage gate structures on the substrate 200. Each storage gate structure includes a floating gate 221 and a control gate structure located on the floating gate 221, the control gate structure including a control gate 222 and the first sidewall 206. The floating gate 221 is formed from the transition floating gate 217, and the control gate 222 is formed from the initial control gate 208.

[0090] In the etching process for removing the sacrifice layer 205, the top surface of the second sidewall 216 is not exposed because it is lower than the top surface of the initial control gate structure. Therefore, the device performance will not be affected by etching the second sidewall 216, thereby improving the process window and the stability of the device performance.

[0091] The control gate structure further comprises a floating gate oxide layer 223 between the floating gate 221 and the substrate 200. Specifically, the floating gate oxide material layer 201 is etched to form the floating gate oxide layer 223.

[0092] In this embodiment, the control gate structure further comprises a control gate dielectric layer 224 between the floating gate 221 and the control gate 222. Specifically, the control gate dielectric material layer 203 is etched to form the transition control gate dielectric layer 224.

[0093] Accordingly, the embodiment of the present application further provides a flash memory structure formed by the above method, please continue to refer to Figure 15 , comprising: a substrate 200; two mutually discrete storage gate structures on the surface of the substrate 200, each storage gate structure comprising a floating gate 221, a control gate structure on the floating gate 221, the control gate structure comprising a control gate 222 and a first sidewall 206 on the surface of the control gate 222; an erase gate structure between the two storage gate structures; a first sidewall 216 between the sidewall of the control gate structure and the erase gate structure, the top surface of the first sidewall 216 being lower than the top of the control gate structure.

[0094] In this embodiment, the erase gate structure comprises an erase gate dielectric layer 219 and an erase gate layer 220 on the erase gate dielectric layer 219.

[0095] In this embodiment, the top of the erase gate structure between the floating gates 221 has a first size, and the bottom of the erase gate structure between the control gate structures has a second size, the first size being smaller than the second size.

[0096] In this embodiment, the control gate structure further comprises a floating gate oxide layer 223 between the floating gate 221 and the substrate 200.

[0097] In this embodiment, the control gate structure further comprises a control gate dielectric layer 224 between the floating gate 221 and the control gate 222.

[0098] Although the present application is disclosed as above, the present application is not limited to this. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, therefore the protection scope of the present application should be limited by the scope defined by the claims.

Claims

1. A method for forming a flash memory structure, characterized in that, include: Provide substrate; A floating gate material layer is formed on the surface of the substrate, and two initial control gate structures are separated from each other on the surface of the floating gate material layer. Each initial control gate structure includes an initial control gate, a sacrificial layer on the initial control gate, and a first sidewall. The initial control gates have a control gate opening between them, and the sacrificial layers have a sacrificial opening that exposes the control gate opening between them. The first sidewall is located on the sidewall of the sacrificial opening. An initial second sidewall and a first dielectric layer located on the sidewall of the initial control gate structure exposed by the control gate opening and the sacrificial opening are formed, wherein the first dielectric layer and the initial second sidewall are made of different materials; Using the first dielectric layer as a protection, the initial second sidewall is etched until the top surface of the initial second sidewall is lower than the top surface of the initial control gate structure to form the second sidewall; After the second sidewall is formed, the floating gate material layer is etched until the substrate is exposed to form a transition floating gate with floating gate openings between the transition floating gates; An erasure gate structure is formed within the control gate opening, the sacrificial opening, and the floating gate opening.

2. The method for forming a flash memory structure as described in claim 1, characterized in that, The etching process for the initial second sidewall includes a wet etching process.

3. The method for forming a flash memory structure as described in claim 2, characterized in that, The process parameters of the wet etching process include: the etching solution includes a phosphoric acid solution, the etching temperature range is 120 ℃ to 180 ℃, and the etching solution concentration range is 80% to 90%.

4. The method for forming a flash memory structure as described in claim 1, characterized in that, After the floating gate opening is formed, and before the erase gate structure is formed, the first dielectric layer is also removed.

5. The method for forming a flash memory structure as described in claim 1, characterized in that, After forming the erase gate structure, the method further includes: removing the sacrificial layer; after removing the sacrificial layer, using the first sidewall as a mask, etching the initial control gate and the transition floating gate until the substrate surface is exposed, forming two independent memory gate structures on the substrate. Each memory gate structure includes a floating gate and a control gate structure located on the floating gate. The control gate structure includes a control gate and the first sidewall. The floating gate is formed using the transition floating gate, and the control gate is formed using the initial control gate.

6. The method for forming a flash memory structure as described in claim 5, characterized in that, The control gate structure further includes a floating gate oxide layer located between the floating gate and the substrate; the method for forming the floating gate oxide layer includes: forming a floating gate oxide material layer on the surface of the substrate before forming the floating gate material layer; and etching the floating gate oxide material layer to form the floating gate oxide layer.

7. The method for forming a flash memory structure as described in claim 1, characterized in that, The method for forming the initial second sidewall and the first dielectric layer includes: forming a second sidewall material layer on the surface of the floating gate material layer and the surfaces of the two initial control gate structures; etching back the second sidewall material layer until the surface of the floating gate material layer is exposed to form the initial second sidewall; after forming the initial second sidewall, forming a first dielectric material layer on the surfaces of the two initial control gate structures; etching back the first dielectric material layer until the surface of the floating gate material layer is exposed to form the first dielectric layer.

8. The method for forming a flash memory structure as described in claim 7, characterized in that, A second dielectric layer is also provided between the initial control grid structure sidewall and the initial second sidewall, and the material of the second dielectric layer is different from the material of the initial second sidewall. The method for forming the second dielectric layer includes: forming a second dielectric material layer on the surface of the floating grid material layer and on the surfaces of the two initial control grid structures before forming the second sidewall material layer; The second dielectric material layer is etched to form the second dielectric layer.

9. The method for forming a flash memory structure as described in claim 8, characterized in that, The material of the second dielectric layer includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

10. The method for forming a flash memory structure as described in claim 7, characterized in that, The process of etching back the second sidewall material layer includes a dry etching process.

11. The method for forming a flash memory structure as described in claim 1, characterized in that, The method for forming the two initial control gate structures includes: forming a control gate material layer on the floating gate material layer; forming a sacrificial material layer on a portion of the control gate material layer; etching the sacrificial material layer to form the sacrificial layer and the sacrificial opening; forming a first sidewall on the sidewall of the sacrificial opening; and after forming the first sidewall, etching the control gate material layer exposed at the bottom of the sacrificial opening to form two initial control gates.

12. The method for forming a flash memory structure as described in claim 11, characterized in that, The control gate structure further includes a control gate dielectric layer located between the floating gate and the control gate; the method for forming the control gate dielectric layer includes: forming a control gate dielectric material layer on the floating gate material layer before forming the control gate material layer; and etching the control gate dielectric material layer to form the control gate dielectric layer.

13. The method for forming a flash memory structure as described in claim 1, characterized in that, The erase gate structure includes an erase gate layer; The method for forming the erase gate structure includes: forming an erase gate material layer in the control gate opening, the sacrificial opening, and the floating gate opening, as well as on the surface of the initial control gate structure; The erase gate material layer is planarized until the top surface of the initial control gate structure is exposed, thereby forming the erase gate layer with the erase gate material layer.

14. The method for forming a flash memory structure as described in claim 13, characterized in that, The erase gate structure further includes an erase gate dielectric layer, which is located on the surface of the erase gate dielectric layer.

15. The method for forming a flash memory structure as described in claim 1, characterized in that, The depth of the top surface of the second sidewall below the top surface of the initial control grid structure ranges from 500 Å to 1000 Å.

16. The method for forming a flash memory structure as described in claim 1, characterized in that, The material of the second sidewall includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. The material of the first dielectric layer includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

17. A flash memory structure, characterized in that, Formed using the forming method according to any one of claims 1 to 16, comprising: Substrate; Two memory gate structures are located on the surface of the substrate and are mutually independent. Each memory gate structure includes a floating gate and a control gate structure located on the floating gate. The control gate structure includes a control gate and a first sidewall located on the surface of the control gate. The erase gate structure is located between the two storage gate structures; A first sidewall is located between the control gate structure sidewall and the erase gate structure, and the top surface of the first sidewall is lower than the top of the control gate structure.

18. The flash memory structure as described in claim 17, characterized in that, The top of the erase gate structure located between the floating gates has a first dimension, and the bottom of the erase gate structure located between the control gate structures has a second dimension, wherein the first dimension is smaller than the second dimension.

19. The flash memory structure as described in claim 17, characterized in that, The erase gate structure includes an erase gate dielectric layer and an erase gate layer located on the erase gate dielectric layer.

20. The flash memory structure as described in claim 17, characterized in that, The control gate structure also includes a floating gate oxide layer located between the floating gate and the substrate.

21. The flash memory structure as described in claim 17, characterized in that, The control gate structure also includes a control gate dielectric layer located between the floating gate and the control gate.

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