An insulated bipolar transistor capable of adjusting a turn-on voltage value and a manufacturing method thereof

Abstract

The application relates to the technical field of semiconductors, in particular to an insulated bipolar transistor capable of adjusting a conduction voltage value and a preparation method thereof. The application discloses an insulated bipolar transistor capable of adjusting a conduction voltage, characterized in that the transistor comprises, from bottom to top, a collector layer, a P+ type silicon substrate layer, an N+ type buffer layer epitaxial silicon layer, an N-type first drift layer epitaxial silicon layer, an N-type field stop layer, a P-type base layer, a groove extending through the N-type field stop layer and the P-type base layer and reaching the N-type first drift layer epitaxial silicon layer, an N+ emitter region and a P+ emitter region located above the P-type base layer on both sides of the groove, a first insulating isolation layer located above the groove, and an emitter layer located above the N+ emitter region and the P+ emitter region on both sides of the groove, respectively. The bottom of the groove is a second insulating isolation layer, the inside of the groove is a polysilicon gate electrode, and the sidewall of the groove is a gate insulating oxide layer. The breakdown voltage of the transistor in the technical solution is greater than or equal to 1300 V, the gate voltage is less than 2 V, the forward conduction voltage is less than 1.2 V@100 A / cm 2 , and the short-circuit time is less than 3 us.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to an insulated bipolar transistor with adjustable on-state voltage and a method for fabricating the same. Background Technology

[0002] IGBT is short for Insulated Gate Bipolar Transistor, a composite, fully controllable, voltage-driven power semiconductor device composed of a BJT (Bipolar Junction Transistor) and a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). It combines the advantages of both MOSFETs (high input impedance) and GTRs (low on-state voltage drop). GTRs have a low saturation voltage drop and high current density, but require a large drive current; MOSFETs have very low drive power and fast switching speed, but a large on-state voltage drop and low current density. IGBTs combine the advantages of both devices, offering low drive power and a low saturation voltage drop. They are ideally suited for applications in DC power conversion systems of 600V and above, such as AC motors, frequency converters, switching power supplies, lighting circuits, and traction drives. IGBT modules are characterized by energy saving, convenient installation and maintenance, and stable heat dissipation. Currently, most products sold on the market are modular IGBTs; the term "IGBT" generally refers to IGBT modules. With the advancement of energy conservation and environmental protection concepts, these products will become increasingly common in the market.

[0003] Since the invention of the IGBT, researchers have been dedicated to improving its performance. Over decades of development, various semiconductor device structures have been proposed, leading to a steady improvement in device performance. Examples include the IEGT (Enhancement Injection Insulated Gate Bipolar Transistor), which reduces the on-state voltage drop by increasing the conductivity of the N-drift region; the CSTBT (Carrier Storage Trench Gate Bipolar Transistor), which reduces the on-state voltage by increasing the conductivity of the N-drift region; a CSTBT device with a deformable trench gate dielectric disclosed in patent CN 102779842A, which significantly improves the breakdown voltage; and a trench bipolar transistor with carrier storage disclosed in patent CN 102779847A, which reduces the on-state voltage drop, increases current, and reduces turn-on time and turn-off characteristics by increasing the electron concentration in the carrier storage layer and drift region. The use of trench gate electrodes leads to a large emitter-collector capacitance. However, the switching process of IGBT devices is a process of charging and discharging the emitter capacitance. The larger the emitter capacitance, the longer the charging and discharging time. A large emitter capacitance reduces the switching speed of the device, increases the switching loss of the device, and affects the trade-off characteristics between the forward voltage drop and the switching loss of the device.

[0004] There is an urgent need for a transistor that has high breakdown voltage, low on-voltage, and low turn-off time. Summary of the Invention

[0005] To address the aforementioned problems, this invention provides an insulated bipolar transistor capable of adjusting the on-state voltage. The transistor comprises, from bottom to top, a collector layer, a P+ type silicon substrate layer, an N+ type buffer epitaxial silicon layer, an N- type first drift epitaxial silicon layer, an N- type field cutoff layer, a P-type base layer, a trench penetrating the N-type field cutoff layer and the P-type base layer and extending to the N-type first drift epitaxial silicon layer, an N+ emitter region and a P+ emitter region located above the P-type base layer on both sides of the trench, a first insulating isolation layer located above the trench, and emitter layers located above the N+ emitter regions and P+ emitter regions on both sides of the trench, respectively. The bottom of the trench is a second insulating isolation layer, the interior of the trench is a polycrystalline silicon gate electrode, and the sidewalls of the trench are gate insulating oxide layers.

[0006] Preferably, the second insulating layer includes an insulating oxide layer and an insulating nitride layer located above the insulating oxide layer.

[0007] Preferably, the thickness of the insulating oxide layer is 300-1500 Å.

[0008] Preferably, the thickness of the insulating nitrided layer is 500-1500 Å.

[0009] Preferably, the concentration of the N+ type buffer layer epitaxial silicon layer is 10. 16 -10 17 cm -3 The thickness is 2-5um.

[0010] Preferably, the concentration of the N-type first drift layer epitaxial silicon layer is 3e 13 -3e 14 cm -3 The thickness is 100-130um.

[0011] Preferably, the resistivity of the P+ type silicon substrate is 0.01-0.02 Ω·m.

[0012] Preferably, the phosphorus doping concentration in the N+ emitter region is 1e. 15 -5e 15 cm -2 The energy is 60-100 keV.

[0013] Preferably, the boron doping concentration in the P+ emitter region is 1e. 14 -1e 15 cm -2 The energy is 60-100 keV.

[0014] A second aspect of the present invention provides a method for fabricating the aforementioned insulated bipolar transistor with adjustable on-state voltage, comprising at least:

[0015] (1) Prepare a P+ type silicon substrate, form an N+ type buffer layer epitaxial silicon layer on the P+ type silicon substrate, form an N- type first drift layer epitaxial silicon layer on the N+ type buffer layer epitaxial silicon layer, and form an N- type diffusion layer on the N- type first drift layer epitaxial silicon layer.

[0016] (2) An ion-implanted photomask is placed on the N-type diffusion layer, and boron atoms are implanted. The amount of boron atoms implanted is 3e. 13 -9e 13 cm- 2 The energy is 60-120 keV, the annealing temperature is 1100-1200℃, and the annealing time is 5-20 min, so as to form an N-type field stop layer and a P-type base layer.

[0017] (3) A trench is formed by etching, which penetrates the P-type base layer, the N-type field stop layer and extends to the N-type first drift layer epitaxial silicon layer.

[0018] (4) A second insulating isolation layer is formed at the bottom of the trench, the second insulating isolation layer including an insulating oxide layer and an insulating nitride layer located on the insulating oxide layer;

[0019] (5) Lateral ion implantation is performed on the device channel on the trench sidewall, and phosphorus atoms are implanted. The amount of phosphorus atoms implanted is 1e. 12 -6e 12 cm -2 The energy is 40-150 keV. When performing lateral ion implantation, the angle between the implantation and the trench sidewall is 30-45°. During lateral ion implantation, the implantation can be performed multiple times depending on the specific structure of the trench. Afterwards, the etched photomask layer of the trench is removed.

[0020] (6) A gate insulating oxide layer is provided on the sidewall of the trench, and then a doped polycrystalline silicon gate electrode is deposited.

[0021] (7) Phosphorus atoms are implanted into the middle of the P-type base layer to form an N+ emitter polar region, and boron atoms are implanted on both sides of the N+ emitter polar region to form a P+ emitter polar region. The amount of phosphorus atoms implanted is 1e. 15 -5e 15 cm -2 The energy is 60-100 keV, and the amount of boron atoms implanted is 1e. 14 -1e 15 cm -2 The energy is 60-100 keV;

[0022] (8) A first insulating layer is provided above the trench, the first insulating layer extends to both sides of the trench, the material of the first insulating layer is silicon dioxide, and it extends into the N+ emitter regions on both sides of the trench respectively.

[0023] (9) Finally, an emitter layer is covered on the P+ emitter region and the N+ emitter region, and a collector layer is covered on the lower part of the P-type silicon substrate to obtain the desired result.

[0024] Beneficial Effects: In this technical solution, the inventors perform lateral ion implantation within the communication layer. The conduction voltage can be adjusted based on the ion implantation concentration. While maintaining the original doping concentration and breakdown voltage of the transistor, the inventors reduced the conduction voltage, increased the current and turn-off speed, and maintained high latch-up immunity. Furthermore, by setting a second insulating isolation layer at the bottom of the trench, including an insulating oxide layer and an insulating nitride layer, recoil phosphorus atoms can be effectively blocked, thereby further adjusting the gate critical voltage. The transistor in this technical solution has a breakdown voltage ≥1300V, a gate voltage <2V, and a forward conduction voltage <1.2V@100A / cm. 2 Short circuit time < 3µs. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a structural diagram of the transistor in step (1) of the preparation method in Example 1.

[0027] Figure 2 This is a structural diagram of the transistor in step (2) of the preparation method in Example 1.

[0028] Figure 3 This is a structural diagram of the transistor in step (4) of the preparation method in Example 1.

[0029] Figure 4 This is a structural diagram of the transistor in step (6) of the preparation method in Example 1.

[0030] Figure 5 This is a complete structural diagram of the transistor in Example 1.

[0031] Figure 6 This is a test graph of the forward conduction voltage performance of the transistor in Example 1, where the solid line represents the test curve of the technical solution in the example, and the dashed line represents the test curve of the transistor without the second insulating layer.

[0032] Figure 7The diagram shows the gate voltage performance test of the transistor in Example 1, where the solid line represents the test curve of the technical solution in the example, and the dashed line represents the test curve of the transistor without a second insulating layer.

[0033] Figure 8 The diagram shows the breakdown voltage performance test of the transistor in Example 1, where the solid line represents the test curve of the technical solution in the example, and the dashed line represents the test curve of the transistor without a second insulating layer.

[0034] Figure 9 The voltage and current performance test graphs for the anti-lock-in capability of the transistor in Example 1 are shown. The solid lines represent the test curves of the technical solutions in the example, and the dashed lines represent the test curves of transistors without a second insulating layer.

[0035] Among them, 1-N-type diffusion layer, 2-N-type first drift layer epitaxial silicon layer, 3-N+ type buffer layer epitaxial silicon layer, 4-P+ type silicon substrate layer, 5-P type base layer, 6-N-type field stop layer, 7-trench etched photomask layer, 8-insulating oxide layer, 9-insulating nitride layer, 10-P+ emitter region, 11-N+ emitter region, 12-emitter layer, 13-first insulating isolation layer, 14-collector layer, 15-trench, 16-polycrystalline silicon gate electrode. Detailed Implementation

[0036] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use. They are only used for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances. The following are only some embodiments listed to facilitate understanding of the technical solutions of this invention.

[0037] To address the aforementioned problems, this invention provides an insulated bipolar transistor capable of adjusting the on-state voltage. The transistor comprises, from bottom to top, a collector layer, a P+ type silicon substrate layer, an N+ type buffer epitaxial silicon layer, an N- type first drift epitaxial silicon layer, an N- type field cutoff layer, a P-type base layer, a trench penetrating the N-type field cutoff layer and the P-type base layer and extending to the N-type first drift epitaxial silicon layer, an N+ emitter region and a P+ emitter region located above the P-type base layer on both sides of the trench, a first insulating isolation layer located above the trench, and emitter layers located above the N+ emitter regions and P+ emitter regions on both sides of the trench, respectively. The bottom of the trench is a second insulating isolation layer, the interior of the trench is a polycrystalline silicon gate electrode, and the sidewalls of the trench are gate insulating oxide layers.

[0038] As a preferred technical solution, the second insulating isolation layer includes an insulating oxide layer and an insulating nitrided layer located above the insulating oxide layer.

[0039] As a preferred technical solution, the thickness of the insulating oxide layer is 300-1500 Å.

[0040] As a preferred technical solution, the thickness of the insulating nitrided layer is 500-1500 Å.

[0041] The inventors discovered that when using lateral ion implantation, recoil atoms accumulate at the bottom of the trench, forming a buildup layer that affects the concentration balance of the transistor device and can even impact its on-state voltage, causing it to increase further. The inventors found that adding an insulating oxide layer can block the accumulation of recoil atoms. However, when the insulating oxide layer is thin, the blocking effect is not significant; when the insulating oxide layer is thick, the blocking effect is significant, but it affects the transistor's breakdown voltage and short-circuit time. The inventors unexpectedly discovered that when an insulating nitride layer is placed above the insulating oxide layer, especially when the thickness of the insulating oxide layer is 300-1500 Å and the thickness of the insulating nitride layer is 500-1500 Å, it not only effectively blocks recoil atoms but also does not affect the transistor's breakdown voltage and short-circuit time.

[0042] As a preferred technical solution, the concentration of the N+ type buffer epitaxial silicon layer is 10. 16 -10 17 cm -3 The thickness is 2-5um.

[0043] As a preferred technical solution, the concentration of the N-type first drift layer epitaxial silicon layer is 3e 13 -3e 14 cm -3 The thickness is 100-130um.

[0044] As a preferred technical solution, the resistivity of the P+ type silicon substrate is 0.01-0.02 Ω·m.

[0045] As a preferred technical solution, the phosphorus atom doping concentration in the N+ emitter region is 1e. 15 -5e 15 cm -2 The energy is 60-100 keV.

[0046] As a preferred technical solution, the boron doping concentration in the P+ emitter region is 1e. 14 -1e 15 cm -2 The energy is 60-100 keV.

[0047] A second aspect of the present invention provides a method for fabricating the aforementioned insulated bipolar transistor with adjustable on-state voltage, comprising at least:

[0048] (1) Prepare a P+ type silicon substrate, form an N+ type buffer layer epitaxial silicon layer on the P+ type silicon substrate, form an N- type first drift layer epitaxial silicon layer on the N+ type buffer layer epitaxial silicon layer, and form an N- type diffusion layer on the N- type first drift layer epitaxial silicon layer.

[0049] (2) An ion-implanted photomask is placed on the N-type diffusion layer, and boron atoms are implanted. The amount of boron atoms implanted is 3e. 13 -9e 13 cm- 2 The energy is 60-120 keV, the annealing temperature is 1100-1200℃, and the annealing time is 5-20 min, so as to form an N-type field stop layer and a P-type base layer.

[0050] (3) A trench is formed by etching, which penetrates the P-type base layer, the N-type field stop layer and extends to the N-type first drift layer epitaxial silicon layer.

[0051] (4) A second insulating isolation layer is formed at the bottom of the trench, the second insulating isolation layer including an insulating oxide layer and an insulating nitride layer located on the insulating oxide layer;

[0052] (5) Lateral ion implantation is performed on the device channel on the trench sidewall, and phosphorus atoms are implanted. The amount of phosphorus atoms implanted is 1e. 12 -6e 12 cm -2 The energy is 40-150 keV. When performing lateral ion implantation, the angle between the implantation and the trench sidewall is 30-45°. During lateral ion implantation, the implantation can be performed multiple times depending on the specific structure of the trench, and the etched photomask layer of the trench can be removed.

[0053] (6) A gate insulating oxide layer is provided on the sidewall of the trench, and then a doped polycrystalline silicon gate electrode is deposited.

[0054] (7) Phosphorus atoms are implanted into the middle of the P-type base layer to form an N+ emitter polar region, and boron atoms are implanted on both sides of the N+ emitter polar region to form a P+ emitter polar region. The amount of phosphorus atoms implanted is 1e. 15 -5e 15 cm -2 The energy is 60-100 keV, and the amount of boron atoms implanted is 1e. 14 -1e 15 cm -2 The energy is 60-100 keV;

[0055] (8) A first insulating layer is provided above the trench, the first insulating layer extends to both sides of the trench, the material of the first insulating layer is silicon dioxide, and it extends into the N+ emitter regions on both sides of the trench respectively.

[0056] (9) Finally, an emitter layer is covered on the P+ emitter region and the N+ emitter region, and a collector layer is covered on the lower part of the P-type silicon substrate to obtain the desired result.

[0057] In this technical solution, the inventors perform ion implantation on the side of the trench. By adjusting the concentration of the ion implantation, the on-state voltage can be adjusted, thereby better reducing the on-state voltage drop of the transistor. Furthermore, when the angle between the lateral ion implantation and the trench sidewall is 30-45°, more uniform implantation can be achieved.

[0058] Example

[0059] The present invention will now be described in detail through embodiments. It should be noted that the following embodiments are only for further illustration of the present invention and should not be construed as limiting the scope of protection of the present invention. Non-essential improvements and adjustments made by those skilled in the art based on the above description of the present invention still fall within the scope of protection of the present invention.

[0060] Example 1

[0061] This embodiment provides an insulated bipolar transistor with adjustable conduction voltage, comprising, from bottom to top, a collector layer 14, a P+ type silicon substrate layer 4, an N+ type buffer epitaxial silicon layer 3, an N- type first drift epitaxial silicon layer 2, an N-type field cutoff layer 6, a P-type base layer 5, a trench 15 penetrating the N-type field cutoff layer 6 and the P-type base layer 5 and extending to the N-type first drift epitaxial silicon layer 3, an N+ emitter region 11 and a P+ emitter region 10 located above the P-type base layer 5 on both sides of the trench 15, a first insulating isolation layer 13 located above the trench 15, and emitter layers 12 located above the N+ emitter region 11 and the P+ emitter region 10 on both sides of the trench 15, respectively. The bottom of the trench 15 is a second insulating isolation layer, the interior of the trench is a polycrystalline silicon gate electrode 16, and the sidewalls of the trench 15 are gate insulating oxide layers. The second insulating layer includes an insulating oxide layer 8 and an insulating nitride layer 9 located above the insulating oxide layer 8. The thickness of the insulating oxide layer 8 is 1500 Å. The thickness of the insulating nitride layer 9 is 1500 Å. The concentration of the N+ type buffer epitaxial silicon layer 3 is 10. 17 cm -3 The thickness is 5 μm. The concentration of the N-type first drift layer epitaxial silicon layer 2 is 3e. 14 cm -3 The thickness is 130 μm. The resistivity of the P+ type silicon substrate layer 4 is 0.01 Ω·m. The phosphorus doping concentration in the N+ emitter region is 5e⁻¹. 15 cm -2 The energy is 100 keV. The boron doping concentration in the P+ emitter region is 1e. 15 cm -2 The energy is 100 keV.

[0062] The second aspect of this embodiment provides a method for fabricating the aforementioned insulated bipolar transistor with adjustable on-state voltage, comprising:

[0063] (1) As Figure 1 As shown, a P+ type silicon substrate 4 is prepared, an N+ type buffer epitaxial silicon layer 3 is formed on the P+ type silicon substrate 4, an N- type first drift layer epitaxial silicon layer 2 is formed on the N+ type buffer layer epitaxial silicon layer 3, and an N- type diffusion layer 1 is formed on the N- type first drift layer epitaxial silicon layer 2. The resistivity of the P+ type silicon substrate 4 is 0.01 Ω·m.

[0064] (2) Figure 2 As shown, an ion-implanted photomask is placed on the N-type diffusion layer 1, and boron atoms are implanted. The amount of boron atoms implanted is 9e. 13 cm- 2 The energy is 120 keV, the annealing temperature is 1200℃, and the annealing time is 20 min, so as to form an N-type field stop layer 6 and a P-type base layer 5.

[0065] (3) Figure 3 As shown, a trench 15 is formed by etching, penetrating the P-type base layer 5, the N-type field stop layer 6 and extending to the N-type first drift layer epitaxial silicon layer 2;

[0066] (4) Figure 3 As shown, a second insulating isolation layer is formed at the bottom of the trench 15. The second insulating isolation layer includes an insulating oxide layer 8 and an insulating nitride layer 9 located on the insulating oxide layer 8.

[0067] (5) Figure 4 As shown, lateral ion implantation was performed on the device channel on the sidewall of trench 15, with phosphorus atoms implanted at a rate of 1e. 12 -6e 12 cm -2 The energy is 40-150 keV. When performing lateral ion implantation, the angle between the implantation and the trench sidewall is 30-45°. During lateral ion implantation, the implantation can be performed multiple times depending on the specific structure of the trench, and the etched photomask layer 7 of the trench can be removed.

[0068] (6) A gate insulating oxide layer is provided on the sidewall of trench 15, and then a doped polycrystalline silicon gate electrode is deposited.

[0069] (7) Phosphorus atoms are implanted into the middle of the P-type base layer 5 to form an N+ emitter polar region 11, and boron atoms are implanted on both sides of the N+ emitter polar region 11 to form a P+ emitter polar region 10. The amount of phosphorus atoms implanted is 1e. 15 -5e 15 cm -2 The energy is 60-100 keV, and the amount of boron atoms implanted is 1e. 14 -1e 15 cm -2 The energy is 60-100 keV;

[0070] (8) Figure 5 As shown, a first insulating layer 13 is provided above the trench. The first insulating layer 13 extends to both sides of the trench. The material of the first insulating layer 13 is silicon dioxide, and it extends into the N+ emitter regions 11 on both sides of the trench 15.

[0071] (9) Finally, an emitter layer is covered on the P+ emitter region 10 and the N+ emitter region 11, and a collector layer 14 is covered on the lower part of the P-type silicon substrate layer 4 to obtain the final product.

[0072] In this technical solution, the inventors perform ion implantation laterally within the trench. By adjusting the concentration of the ion implantation, the on-state voltage can be adjusted, thereby better reducing the on-state voltage drop of the transistor. Furthermore, when the angle between the lateral ion implantation and the trench sidewall is 45°, more uniform implantation can be achieved. Figures 6-9 The transistor in this embodiment has a breakdown voltage ≥1300V, a gate voltage <2V, and a forward conduction voltage <1.2V@100A / cm. 2 It has a short-circuit time of <3µs and good static anti-lock-in capability.

[0073] The foregoing examples are merely illustrative, used to explain some features of the method described in this invention. The appended claims are intended to claim the broadest possible scope, and the embodiments presented herein are merely illustrative of selected implementations based on combinations of all possible embodiments. Therefore, the applicant intends that the appended claims are not limited by the selection of examples illustrating the features of the invention. Some numerical ranges used in the claims also include sub-ranges within them, and variations within these ranges should also be interpreted as being covered by the appended claims where possible.

Claims

1. A method for fabricating an insulated bipolar transistor with adjustable on-state voltage, characterized in that, At least including: (1) Prepare a P+ type silicon substrate, form an N+ type buffer layer epitaxial silicon layer on the P+ type silicon substrate, form an N- type first drift layer epitaxial silicon layer on the N+ type buffer layer epitaxial silicon layer, and form an N- type diffusion layer on the N- type first drift layer epitaxial silicon layer; (2) An ion-implanted photomask is placed on the N-type diffusion layer, and boron atoms are implanted. The amount of boron atoms implanted is 3e. 13 -9e 13 cm- 2 The energy is 60-120 keV, the annealing temperature is 1100-1200℃, and the annealing time is 5-20 min, so as to form an N-type field stop layer and a P-type base layer. (3) A trench is formed by etching, which penetrates the P-type base layer, the N-type field stop layer and extends to the N-type first drift layer epitaxial silicon layer; (4) A second insulating isolation layer is formed at the bottom of the trench, the second insulating isolation layer including an insulating oxide layer and an insulating nitride layer located on the insulating oxide layer; (5) Lateral ion implantation is performed on the device channel on the trench sidewall, and phosphorus atoms are implanted. The amount of phosphorus atoms implanted is 1e. 12 -6e 12 cm -2 The energy is 40-150 keV. When performing lateral ion implantation, the angle between the implantation and the trench sidewall is 30-45°. During lateral ion implantation, the implantation can be performed multiple times depending on the specific structure of the trench. Afterward, the etched photomask layer of the trench is removed. (6) A gate insulating oxide layer is provided on the sidewall of the trench, and then a doped polycrystalline silicon gate electrode is deposited; (7) Phosphorus atoms are implanted into the middle of the P-type base layer to form an N+ emitter polar region, and boron atoms are implanted on both sides of the N+ emitter polar region to form a P+ emitter polar region. The amount of phosphorus atoms implanted is 1e. 15 -5e 15 cm -2 The energy is 60-100 keV, and the amount of boron atoms implanted is 1e. 14 -1e 15 cm -2 The energy is 60-100 keV; (8) A first insulating layer is provided above the trench, the first insulating layer extends to both sides of the trench, the material of the first insulating layer is silicon dioxide, and it extends into the N+ emitter regions on both sides of the trench respectively; (9) Finally, an emitter layer is covered on the P+ emitter region and the N+ emitter region, and a collector layer is covered on the lower part of the P-type silicon substrate to obtain the desired result. The adjustable on-state bipolar transistor comprises, from bottom to top, a collector layer, a P+ type silicon substrate layer, an N+ type buffer layer epitaxial silicon layer, an N- type first drift layer epitaxial silicon layer, an N- type field cutoff layer, a P-type base layer, a trench penetrating the N-type field cutoff layer and the P-type base layer and extending to the N-type first drift layer epitaxial silicon layer, an N+ emitter region and a P+ emitter region located above the P-type base layer on both sides of the trench, a first insulating isolation layer located above the trench, and emitter layers located above the N+ emitter region and the P+ emitter region on both sides of the trench, respectively. The bottom of the trench is a second insulating isolation layer, the interior of the trench is a polycrystalline silicon gate electrode, and the sidewall of the trench is a gate insulating oxide layer. The thickness of the insulating oxide layer is 300-1500 Å, and the thickness of the insulating nitrided layer is 500-1500 Å.

2. The method for fabricating an insulated bipolar transistor with adjustable on-state voltage according to claim 1, characterized in that, The second insulating layer includes an insulating oxide layer and an insulating nitride layer located above the insulating oxide layer.

3. The method for fabricating an insulated bipolar transistor with adjustable on-state voltage according to claim 1, characterized in that, The concentration of the N+ type buffer layer epitaxial silicon layer is 10. 16 -10 17 cm -3 The thickness is 2-5um.

4. The method for fabricating an insulated bipolar transistor with adjustable on-state voltage according to claim 1, characterized in that, The concentration of the N-type first drift layer epitaxial silicon layer is 3e 13 -3e 14 cm -3 The thickness is 100-130um.

5. The method for fabricating an insulated bipolar transistor with adjustable on-state voltage according to claim 1, characterized in that, The resistivity of the P+ type silicon substrate is 0.01-0.02 Ω·m.

6. The method for fabricating an insulated bipolar transistor with adjustable on-state voltage according to claim 1, characterized in that, The phosphorus doping concentration in the N+ emitter region is 1e. 15 -5e 15 cm -2 The energy is 60-100 keV.

7. The method for fabricating an insulated bipolar transistor with adjustable on-state voltage according to any one of claims 1-6, characterized in that, The boron doping concentration in the P+ emitter region is 1e. 14 -1e 15 cm -2 The energy is 60-100 keV.

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