Formal light emitting diode and preparation method thereof

Abstract

The invention provides a positive light emitting diode and a preparation method thereof. A transparent dielectric layer is formed between a first part of a transparent conductive layer and an epitaxial layer. The first part of the transparent conductive layer, the transparent dielectric layer and the epitaxial layer can constitute a MIS capacitor structure. The second part of the transparent conductive layer is used for ohmic contact and current expansion. The second electrode can be connected to a relatively high potential and the third electrode can be connected to a relatively low potential, so that a light emitting layer in the epitaxial layer emits light. At the same time, the first electrode is connected to a relatively high potential and the third electrode is connected to a relatively low potential, so that electrons gather from the first semiconductor layer to the light emitting layer and holes gather from the second semiconductor layer to the light emitting layer. The first part and the second part of the transparent conductive layer use different working principles to improve the hole injection efficiency, increase the radiation recombination efficiency in the light emitting layer, and improve the photoelectric conversion efficiency while not reducing the transmission efficiency of the radiation recombination luminescence. The cost is low.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor manufacturing, and in particular to a normal-mounted light-emitting diode and a preparation method thereof. Background Art

[0002] Improving the photoelectric conversion efficiency of light-emitting diodes is a technical focus that has attracted much attention at present, especially for light-emitting diodes based on III-N materials (compound materials formed by III-N materials and nitrogen, such as GaN, AlGaN and other materials). Since P-type doping activation of III-N materials is relatively difficult, the hole concentration of the P-type semiconductor layer of the epitaxial layer is one to two orders of magnitude lower than the electron concentration of the N-type semiconductor layer, and the effective mass of holes is also greater than the effective mass of electrons. At the same time, the mobility of holes is also significantly lower than that of electrons. Therefore, how to obtain a higher hole concentration and a better hole injection effect is one of the key issues in solving the photoelectric conversion efficiency of light-emitting diodes.

[0003] For traditional upright light-emitting diodes, a transparent conductive layer is generally used for ohmic contact and current expansion to achieve efficient hole injection while making the light-emitting surface have a high light transmission efficiency. However, when the size of the upright light-emitting diode is large, the current expansion effect of the transparent conductive layer is limited. At the same time, if the upright light-emitting diode works at a high current density, the current expansion effect of the transparent conductive layer will be further reduced, resulting in poor hole injection effect. At present, the current expansion effect can be increased by increasing the thickness of the transparent conductive layer, but at the same time it will increase light absorption, resulting in a decrease in light transmission efficiency; the conventional transparent conductive layer can also be replaced by a sandwich structure of a transparent conductive layer-ultra-thin metal-transparent conductive layer, but the sputtering process used in the preparation process will damage the surface of the P-type semiconductor layer, and the process parameters of the sandwich structure are difficult to debug and the cost is also high. Summary of the invention

[0004] The object of the present invention is to provide a front-mounted light emitting diode and a preparation method thereof, so as to solve the problem of low photoelectric conversion efficiency of the existing front-mounted light emitting diode.

[0005] In order to achieve the above object, the present invention provides a front mounted light emitting diode, comprising:

[0006] substrate;

[0007] The epitaxial layer is located on the substrate and includes a first semiconductor layer, a light-emitting layer and a second semiconductor layer arranged in sequence from bottom to top;

[0008] A transparent dielectric layer, located on a portion of the second semiconductor layer;

[0009] a transparent conductive layer, comprising a first portion located on the transparent dielectric layer and a second portion located on a portion of the second semiconductor layer, wherein the first portion of the transparent conductive layer, the transparent dielectric layer and the epitaxial layer constitute a MIS capacitor structure; and

[0010] The first electrode, the second electrode and the third electrode are electrically connected to the first portion of the transparent conductive layer, the second portion of the transparent conductive layer and the first semiconductor layer respectively.

[0011] Optionally, the second electrode is located on the second portion of the transparent conductive layer, and is electrically connected to the second semiconductor layer through the second portion of the transparent conductive layer.

[0012] Optionally, the second portion of the transparent conductive layer has a first through hole, and the second electrode is located on the second portion of the transparent conductive layer and fills the first through hole to be directly electrically connected to the second semiconductor layer.

[0013] Optionally, the first electrode is located on a first portion of the transparent conductive layer.

[0014] Optionally, a second perforation is provided in the first portion of the transparent conductive layer and the transparent dielectric layer, the surface of the second semiconductor layer exposed by the second perforation is a high-resistance surface, and the first electrode is located on the first portion of the transparent conductive layer and fills the second perforation to contact the high-resistance surface.

[0015] Optionally, the resistivity of the high-resistance surface is greater than or equal to 10 6 Ω·cm.

[0016] Optionally, when the upright light emitting diode is in use, the first electrode is connected to a first potential, the second electrode is connected to a second potential, the third electrode is connected to a third potential, and the first potential and the second potential are both greater than the third potential.

[0017] Optionally, the difference between the first potential and the third potential is 3V to 10V.

[0018] Optionally, an edge of the epitaxial layer has a step, the step penetrates the second semiconductor layer and the light-emitting layer and exposes the first semiconductor layer, and the third electrode is located on a lower step surface of the step.

[0019] Optionally, also include:

[0020] A passivation layer conformally covers the epitaxial layer, the transparent dielectric layer and the transparent conductive layer, and at least a portion of the surfaces of the first electrode, the second electrode and the third electrode are exposed from the passivation layer.

[0021] Optionally, the passivation layer is made of SiO 2 and / or Al 2 O 3 A single layer or at least two layers of film.

[0022] Optionally, the material of the transparent dielectric layer is SiO 2 、Al 2 O 3 , HfO 2 、SiN x , AlN, BN and MgF 2 At least one of; and / or, the thickness of the transparent dielectric layer is 2nm-30nm.

[0023] Optionally, the width of the front-mounted light emitting diode is greater than or equal to 0.5 mm.

[0024] Optionally, the operating current density of the forward-mounted light-emitting diode is greater than or equal to 350 mA / mm 2 .

[0025] The present invention also provides a method for preparing a normal-mounted light-emitting diode, comprising:

[0026] providing a substrate;

[0027] forming an epitaxial layer, wherein the epitaxial layer is located on the substrate, and the epitaxial layer includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer arranged in sequence from bottom to top;

[0028] forming a transparent dielectric layer, wherein the transparent dielectric layer is located on a portion of the second semiconductor layer;

[0029] forming a transparent conductive layer, the transparent conductive layer comprising a first portion located on the transparent dielectric layer and a second portion located on a portion of the second semiconductor layer, the first portion of the transparent conductive layer, the transparent dielectric layer and the epitaxial layer forming a MIS capacitor structure; and,

[0030] A first electrode, a second electrode and a third electrode are formed, wherein the first electrode, the second electrode and the third electrode are electrically connected to the first portion of the transparent conductive layer, the second portion of the transparent conductive layer and the first semiconductor layer, respectively.

[0031] Optionally, the step of forming the transparent conductive layer includes:

[0032] forming the transparent conductive layer on the transparent dielectric layer and the second semiconductor layer; and,

[0033] etching a partial area of ​​the transparent conductive layer to separate the transparent conductive layer into a first portion of the transparent conductive layer and a second portion of the transparent conductive layer; and,

[0034] The second electrode is formed on the second portion of the transparent conductive layer.

[0035] Optionally, the step of forming the transparent conductive layer includes:

[0036] forming the transparent conductive layer on the transparent dielectric layer and the second semiconductor layer; and,

[0037] Etching a partial area of ​​the transparent conductive layer to separate the transparent conductive layer into a first portion of the transparent conductive layer and a second portion of the transparent conductive layer, and forming a first through hole in the second portion of the transparent conductive layer; and,

[0038] The second electrode is formed on the second portion of the transparent conductive layer and in the first through hole.

[0039] Optionally, after etching a partial area of ​​the transparent conductive layer, the first electrode is formed on a first portion of the transparent conductive layer.

[0040] Optionally, after forming the transparent dielectric layer, a first sub-perforation is formed in the transparent dielectric layer, and the surface of the second semiconductor layer exposed by the first sub-perforation is plasma treated so that the surface of the second semiconductor layer exposed by the first sub-perforation forms a high-resistance surface, and when etching a partial area of ​​the transparent conductive layer, a second sub-perforation is also formed in the first part of the transparent conductive layer, the second sub-perforation is connected to the first sub-perforation to form a second perforation, and the first electrode is formed on the first part of the transparent conductive layer and in the second perforation.

[0041] Optionally, the process gas for the plasma treatment includes at least one of oxygen-based, argon-based and fluorine-based gases.

[0042] Optionally, the resistivity of the high-resistance surface is greater than or equal to 10 6 Ω·cm.

[0043] Optionally, before forming the transparent dielectric layer, a step is formed at the edge of the epitaxial layer, penetrating the second semiconductor layer and the light-emitting layer and exposing the first semiconductor layer, and the third electrode is formed on a lower step surface of the step.

[0044] Optionally, before or after forming the first electrode, the second electrode and the third electrode, the method further includes:

[0045] A passivation layer is formed, wherein the passivation layer conformally covers the epitaxial layer, the transparent dielectric layer, and the transparent conductive layer, and at least a portion of the surfaces of the first electrode, the second electrode, and the third electrode are exposed from the passivation layer.

[0046] The passivation layer is made of SiO 2 and / or Al 2 O 3 A single layer or at least two layers of film.

[0047] Optionally, the material of the transparent dielectric layer is SiO 2 、Al 2 O 3 , HfO 2 、SiN x , AlN, BN and MgF 2 At least one of; and / or, the thickness of the transparent dielectric layer is 2nm-30nm.

[0048] Optionally, the width of the front-mounted light emitting diode is greater than or equal to 0.5 mm.

[0049] Optionally, the operating current density of the forward-mounted light-emitting diode is greater than or equal to 350 mA / mm 2 .

[0050] Optionally, when the upright light emitting diode is in use, the first electrode is connected to a first potential, the second electrode is connected to a second potential, the third electrode is connected to a third potential, and the first potential and the second potential are both greater than the third potential.

[0051] Optionally, the difference between the first potential and the third potential is 3V to 10V.

[0052] In the upright light-emitting diode and the preparation method thereof provided by the present invention, a transparent dielectric layer is formed between the first part of the transparent conductive layer and the epitaxial layer, the first part of the transparent conductive layer, the transparent dielectric layer and the epitaxial layer can constitute a MIS (Metal-Insulator-Semiconductor) capacitor structure, and the second part of the transparent conductive layer is used for ohmic contact and current expansion. When the upright light-emitting diode is in use, the second electrode can be connected to a relatively high potential and the third electrode can be connected to a relatively low potential, so that the light-emitting layer in the epitaxial layer emits light. At the same time, the first electrode is connected to a relatively high potential and the third electrode is connected to a relatively low potential, so that electrons gather from the first semiconductor layer of the epitaxial layer to the light-emitting layer, and holes gather from the second semiconductor layer of the epitaxial layer to the light-emitting layer. The first part and the second part of the transparent conductive layer use different working principles to improve the hole injection efficiency, increase the radiation recombination efficiency in the light-emitting layer, and improve the photoelectric conversion efficiency of the upright light-emitting diode without reducing the transmission efficiency of the radiation recombination luminescence, and the cost is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 A flow chart of a method for preparing a front-mounted light-emitting diode provided in Embodiment 1 of the present invention;

[0054] Figure 2 to Figure 7 A schematic structural diagram corresponding to corresponding steps of the method for preparing a normal-mounted light-emitting diode provided in the first embodiment of the present invention;

[0055] Figure 8 to Figure 11 A schematic structural diagram corresponding to corresponding steps of the method for preparing a normal-mounted light-emitting diode provided in the second embodiment of the present invention;

[0056] Wherein, the accompanying drawings are marked as follows:

[0057] 100-substrate; 200-epitaxial layer; 200a-step; 201-buffer layer; 202-low defect density layer; 203-stress adjustment layer; 204-first semiconductor layer; 205-light-emitting layer; 206-second semiconductor layer; 300-transparent dielectric layer; 300a-first sub-perforation; 400-transparent conductive layer; 401-first part of transparent conductive layer; 401a-second sub-perforation; 402-second part of transparent conductive layer; 402a-first perforation; 304a-second perforation; 500-passivation layer; 601-first electrode; 602-second electrode; 603-third electrode. DETAILED DESCRIPTION

[0058] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0059] Embodiment 1

[0060] Figure 7 This is a schematic diagram of the structure of the upright light emitting diode provided in this embodiment. Figure 7 As shown, the front-mounted light emitting diode includes a substrate 100 , an epitaxial layer 200 , a transparent dielectric layer 300 , a transparent conductive layer 400 , a first electrode 601 , a second electrode 602 and a third electrode 603 .

[0061] Specifically, the substrate 100 is an epitaxial heterogeneous substrate, and its material can be Ga 2 O 3 , SiC, Si, sapphire, ZnO and LiGaO 2 Any one of the above, the thickness can be 300um ~ 2mm, but should not be limited to this.

[0062] The surface of the substrate 100 can be prepared with a micro-nano pattern, thereby improving the luminous efficiency. The micro-nano pattern can be prepared directly on the surface of the substrate 100, or a dielectric layer such as an AlN film can be deposited on the substrate 100 in advance, and the micro-nano pattern is prepared on the dielectric layer. The characteristic size range of the prepared micro-nano pattern can be hundreds of nanometers to several microns, and the pattern array mode can be any one of parallel straight lines, curved lines, squares, and hexagonal arrangements.

[0063] The epitaxial layer 200 is located on the substrate 100, and includes a first semiconductor layer 204, a light-emitting layer 205, and a second semiconductor layer 206 arranged in sequence from bottom to top. In this embodiment, the first semiconductor layer 204 is an N-type semiconductor layer, and the second semiconductor layer 206 is a P-type semiconductor layer; wherein, the first semiconductor layer 204 is an n-GaN layer, the second semiconductor layer 206 is a P-GaN layer, and the light-emitting layer 205 is a multi-quantum well layer (MQW), and the multi-quantum well layer can be stacked by GaInN / GaN with a gradient In component, and the corresponding light-emitting wavelength range is 360nm to 600nm.

[0064] Furthermore, in this embodiment, the epitaxial layer 200 further comprises a buffer layer 201, a low defect density layer 202 and a stress adjustment layer 203 which are sequentially arranged from bottom to top, and the buffer layer 201, the low defect density layer 202 and the stress adjustment layer 203 are stacked and located between the substrate 100 and the first semiconductor layer 204. The buffer layer 201 may be a GaN or AlN layer, the low defect density layer 202 may be a thicker non-intentionally doped GaN layer, and the stress adjustment layer 203 may be a superlattice structure, specifically: between the low defect density layer 202 and the first semiconductor layer 204, the Al component gradually changes (gradually decreases) from the low defect density layer 202 to the first semiconductor layer 204 to form an AlxGa1-xN / AlyGa1-yN superlattice structure, wherein 0<y<x<1, thereby continuing to reduce the stress difference between the substrate 100 and the epitaxial layer 200 caused by the difference in lattice and thermal expansion coefficient.

[0065] It should be understood that other film layers may be formed in the epitaxial layer 200 , for example, an EBL electron blocking layer may be formed between the light emitting layer 205 and the second semiconductor layer 206 , which will not be explained one by one here.

[0066] The epitaxial layer 200 has a step 200a, and the step 200a penetrates the second semiconductor layer 206 and the light-emitting layer 205 and exposes the first semiconductor layer 204. The step 200a is located at the edge of the epitaxial layer 200, and the step 200a serves as a MESA step, the upper step surface of the MESA step is the second semiconductor layer 206, and the lower step surface is the first semiconductor layer 204, and the upper step surface and the lower step surface are connected to form a step side surface.

[0067] Please continue reading Figure 7 The transparent dielectric layer 300 is located on the second semiconductor layer 206 and covers part of the surface of the second semiconductor layer 206. Since the transparent dielectric layer 300 is a transparent film layer, it will not affect light transmission. In this embodiment, the material of the transparent dielectric layer 300 can be SiO 2 、Al 2 O 3 , HfO 2 、SiN x , AlN, BN and MgF 2 At least one of the above may have a thickness of 2 nm to 30 nm, but should not be limited thereto.

[0068] Please continue reading Figure 7, the transparent conductive layer 400 includes a first part 401 and a second part 402 which are insulated from each other, the first part 401 of the transparent conductive layer is located on the transparent dielectric layer 300, covering at least a portion of the transparent dielectric layer 300, and the second part 402 of the transparent conductive layer is located on the second semiconductor layer 206, covering a portion of the second semiconductor layer 206. The first part 401 of the transparent conductive layer, the transparent dielectric layer 300 and the epitaxial layer 200 can form a MIS capacitor structure, and the second part 402 of the transparent conductive layer is used for ohmic contact and current expansion. In this embodiment, the material of the transparent conductive layer 400 can be ITO, IZO, GZO or AZO, and the thickness can be 10nm to 200nm, but it should not be limited thereto.

[0069] Further, the first electrode 601 is located on the first part 401 of the transparent conductive layer, covers at least part of the surface of the first part 401 of the transparent conductive layer, and the first electrode 601 is electrically connected to the first part 401 of the transparent conductive layer; the second part 402 of the transparent conductive layer has a first through hole 402a, the second electrode 602 is located on the second part 402 of the transparent conductive layer and fills the first through hole 402a, and the second electrode 602 is directly electrically connected to the second part 402 of the transparent conductive layer and the second semiconductor layer 206; the third electrode 603 is located on the lower step surface of the step 200a, and is electrically connected to the first semiconductor layer 204. The first electrode 601 serves as one electrode of the MIS capacitor structure, the second electrode 602 serves as the P electrode of the upright light-emitting diode, and the third electrode 603 serves as the other electrode of the MIS capacitor structure and the N electrode of the upright light-emitting diode. The third electrode 603 can be shared or separated into two separate electrodes.

[0070] It should be understood that when the size of the upright light-emitting diode is large, the current spreading effect of the second part 402 of the transparent conductive layer is limited. At the same time, if the upright light-emitting diode operates at a high current density, the current spreading effect of the second part 402 of the transparent conductive layer will be further reduced, resulting in a poor hole injection effect. In this embodiment, since the second part 402 of the transparent conductive layer has the first through-hole 402a, the second electrode 602 can pass through the first through-hole 402a to contact the second semiconductor layer 206, thereby improving the adhesion effect of the second electrode 602 and the second semiconductor layer 206. Of course, as an optional embodiment, the second electrode 602 can be located on the second part 402 of the transparent conductive layer, covering at least a portion of the surface of the second part 402 of the transparent conductive layer, so that the second electrode 602 can also be electrically connected to the second part 402 of the transparent conductive layer and the second semiconductor layer 206.

[0071] In this embodiment, the width of the upright light emitting diode is greater than or equal to 0.5 mm, and the operating current density is greater than or equal to 350 mA / mm 2 , but it should not be limited to this.

[0072] Furthermore, in this embodiment, the first electrode 601, the second electrode 602 and the third electrode 603 all include an adhesive metal layer and a reflective metal layer ( Figure 7 ), the reflective metal layer is located on the adhesive metal layer. The adhesive metal layer can be well adhered to the transparent conductive layer 400 to prevent delamination; the reflectivity of the reflective metal layer can be greater than or equal to 70%, so that it can reflect the light emitted by the light-emitting layer 205 and reduce light absorption. In this embodiment, the material of the reflective metal layer can be at least one of Al, Ag and Au, and the thickness can be 60nm to 500nm; the material of the adhesive metal layer can be at least one of Cr, Ti and Ni, and the thickness can be 2nm to 5nm, but it should not be limited thereto.

[0073] Of course, in some embodiments, the adhesion metal layer may be omitted, which will not be described in detail here.

[0074] Please continue reading Figure 7, the upright light emitting diode also includes a passivation layer 500, and the passivation layer 500 conformally covers the epitaxial layer 200, the transparent dielectric layer 300 and the transparent conductive layer 400 (of course, it also covers the side wall and the lower step surface of the step 200a). In other words, the passivation layer 500 covers the entire surface of the upright light emitting diode, thereby protecting the internal structure of the upright light emitting diode. It should be noted that at least part of the surface of the first electrode 601, the second electrode 602 and the third electrode 603 needs to expose the passivation layer 500 to facilitate the application of voltage. In this embodiment, the passivation layer 500 can be made of SiO 2 and / or Al 2 O 3 A single layer or at least two layers of film, for example, can be made of SiO 2 -Al 2 O 3 -SiO 2 The three-layer film formed can prevent external water vapor from entering, thereby improving the moisture-proof ability of the upright light-emitting diode, but it should not be limited to this.

[0075] In this embodiment, when the upright light emitting diode is in use, the second electrode 602 is connected to the second potential, the third electrode 603 is connected to the third potential, the second potential is greater than the third potential, thereby providing a forward working current for the upright light emitting diode, so that the light emitting layer 205 emits light; at the same time, the first electrode 601 is connected to the first potential, the first potential is greater than the third potential, thereby providing a forward working current for the MIS capacitor structure, so that electrons gather from the first semiconductor layer 204 to the light emitting layer 205, and holes gather from the second semiconductor layer 206 to the light emitting layer 205, which is equivalent to improving the hole injection efficiency, increasing the radiation recombination efficiency in the light emitting layer 205, and improving the photoelectric conversion efficiency of the upright light emitting diode without reducing the transmission efficiency of the radiation recombination luminescence, and the cost is low, which is of great significance for realizing the industrialization of large-size upright light emitting diodes. At the same time, since the second electrode 602 in this embodiment contacts the second semiconductor layer 206 through the first through hole 402a, the adhesion effect of the second electrode 602 and the second semiconductor layer 206 is improved.

[0076] Optionally, the difference between the first potential and the third potential may be 3V to 10V, but should not be limited thereto.

[0077] Figure 1 The flowchart of the method for preparing the upright light emitting diode provided in this embodiment is as follows: Figure 1 As shown, the preparation method of the upright light emitting diode comprises:

[0078] Step S100: providing a substrate;

[0079] Step S200: forming an epitaxial layer, wherein the epitaxial layer is located on the substrate, and the epitaxial layer includes a first semiconductor layer, a light emitting layer, and a second semiconductor layer arranged in sequence from bottom to top;

[0080] Step S300: forming a transparent dielectric layer, wherein the transparent dielectric layer is located on a portion of the second semiconductor layer;

[0081] Step S400: forming a transparent conductive layer, wherein the transparent conductive layer includes a first portion located on the transparent dielectric layer and a second portion located on a portion of the second semiconductor layer, wherein the first portion of the transparent conductive layer, the transparent dielectric layer and the epitaxial layer constitute a MIS capacitor structure; and

[0082] Step S500: forming a first electrode, a second electrode and a third electrode, wherein the first electrode, the second electrode and the third electrode are electrically connected to the first portion of the transparent conductive layer, the second portion of the transparent conductive layer and the first semiconductor layer, respectively.

[0083] Figure 2 to Figure 7 The following is a schematic diagram of the structure corresponding to the corresponding steps of the method for preparing a normal-mounted light-emitting diode provided in this embodiment. Figure 2 to Figure 7 The preparation method of the upright light emitting diode provided in this embodiment is described in detail.

[0084] See also Figure 2 , perform step S100 to provide the substrate 100. At this time, the substrate 100 can be a 1-inch to 8-inch wafer, and the thickness can be 300um to 2mm, but it should not be limited thereto.

[0085] Next, step S200 is performed to form the epitaxial layer 200 on the substrate 100. Specifically, the buffer layer 201, the low defect density layer 202, the stress adjustment layer 203, the first semiconductor layer 204, the light emitting layer 205 and the second semiconductor layer 206 are sequentially formed on the substrate 100. Specifically, the buffer layer 201 can be prepared by a low temperature growth process or a sputtering process, and the low defect density layer 202, the stress adjustment layer 203, the first semiconductor layer 204, the light emitting layer 205 and the second semiconductor layer 206 can be prepared by a metal chemical vapor deposition process, a laser-assisted molecular beam epitaxy process, a laser sputtering process or a hydride vapor phase epitaxy process.

[0086] See also Figure 3, the second semiconductor layer 206 and the light emitting layer 205 are etched downward until the first semiconductor layer 204 is exposed to form the step 200a. Specifically, the step of forming the step 200a includes: making a light emitting area MESA pattern by photolithography, etching the second semiconductor layer 206 and the light emitting layer 205 by ICP to form the step 200a, and the etching depth needs to exceed the light emitting layer 205.

[0087] As an optional embodiment, after the step 200a is formed, the first semiconductor layer 204, the stress adjustment layer 203, the low defect density layer 202 and the buffer layer 201 can be etched downward along the step 200a until the substrate 100 is exposed. After the etching is completed, horizontal and vertical scribe lines are formed. At this time, the scribe lines can be used to define the area of ​​a single upright light-emitting diode, which is convenient for subsequent scribe.

[0088] See also Figure 4 , perform step S300 to form the transparent dielectric layer 300 on a portion of the second semiconductor layer 206. The step of forming the transparent dielectric layer 300 may be: depositing a transparent dielectric material ( ) on the second semiconductor layer 206 by electron beam evaporation, sputtering, atomic layer deposition, plasma assisted deposition, ion beam assisted deposition or chemical vapor deposition. Figure 4 (not shown), and then a wet etching process is used to remove part of the transparent dielectric material on the second semiconductor layer 206, so that part of the transparent dielectric material on the second semiconductor layer 206 is retained, and the remaining transparent dielectric material constitutes the transparent dielectric layer 300.

[0089] See also Figure 5 , perform step S400, form the transparent conductive layer 400 on the transparent dielectric layer 300 and part of the second semiconductor layer 206, the transparent conductive layer 400 includes a first portion 401 and a second portion 402, the first portion 401 of the transparent conductive layer is located on the transparent dielectric layer 300, and the second portion 402 of the transparent conductive layer is located on part of the second semiconductor layer 206. The step of forming the transparent conductive layer 400 includes: forming a transparent conductive material ( Figure 5The transparent conductive material is patterned by photolithography and wet etching to remove unnecessary transparent conductive material. After etching, at least part of the transparent conductive material on the transparent dielectric layer 300 is retained to form the first part 401 of the transparent conductive layer, and part of the transparent conductive material on the second semiconductor layer 206 is retained to form the second part 402 of the transparent conductive layer.

[0090] In this embodiment, when removing the unnecessary transparent conductive material, a portion of the middle area of ​​the second portion 402 of the transparent conductive layer is also removed at the same time, so as to form a first through hole 402 a in the second portion 402 of the transparent conductive layer.

[0091] See also Figure 6 , perform step S500, and simultaneously form the first electrode 601, the second electrode 602, and the third electrode 603, wherein the first electrode 601 is located on the first portion 401 of the transparent conductive layer, the second electrode 602 is located on the second portion 402 of the transparent conductive layer and fills the first through-hole 402a, and the third electrode 603 is located on the lower step surface of the step 200a. The steps of forming the first electrode 601, the second electrode 602, and the third electrode 603 include: forming a photoresist mask to cover the area where the electrode does not need to be formed, then forming a conductive material by an electron beam evaporation process, and then removing the photoresist mask and the conductive material on the photoresist mask by a stripping process, and the conductive material in the area not covered by the photoresist mask is retained, thereby forming the first electrode 601, the second electrode 602, and the third electrode 603.

[0092] See also Figure 7 , the passivation layer 500 is formed on the entire surface of the substrate 100, so that the passivation layer 500 conformally covers the epitaxial layer 200, the transparent dielectric layer 300, the transparent conductive layer 400, the first electrode 601, the second electrode 602 and the third electrode 603, but at least part of the surface of the first electrode 601, the second electrode 602 and the third electrode 603 needs to be exposed from the passivation layer 500. The step of forming the passivation layer 500 includes: using a plasma enhanced chemical vapor deposition process or an atomic layer deposition process to deposit a passivation material ( Figure 6 (not shown), then use photolithography and dry etching processes to remove the passivation material on the surface of part of the first electrode 601, the second electrode 602 and the third electrode 603, and the remaining passivation material constitutes the passivation layer 500.

[0093] As an optional embodiment, the passivation layer 500 can also be formed before forming the first electrode 601, the second electrode 602 and the third electrode 603. In this way, before forming the first electrode 601, the second electrode 602 and the third electrode 603, the passivation layer 500 needs to be etched to form openings to accommodate the first electrode 601, the second electrode 602 and the third electrode 603.

[0094] Furthermore, the substrate 100 is cut along the scribe lines using a grinding wheel or a laser (water-guided laser, laser surface cutting), so as to separate individual upright light-emitting diodes.

[0095] Embodiment 2

[0096] Fig.11 This is a schematic diagram of the structure of the upright light emitting diode provided in this embodiment. Fig.11 As shown, the difference from Example 1 is that, in this embodiment, the first part 401 of the transparent conductive layer and the transparent dielectric layer 300 have a second perforation 304a, and the surface of the second semiconductor layer 206 exposed by the second perforation 304a is a high-resistance surface. The first electrode 601 is located on the first part 401 of the transparent conductive layer and fills the second perforation 304a to contact the high-resistance surface. The first electrode 601 and the second semiconductor layer 206 are insulated by the high-resistance surface to prevent the MIS capacitor structure from short-circuiting.

[0097] It should be understood that due to the different adhesion between metal and medium, and metal and semiconductor, compared with the first embodiment in which the first electrode 601 is formed on the first part 401 of the transparent conductive layer, the present embodiment contacts the first electrode 601 with the high-resistance surface through the second perforation 304a, thereby reducing the thrust difference between the first electrode 601 and the second electrode 602.

[0098] Optionally, the resistivity of the high-resistance surface is greater than or equal to 10 6 Ω·cm, but should not be limited to this.

[0099] Figure 8 to Figure 11 The schematic diagram of the structure corresponding to the corresponding steps of the method for preparing the upright light emitting diode provided in this embodiment is shown below. Figure 8 to Figure 11 The preparation method of the upright light emitting diode provided in this embodiment is described in detail.

[0100] See also Figure 8On the basis of executing step S100 and step S200 in the first embodiment, step S300 is executed to form the transparent dielectric layer 300 on part of the second semiconductor layer 206, wherein the transparent dielectric layer 300 has a first sub-perforation 300a. The step of forming the transparent dielectric layer 300 may be: depositing a transparent dielectric material ( Figure 8 (not shown), and then a wet etching process is used to remove part of the transparent dielectric material on the second semiconductor layer 206, so that part of the transparent dielectric material on the second semiconductor layer 206 is retained, and the remaining transparent dielectric material constitutes the transparent dielectric layer 300.

[0101] Compared with the first embodiment, in this embodiment, when a portion of the transparent dielectric material on the second semiconductor layer 206 is removed by a wet etching process, the first sub-through hole 300 a is also formed in the transparent dielectric layer 300 simultaneously.

[0102] Next, plasma treatment is performed on the surface of the second semiconductor layer 206 exposed by the first sub-through hole 300 a , so that the surface of the second semiconductor layer 206 exposed by the first sub-through hole 300 a forms a high-resistance surface.

[0103] The process gas for the plasma treatment may be at least one of oxygen-based, argon-based and fluorine-based gases.

[0104] See also Fig. 9 , perform step S400, form the transparent conductive layer 400 on the transparent dielectric layer 300 and part of the second semiconductor layer 206, the transparent conductive layer 400 includes a first portion 401 and a second portion 402, the first portion 401 of the transparent conductive layer is located on the transparent dielectric layer 300, and the second portion 402 of the transparent conductive layer is located on part of the second semiconductor layer 206; the first portion 401 of the transparent conductive layer has a second sub-perforation 401a, and the second portion 402 of the transparent conductive layer has a first perforation 402a. The step of forming the transparent conductive layer 400 includes: forming a transparent conductive material ( Fig. 9The transparent dielectric layer 300 is formed by a first sub-throughhole 300a and a second semiconductor layer 206 is formed by a second semiconductor layer 206. ... conductive material is then patterned by a photolithography and a wet etching process to remove unnecessary transparent conductive material. After etching, at least part of the transparent conductive material on the transparent dielectric layer 300 is retained to form a first part 401 of the transparent conductive layer. Part of the transparent conductive material on the second semiconductor layer 206 is retained to form a second part 402 of the transparent conductive layer.

[0105] Compared with the first embodiment, in the present embodiment, when removing the unnecessary transparent conductive material, the transparent conductive material in and above the first sub-perforation 300a is also removed, so that the first portion 401 of the transparent conductive layer has a second sub-perforation 401a, the second sub-perforation 401a exposes the first sub-perforation 300a, and the first sub-perforation 300a and the second sub-perforation 401a are connected to form the second perforation 304a.

[0106] See also Fig.10 , perform step S500, and simultaneously form the first electrode 601, the second electrode 602, and the third electrode 603, wherein the first electrode 601 is located on the first portion 401 of the transparent conductive layer and contacts the high-resistance surface after filling the second through-hole 304a, the second electrode 602 is located on the second portion 402 of the transparent conductive layer and fills the first through-hole 402a, and the third electrode 603 is located on the lower step surface of the step 200a. The steps of forming the first electrode 601, the second electrode 602, and the third electrode 603 include: forming a photoresist mask to cover the area where the electrode does not need to be formed, then forming a conductive material by an electron beam evaporation process, and then removing the photoresist mask and the conductive material on the photoresist mask by a stripping process, and the conductive material in the area not covered by the photoresist mask is retained, thereby forming the first electrode 601, the second electrode 602, and the third electrode 603.

[0107] See also Fig.11, the passivation layer 500 is formed on the entire surface of the substrate 100, so that the passivation layer 500 conformally covers the epitaxial layer 200, the transparent dielectric layer 300, the transparent conductive layer 400, the first electrode 601, the second electrode 602 and the third electrode 603, but at least part of the surface of the first electrode 601, the second electrode 602 and the third electrode 603 needs to be exposed from the passivation layer 500. The step of forming the passivation layer 500 includes: using a plasma enhanced chemical vapor deposition process or an atomic layer deposition process to deposit a passivation material ( Fig.11 (not shown), then use photolithography and dry etching processes to remove the passivation material on the surface of part of the first electrode 601, the second electrode 602 and the third electrode 603, and the remaining passivation material constitutes the passivation layer 500.

[0108] As an optional embodiment, the passivation layer 500 can also be formed before forming the first electrode 601, the second electrode 602 and the third electrode 603. In this way, before forming the first electrode 601, the second electrode 602 and the third electrode 603, the passivation layer 500 needs to be etched to form openings to accommodate the first electrode 601, the second electrode 602 and the third electrode 603.

[0109] Furthermore, the substrate 100 is cut along the scribe lines using a grinding wheel or a laser (water-guided laser, laser surface cutting), so as to separate individual upright light-emitting diodes.

[0110] In summary, in the upright light-emitting diode and the preparation method thereof provided in the embodiments of the present invention, a transparent dielectric layer is formed between the first part of the transparent conductive layer and the epitaxial layer, the first part of the transparent conductive layer, the transparent dielectric layer and the epitaxial layer can constitute a MIS capacitor structure, and the second part of the transparent conductive layer is used for ohmic contact and current expansion. When the upright light-emitting diode is in use, the second electrode can be connected to a relatively high potential and the third electrode can be connected to a relatively low potential, so that the light-emitting layer in the epitaxial layer emits light. At the same time, the first electrode is connected to a relatively high potential and the third electrode is connected to a relatively low potential, so that electrons gather from the first semiconductor layer of the epitaxial layer to the light-emitting layer, and holes gather from the second semiconductor layer of the epitaxial layer to the light-emitting layer. The first part and the second part of the transparent conductive layer use different working principles to improve the hole injection efficiency, increase the radiation recombination efficiency in the light-emitting layer, and improve the photoelectric conversion efficiency of the upright light-emitting diode without reducing the transmission efficiency of the radiation recombination luminescence, and the cost is low.

[0111] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0112] It should also be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

[0113] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are merely used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0114] It should also be recognized that the terms described herein are only used to describe specific embodiments and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or", rather than a logical "exclusive or", unless the context clearly indicates otherwise. In addition, the implementation of the method and / or device in the embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

Claims

1. A normal mounted light emitting diode, characterized in that: include: substrate; The epitaxial layer is located on the substrate and includes a first semiconductor layer, a light-emitting layer and a second semiconductor layer arranged in sequence from bottom to top; A transparent dielectric layer, located on a portion of the second semiconductor layer; A transparent conductive layer, comprising a first portion located on the transparent dielectric layer and a second portion located on a portion of the second semiconductor layer, wherein the first portion of the transparent conductive layer, the transparent dielectric layer and the epitaxial layer form a MIS capacitor structure; as well as, The first electrode, the second electrode and the third electrode are electrically connected to the first portion of the transparent conductive layer, the second portion of the transparent conductive layer and the first semiconductor layer respectively.

2. The upright light emitting diode according to claim 1, characterized in that: The second electrode is located on the second portion of the transparent conductive layer and is electrically connected to the second semiconductor layer through the second portion of the transparent conductive layer.

3. The upright light emitting diode according to claim 1, characterized in that: The second portion of the transparent conductive layer has a first through hole, and the second electrode is located on the second portion of the transparent conductive layer and fills the first through hole to be directly electrically connected to the second semiconductor layer.

4. The upright light emitting diode according to any one of claims 1 to 3, characterized in that: The first electrode is located on a first portion of the transparent conductive layer.

5. The upright light emitting diode according to any one of claims 1 to 3, characterized in that: The first portion of the transparent conductive layer and the transparent dielectric layer have a second through hole, the surface of the second semiconductor layer exposed by the second through hole is a high-resistance surface, the first electrode is located on the first portion of the transparent conductive layer and fills the second through hole to contact the high-resistance surface.

6. The upright light emitting diode according to claim 5, characterized in that: The resistivity of the high resistance surface is greater than or equal to 10 6 Ω·cm.

7. The front-mounted light emitting diode according to claim 1, characterized in that: When the upright light emitting diode is in use, the first electrode is connected to a first potential, the second electrode is connected to a second potential, the third electrode is connected to a third potential, and both the first potential and the second potential are greater than the third potential.

8. The upright light emitting diode according to claim 7, characterized in that: The difference between the first potential and the third potential is 3V to 10V.

9. The front-mounted light emitting diode according to claim 1, characterized in that: The edge of the epitaxial layer has a step, the step penetrates the second semiconductor layer and the light emitting layer and exposes the first semiconductor layer, and the third electrode is located on the lower step surface of the step.

10. The upright light emitting diode according to claim 1 or 9, characterized in that: Also includes: A passivation layer conformally covers the epitaxial layer, the transparent dielectric layer and the transparent conductive layer, and at least a portion of the surfaces of the first electrode, the second electrode and the third electrode are exposed from the passivation layer.

11. The front-mounted light emitting diode according to claim 10, characterized in that: The passivation layer is a single layer or at least two layers of SiO2 and / or Al2O3.

12. The front-mounted light emitting diode according to claim 1, characterized in that: The material of the transparent dielectric layer is SiO2, Al2O3, HfO2, SiN x , at least one of AlN, BN and MgF2; and / or, the thickness of the transparent dielectric layer is 2nm-30nm.

13. The front-mounted light emitting diode according to claim 1, characterized in that: The width of the front-mounted light emitting diode is greater than or equal to 0.5 mm.

14. The front-mounted light emitting diode according to claim 1, characterized in that: The working current density of the upright light emitting diode is greater than or equal to 350mA / mm 2 .

15. A method for preparing a front-mounted light-emitting diode, characterized in that: include: providing a substrate; forming an epitaxial layer, wherein the epitaxial layer is located on the substrate, and the epitaxial layer comprises a first semiconductor layer, a light emitting layer and a second semiconductor layer arranged in sequence from bottom to top; forming a transparent dielectric layer, wherein the transparent dielectric layer is located on a portion of the second semiconductor layer; forming a transparent conductive layer, wherein the transparent conductive layer includes a first portion located on the transparent dielectric layer and a second portion located on a portion of the second semiconductor layer, wherein the first portion of the transparent conductive layer, the transparent dielectric layer and the epitaxial layer constitute a MIS capacitor structure; as well as, A first electrode, a second electrode and a third electrode are formed, wherein the first electrode, the second electrode and the third electrode are electrically connected to the first portion of the transparent conductive layer, the second portion of the transparent conductive layer and the first semiconductor layer, respectively.

16. The method for preparing a front-mounted light emitting diode according to claim 15, characterized in that: The step of forming the transparent conductive layer comprises: forming the transparent conductive layer on the transparent dielectric layer and the second semiconductor layer; and, etching a partial area of ​​the transparent conductive layer to separate the transparent conductive layer into a first portion of the transparent conductive layer and a second portion of the transparent conductive layer; and, The second electrode is formed on the second portion of the transparent conductive layer.

17. The method for preparing a front-mounted light emitting diode according to claim 15, characterized in that: The step of forming the transparent conductive layer comprises: forming the transparent conductive layer on the transparent dielectric layer and the second semiconductor layer; and, Etching a partial area of ​​the transparent conductive layer to separate the transparent conductive layer into a first portion of the transparent conductive layer and a second portion of the transparent conductive layer, and forming a first through hole in the second portion of the transparent conductive layer; and, The second electrode is formed on the second portion of the transparent conductive layer and in the first through hole.

18. The method for preparing a front-mounted light emitting diode according to claim 16 or 17, characterized in that: After etching a partial area of ​​the transparent conductive layer, the first electrode is formed on a first portion of the transparent conductive layer.

19. The method for preparing a front-mounted light emitting diode according to claim 16 or 17, characterized in that: After forming the transparent dielectric layer, a first sub-perforation is formed in the transparent dielectric layer, and a surface of the second semiconductor layer exposed by the first sub-perforation is subjected to plasma treatment so that the surface of the second semiconductor layer exposed by the first sub-perforation forms a high-resistance surface, and when etching a partial area of ​​the transparent conductive layer, a second sub-perforation is also formed in the first part of the transparent conductive layer, the second sub-perforation is connected with the first sub-perforation to form a second perforation, and the first electrode is formed on the first part of the transparent conductive layer and in the second perforation.

20. The method for preparing a front-mounted light emitting diode according to claim 19, characterized in that: The process gas for the plasma treatment includes at least one of oxygen-based, argon-based and fluorine-based gases.

21. The method for preparing a front-mounted light emitting diode according to claim 19, characterized in that: The resistivity of the high resistance surface is greater than or equal to 10 6 Ω·cm.

22. The method for preparing a front-mounted light emitting diode according to claim 15, characterized in that: Before forming the transparent dielectric layer, a step penetrating the second semiconductor layer and the light emitting layer and exposing the first semiconductor layer is formed at the edge of the epitaxial layer, and the third electrode is formed on the lower step surface of the step.

23. The method for preparing a front-mounted light emitting diode according to claim 15, characterized in that: Before or after forming the first electrode, the second electrode and the third electrode, the method further includes: A passivation layer is formed, wherein the passivation layer conformally covers the epitaxial layer, the transparent dielectric layer, and the transparent conductive layer, and at least a portion of the surfaces of the first electrode, the second electrode, and the third electrode are exposed from the passivation layer.

24. The method for preparing a front-mounted light emitting diode according to claim 23, characterized in that: The passivation layer is a single layer or at least two layers of SiO2 and / or Al2O3.

25. The method for preparing a front-mounted light emitting diode according to claim 15, characterized in that: The material of the transparent dielectric layer is SiO2, Al2O3, HfO2, SiN x , at least one of AlN, BN and MgF2; and / or, the thickness of the transparent dielectric layer is 2nm-30nm.

26. The method for preparing a front-mounted light emitting diode according to claim 15, characterized in that: The width of the front-mounted light emitting diode is greater than or equal to 0.5 mm.

27. The method for preparing a front-mounted light emitting diode according to claim 15, characterized in that: The working current density of the upright light emitting diode is greater than or equal to 350mA / mm 2 .

28. The method for preparing a front-mounted light emitting diode according to claim 15, characterized in that: When the upright light emitting diode is in use, the first electrode is connected to a first potential, the second electrode is connected to a second potential, the third electrode is connected to a third potential, and both the first potential and the second potential are greater than the third potential.

29. The method for preparing a front-mounted light emitting diode according to claim 28, characterized in that: The difference between the first potential and the third potential is 3V to 10V.

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