Zero-crossing current spike suppression method and totem pole bridgeless power factor correction circuit

Abstract

The present application provides a method for suppressing zero-crossing current spikes and a totem pole bridgeless power factor correction circuit, belonging to the field of electronic technology. The method includes: determining a first dead time and a second dead time based on the switching period of a pulse signal corresponding to the zero-crossing point; controlling the phase-locked loop to disconnect the first slow-switching bridge arm switch and the second slow-switching bridge arm switch during the first dead time and the second dead time; controlling the first fast-switching bridge arm switch and the second fast-switching bridge arm switch by the first proportional-integral controller during the first dead time; and controlling the first fast-switching bridge arm switch and the second fast-switching bridge arm switch by the second proportional-integral controller during the second dead time. The present application can reduce the zero-crossing current spike and improve the smoothness of the zero-crossing point, thereby achieving the effect of reducing input current harmonics and improving power factor and efficiency.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a method for suppressing a zero-crossing current spike and a totem pole bridgeless power factor correction circuit. Background Art

[0002] With the development of power electronics technology, a wide variety of electronic devices have become commonplace in people's lives. Generally, an AC-DC converter equipped with diodes or thyristors is used to convert 50Hz AC mains power into DC power to power the corresponding electronic devices. However, this AC-DC converter generates a large number of harmonics, which require the use of corresponding correction circuits to reduce harmonics.

[0003] In the related art, a totem pole bridgeless PFC circuit can be used to reduce the harmonics generated when converting AC power to DC power. However, the totem pole bridgeless PFC circuit has the problem of current spikes at the zero-crossing point. Therefore, relevant technicians generally set a period of time to turn off the slow-switching switch tube in the totem pole bridgeless PFC circuit near the zero-crossing point of the AC power, so that the reverse recovery charge of the body diode of the slow-switching switch tube in the totem pole bridgeless PFC circuit can be consumed in the on-resistance of the fast-switching bridge arm switch tube, thereby achieving the purpose of reducing the zero-crossing current spike.

[0004] However, this solution cannot effectively reduce the current spike at the zero-crossing point, and the zero-crossing transition is not smooth enough. Therefore, this solution has the problems of large input current harmonics, low power factor and low efficiency. Summary of the Invention

[0005] The purpose of this application is to provide a method for suppressing zero-crossing current spikes and a totem pole bridgeless power factor correction circuit, which can reduce the zero-crossing current spikes and improve the smoothness of the zero-crossing point, thereby achieving the effect of reducing input current harmonics and improving power factor and efficiency.

[0006] The embodiment of the present application is implemented as follows:

[0007] In a first aspect of an embodiment of the present application, a method for suppressing a zero-crossing current spike is provided, which is applied to a digital controller in a totem pole bridgeless power factor correction circuit. The totem pole bridgeless power factor correction circuit includes: the digital controller, a first proportional-integral controller, a second proportional-integral controller, a phase-locked loop, a first slow-switching bridge arm switch, a second slow-switching bridge arm switch, a first fast-switching bridge arm switch, and a second fast-switching bridge arm switch. The method includes:

[0008] Determining a first dead time and a second dead time according to a switching period of the pulse signal corresponding to the zero crossing point;

[0009] Controlling the phase-locked loop to disconnect the first slow-switching bridge arm switch and the second slow-switching bridge arm switch during the first dead time and the second dead time;

[0010] Controlling the first fast-switching bridge arm switch and the second fast-switching bridge arm switch by the first proportional-integral controller within the first dead time;

[0011] The first fast-switching bridge arm switch and the second fast-switching bridge arm switch are controlled by the second proportional-integral controller within the second dead time.

[0012] Optionally, determining the first dead time and the second dead time according to the switching period in which the zero crossing point of the pulse signal is within the switching period includes:

[0013] Determining that each zero-crossing point of the input alternating current corresponds to a switching period of the pulse signal;

[0014] The zero-crossing point corresponds to a plurality of switching cycles before the switching cycle of the pulse signal as the first dead time;

[0015] The plurality of switching cycles after the switching cycle in which the zero-crossing point corresponds to the pulse signal is used as the second dead time.

[0016] Optionally, controlling the phase-locked loop to disconnect the first slow-switching bridge arm switch and the second slow-switching bridge arm switch during the first dead time and the second dead time includes:

[0017] monitoring in real time by the phase-locked loop whether the period of the pulse signal corresponding to the phase of the current input alternating current is within the first dead time or the second dead time;

[0018] If so, the phase-locked loop is controlled to turn off the first slow-switching bridge arm switch and the second slow-switching bridge arm switch.

[0019] Optionally, controlling the first fast-switching bridge arm switch and the second fast-switching bridge arm switch by the first proportional-integral controller within the first dead time includes:

[0020] Determining the duty cycle of each switching period of the pulse signal within the first dead time, and obtaining a first duty cycle signal;

[0021] The first proportional-integral controller controls the first fast-switching bridge arm switch and the second fast-switching bridge arm switch to soft-start within the first dead time according to the first duty cycle signal.

[0022] Optionally, determining the duty cycle of each switching period of the pulse signal within the first dead time and obtaining a first duty cycle signal includes:

[0023] determining a first duty cycle of the pulse signal in at least one switching cycle before the first dead time;

[0024] determining a second duty cycle of the pulse signal in at least one switching period after the first dead time;

[0025] The duty cycle of each switching period of the pulse signal within the first dead time is adjusted according to the first duty cycle and the second duty cycle to obtain the first duty cycle signal.

[0026] Optionally, controlling the first fast-switching bridge arm switch and the second fast-switching bridge arm switch within the second dead time by the second proportional-integral controller includes:

[0027] Determining the duty cycle of each switching period of the pulse signal within the second dead time by the second proportional-integral controller, and obtaining a second duty cycle signal;

[0028] determining the duty cycle of each switching period of the pulse signal within the second dead time by the first proportional-integral controller, and obtaining a third duty cycle signal;

[0029] Obtaining a fourth duty cycle signal according to the second duty cycle signal and the third duty cycle signal;

[0030] The first fast-switching bridge arm switch and the second fast-switching bridge arm switch are controlled to start within the second dead time by the fourth duty cycle signal.

[0031] Optionally, determining the duty cycle of each switching period of the pulse signal within the second dead time by the second proportional-integral controller and obtaining a second duty cycle signal includes:

[0032] Determining a current set value and a current sampling value of each switching cycle, and determining a duty cycle of each switching cycle of the pulse signal within the second dead time by the second proportional-integral controller;

[0033] According to the current set value, the current sampling value, the preset proportional coefficient and the preset integral coefficient of the second proportional-integral controller, the duty cycle of each switching cycle of the pulse signal within the second dead time is calculated to obtain a second duty cycle signal.

[0034] According to a second aspect of an embodiment of the present application, a totem pole bridgeless power factor correction circuit is provided, the circuit comprising a digital controller, a first proportional-integral controller, a second proportional-integral controller, a third proportional-integral controller, a phase-locked loop, a first slow-switching bridge arm switch, a second slow-switching bridge arm switch, a first fast-switching bridge arm switch, a second fast-switching bridge arm switch, an amplifier, a comparator, a capacitor, an inductor, a load, and an adder;

[0035] The adder is used to input a bus voltage and a reference voltage, and obtain a deviation between the bus voltage and the reference voltage; the output end of the third proportional-integral controller is connected to the first input end of the digital controller, the input end of the third proportional-integral controller is connected to the output end of the adder, the input end of the third proportional-integral controller is used to input the deviation, and the output end of the third proportional-integral controller is used to output a reference current;

[0036] The first output end of the phase-locked loop is connected to the second input end of the digital controller, the third input end of the digital controller is used to input an operating voltage, the output end of the digital controller is used to be connected to the first input end of the first proportional-integral controller and the first input end of the second proportional-integral controller, respectively, the negative phase input end of the amplifier is connected to the second input end of the first proportional-integral controller and the second input end of the second proportional-integral controller, and the output ends of the first proportional-integral controller and the second proportional-integral controller are both used to output a first control signal or a second control signal for controlling the first fast-switching bridge arm switch and the second fast-switching bridge arm switch;

[0037] The second output end of the phase-locked loop is connected to the non-inverting input end of the comparator, the output end of the phase-locked loop is used to output a third control signal for controlling the first slow-switching bridge arm switch and the second slow-switching bridge arm switch, and the output end of the amplifier is connected to the input end of the phase-locked loop;

[0038] The positive phase input terminal of the amplifier is connected to the first end of the inductor, the second end of the inductor is connected to the first end of the first fast switching bridge arm switch and the first end of the second fast switching bridge arm switch respectively, the second end of the first fast switching bridge arm switch is connected to the first end of the first slow switching bridge arm switch, the second end of the second fast switching bridge arm switch is connected to the first end of the second slow switching bridge arm switch, the second end of the first slow switching bridge arm switch and the second end of the second slow switching bridge arm switch are both connected to the negative phase input terminal of the amplifier, the third end of the first slow switching bridge arm switch and the third end of the second slow switching bridge arm switch are used to input the third control signal, and the third end of the first fast switching bridge arm switch and the third end of the second fast switching bridge arm switch are used to input the first control signal or the second control signal;

[0039] The first electrode plate of the capacitor is connected to the first end of the first fast-switching bridge arm switch, the second electrode plate of the capacitor is connected to the second end of the second fast-switching bridge arm switch, the load is connected in parallel with the capacitor, and both ends of the load are used to input the bus voltage;

[0040] The digital controller is used to execute the zero-crossing current spike suppression method as described in the first aspect above.

[0041] Optionally, the first slow-switching bridge arm switch is a first NMOS transistor, the second slow-switching bridge arm switch is a second NMOS transistor, the first fast-switching bridge arm switch is a third NMOS transistor, and the second fast-switching bridge arm switch is a fourth NMOS transistor.

[0042] Optionally, the circuit further includes a driving circuit;

[0043] The input end of the drive circuit is connected to the second proportional-integral controller, the first output end of the drive circuit is connected to the third end of the first fast-switching bridge arm switch, and the second output end of the drive circuit is connected to the third end of the second fast-switching bridge arm switch;

[0044] The circuit further includes an inverter;

[0045] The output end of the comparator is connected to the third end of the first slow-switching bridge arm switch and the input end of the inverter respectively, and the output end of the inverter is connected to the third end of the second slow-switching bridge arm switch.

[0046] According to a third aspect of the present application, a device for suppressing a zero-crossing current spike is provided. The device for suppressing a zero-crossing current spike comprises:

[0047] A determination module, configured to determine a first dead time and a second dead time according to a switching period of a pulse signal corresponding to a zero-crossing point;

[0048] A slow switching bridge arm disconnection module, configured to control the phase-locked loop to disconnect the first slow switching bridge arm switch and the second slow switching bridge arm switch within the first dead time and the second dead time;

[0049] a first fast-switching bridge arm conduction control module, configured to control the first fast-switching bridge arm switch and the second fast-switching bridge arm switch through the first proportional-integral controller within the first dead time;

[0050] The second fast-switching bridge arm control module is configured to control the first fast-switching bridge arm switch and the second fast-switching bridge arm switch within the second dead time through the second proportional-integral controller.

[0051] According to a fourth aspect of an embodiment of the present application, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method for suppressing zero-crossing current spikes described in the first aspect is implemented.

[0052] The beneficial effects of the embodiments of the present application include:

[0053] An embodiment of the present application provides a method for suppressing a zero-crossing current spike, which determines a first dead time and a second dead time according to a switching period of a pulse signal corresponding to a zero-crossing point, controls a phase-locked loop to disconnect a first slow-switching bridge arm switch and a second slow-switching bridge arm switch during the first dead time and the second dead time, controls a first fast-switching bridge arm switch and a second fast-switching bridge arm switch by a first proportional-integral controller during the first dead time, and controls the first fast-switching bridge arm switch and the second fast-switching bridge arm switch by a second proportional-integral controller during the second dead time.

[0054] The phase-locked loop is controlled to disconnect the first slow-switching bridge arm switch and the second slow-switching bridge arm switch during the first dead time and the second dead time, thereby preventing the first slow-switching bridge arm switch, the second slow-switching bridge arm switch, the first fast-switching bridge arm switch, and the second fast-switching bridge arm switch from being turned on at the same time, thereby ensuring the safety of the totem pole bridgeless power factor correction circuit.

[0055] During the first dead time, the first proportional-integral controller controls the first and second fast-switching bridge arm switches. This allows for smooth duty cycle changes before and after the zero crossing point, thereby preventing current spikes caused by sudden duty cycle changes. This effectively suppresses current spikes at the zero crossing point.

[0056] By controlling the first fast-switching bridge arm switch and the second fast-switching bridge arm switch within the second dead time by the second proportional-integral controller, the effect of current tracking voltage can be improved. Specifically, the current tracking within the second dead time is strengthened, thereby improving the performance of tracking the current set value near the zero crossing point.

[0057] In this way, the current peak at the zero-crossing point can be reduced and the smoothness of the zero-crossing point can be improved, thereby achieving the effect of reducing input current harmonics and improving power factor and efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0059] Figure 1 A flow chart of the first method for suppressing zero-crossing current spikes provided in an embodiment of the present application;

[0060] Figure 2 A flow chart of a second method for suppressing zero-crossing current spikes provided in an embodiment of the present application;

[0061] Figure 3 A flowchart of a third method for suppressing zero-crossing current spikes provided in an embodiment of the present application;

[0062] Figure 4 A flowchart of a fourth method for suppressing zero-crossing current spikes provided in an embodiment of the present application;

[0063] Figure 5 A flowchart of a fifth method for suppressing zero-crossing current spikes provided in an embodiment of the present application;

[0064] Figure 6 A flowchart of a sixth method for suppressing zero-crossing current spikes provided in an embodiment of the present application;

[0065] Figure 7 A flowchart of a seventh method for suppressing zero-crossing current spikes provided in an embodiment of the present application;

[0066] Figure 8 A schematic structural diagram of a totem pole bridgeless power factor correction circuit provided in an embodiment of the present application;

[0067] Figure 9 A schematic diagram of dead time provided in an embodiment of the present application;

[0068] Figure 10 A schematic diagram of the principle of a method for suppressing zero-crossing current spikes provided in an embodiment of the present application;

[0069] Figure 11 A schematic structural diagram of a zero-crossing current spike suppression device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0070] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0071] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without creative work are within the scope of protection of the present application.

[0072] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0073] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the inventive product is typically placed when in use. These terms are intended only to facilitate the description of this application and simplify the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting this application. Furthermore, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0074] Furthermore, terms such as "horizontal" and "vertical" do not necessarily mean that a component must be absolutely horizontal or overhanging, but rather that it can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but rather that it can be slightly tilted.

[0075] It should also be noted that, in the description of this application, unless otherwise expressly specified or limited, the terms "disposed," "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0076] In the related art, a totem pole bridgeless PFC circuit can be used to reduce the harmonics generated when converting AC power to DC power. However, this circuit suffers from current spikes at the zero-crossing point. Therefore, relevant technicians generally set a time to shut down the slow-switching switches in the totem pole bridgeless PFC circuit near the AC zero-crossing point. This allows the reverse recovery charge of the slow-switching switches in the totem pole bridgeless PFC circuit to be dissipated by the on-resistance of the fast-switching bridge arm switches, thereby reducing the zero-crossing current spikes. However, this solution does not effectively reduce the zero-crossing current spikes, and the zero-crossing transition is not smooth. As a result, this solution suffers from large input current harmonics, low power factor, and low efficiency.

[0077] To this end, an embodiment of the present application provides a method for suppressing zero-crossing current spikes, by determining a first dead time and a second dead time based on the switching period of the pulse signal corresponding to the zero-crossing point; controlling the phase-locked loop to disconnect the first slow-switching bridge arm switch and the second slow-switching bridge arm switch during the first dead time and the second dead time; controlling the first fast-switching bridge arm switch and the second fast-switching bridge arm switch by the first proportional-integral controller during the first dead time; and controlling the first fast-switching bridge arm switch and the second fast-switching bridge arm switch by the second proportional-integral controller during the second dead time, thereby reducing the zero-crossing current spike and improving the smoothness of the zero-crossing point, thereby achieving the effect of reducing input current harmonics and improving power factor and efficiency.

[0078] The present invention uses the method for suppressing zero-crossing current spikes in a totem pole bridgeless power factor correction circuit as an example to illustrate the present invention. However, this does not mean that the present invention can only be applied to suppressing zero-crossing current spikes in a totem pole bridgeless power factor correction circuit.

[0079] The zero-crossing current spike suppression method provided in the embodiment of the present application is explained in detail below.

[0080] Figure 1 This is a flow chart of a method for suppressing zero-crossing current spikes provided by the present application. This method can be applied to a digital controller in a totem pole bridgeless power factor correction circuit. The totem pole bridgeless power factor correction circuit includes: the digital controller, a first proportional-integral controller, a second proportional-integral controller, a phase-locked loop, a first slow-switching bridge arm switch, a second slow-switching bridge arm switch, a first fast-switching bridge arm switch, and a second fast-switching bridge arm switch. Figure 1 , an embodiment of the present application provides a method for suppressing a zero-crossing current spike, comprising:

[0081] Step 1001: Determine a first dead time and a second dead time according to a switching period of a pulse signal corresponding to a zero-crossing point.

[0082] Optionally, the zero-crossing point refers to the zero-crossing point of the AC power input to the totem pole bridgeless power factor correction circuit. The AC power input to the totem pole bridgeless power factor correction circuit can be referred to as input AC power. The zero-crossing point refers to the moment when the voltage or current of the input AC power is zero. At this moment, the instantaneous voltage or instantaneous current of the input AC power is zero.

[0083] The alternating current may refer to the electric energy provided by a generator or the electric energy directly provided by the mains. Generally, the frequency of the alternating current may be 50 Hz (Hertz), 60 Hz or other possible frequencies. This embodiment of the present application does not limit this.

[0084] Optionally, the pulse signal may be a pulse width modulation (PWM) signal.

[0085] Then, the switching period of the pulse signal may refer to the time interval between two adjacent update pulses of the PWM signal. Since the update of the switching period requires comparison between the modulation wave and the carrier, the switching period is also called the carrier period.

[0086] In addition, the switching period of the pulse signal may represent the switching period of the totem pole bridgeless power factor correction circuit.

[0087] The dead time may be a specific length of inaction time in a switch system set by relevant technical personnel. Specifically, the dead time may refer to a time introduced to prevent multiple transistor switches from being turned on at the same time.

[0088] Optionally, the first dead time may be a period of time before the switching period of the pulse signal corresponding to the zero crossing point. The second dead time may be a period of time after the switching period of the pulse signal corresponding to the zero crossing point. This embodiment of the present application does not limit this.

[0089] It is worth noting that, since the period or frequency of the alternating current may not be the same as the period of the pulse signal, the alternating current may have multiple zero crossings within the same time period. Generally, there may be two zero crossings within one period of the alternating current. Since the peak current near the zero crossing can be suppressed by adjusting the duty cycle of the pulse signal, it is necessary to determine in which switching cycle of the pulse signal each zero crossing of the alternating current is located. In this way, the first dead time and the second dead time for controlling the first slow switching bridge arm switch, the second slow switching bridge arm switch, the first fast switching bridge arm switch, and the second fast switching bridge arm switch in the totem pole bridgeless power factor correction circuit can be determined. In this way, it is convenient to subsequently control the first slow switching bridge arm switch, the second slow switching bridge arm switch, the first fast switching bridge arm switch, and the second fast switching bridge arm switch respectively within the first dead time and / or the second dead time.

[0090] Step 1002: Control the phase-locked loop to turn off the first slow-switching bridge arm switch and the second slow-switching bridge arm switch during the first dead time and the second dead time.

[0091] Optionally, the phase-locked loop (PLL) is a negative feedback control device that uses a voltage generated by phase synchronization to adjust a voltage-controlled oscillator to produce a target frequency. The PLL is a feedback control circuit based on the principle of automatic control. The PLL uses a reference signal input to the PLL to control the frequency and phase of the pulse signal within the totem pole bridgeless power factor correction circuit, thereby enabling the output signal frequency to automatically track the input signal frequency.

[0092] It is worth noting that controlling the phase-locked loop to disconnect the first slow-switching bridge arm switch and the second slow-switching bridge arm switch during the first dead time and the second dead time may mean continuously disconnecting the first slow-switching bridge arm switch and the second slow-switching bridge arm switch during the first dead time and the second dead time. In this way, the first slow-switching bridge arm switch, the second slow-switching bridge arm switch, the first fast-switching bridge arm switch, and the second fast-switching bridge arm switch can be prevented from being turned on simultaneously, thereby ensuring the safety of the totem pole bridgeless power factor correction circuit.

[0093] Step 1003: Control the first fast-switching bridge arm switch and the second fast-switching bridge arm switch by the first proportional-integral controller within the first dead time.

[0094] Optionally, the proportional-integral parameter of the first proportional-integral controller may be set to be relatively large, so that a smooth transition of the current crossing the zero point may be achieved through optimization of the first proportional-integral controller.

[0095] It is worth noting that the first fast-switching bridge arm switch and the second fast-switching bridge arm switch can be soft-started during the first dead time. In this way, the starting current during the startup process is converted from an uncontrollable overload surge current to a controllable, slowly increasing current. This can reduce the inrush current of the totem pole bridgeless power factor correction circuit, prevent damage to components in the totem pole bridgeless power factor correction circuit, and further improve the stability and safety of zero-crossing current spike suppression.

[0096] It is worth noting that by soft-starting the first fast-switching bridge arm switch and the second fast-switching bridge arm switch through the first proportional-integral controller, the duty cycle of the first fast-switching bridge arm switch and the second fast-switching bridge arm switch can be smoothly changed before and after the zero-crossing point, thereby avoiding current spikes caused by sudden changes in the duty cycle. In this way, zero-crossing current spikes can be effectively suppressed.

[0097] Step 1004 : Control the first fast-switching bridge arm switch and the second fast-switching bridge arm switch within the second dead time by using the second proportional-integral controller.

[0098] Optionally, the second proportional-integral controller may be an enhanced proportional-integral controller.

[0099] Generally, the proportional-integral parameter of the second proportional-integral controller can be set to be very large. Specifically, the proportional-integral parameter of the second proportional-integral controller can be set to be larger than the proportional-integral parameter of the first proportional-integral controller.

[0100] It is worth noting that, since the proportional integral parameter of the second proportional integral controller is large, controlling the first fast-switching bridge arm switch and the second fast-switching bridge arm switch through the second proportional integral controller can improve the effect of current tracking voltage, specifically strengthening the current tracking within the second dead time, thereby improving the performance of tracking the current set value near the zero crossing point.

[0101] In an embodiment of the present application, the first dead time and the second dead time are determined based on the switching period of the pulse signal corresponding to the zero crossing point, and the phase-locked loop is controlled to disconnect the first slow-switching bridge arm switch and the second slow-switching bridge arm switch within the first dead time and the second dead time. The first fast-switching bridge arm switch and the second fast-switching bridge arm switch are controlled by the first proportional-integral controller within the first dead time, and the first fast-switching bridge arm switch and the second fast-switching bridge arm switch are controlled by the second proportional-integral controller within the second dead time.

[0102] The phase-locked loop is controlled to disconnect the first slow-switching bridge arm switch and the second slow-switching bridge arm switch during the first dead band and the second dead band, thereby preventing the first slow-switching bridge arm switch, the second slow-switching bridge arm switch, the first fast-switching bridge arm switch, and the second fast-switching bridge arm switch from being turned on at the same time, thereby ensuring the safety of the totem pole bridgeless power factor correction circuit.

[0103] By controlling the first fast-switching bridge arm switch and the second fast-switching bridge arm switch via the first proportional-integral controller during the first dead time, the duty cycle of the first fast-switching bridge arm switch and the second fast-switching bridge arm switch can be smoothly varied before and after the zero-crossing point, thereby avoiding current spikes caused by sudden duty cycle changes. Thus, zero-crossing current spikes can be effectively suppressed.

[0104] By controlling the first fast-switching bridge arm switch and the second fast-switching bridge arm switch through the second proportional-integral controller within the second dead time, the effect of current tracking voltage can be improved, specifically, the current tracking within the second dead time is enhanced, thereby improving the performance of tracking the current set value near the zero crossing point.

[0105] In this way, the current peak at the zero-crossing point can be reduced and the smoothness of the zero-crossing point can be improved, thereby achieving the effect of reducing input current harmonics and improving power factor and efficiency.

[0106] In one possible embodiment, the functions of the first proportional-integral controller and the second proportional-integral controller can also be implemented by the same proportional-integral controller. That is, the first fast-switching bridge arm switch and the second fast-switching bridge arm switch can be controlled by the same proportional-integral controller during the first dead time, and the first fast-switching bridge arm switch and the second fast-switching bridge arm switch can be controlled by the same proportional-integral controller during the second dead time.

[0107] In this case, the proportional-integral controller can be adjusted to different parameters within the first dead time and the second dead time. For example, proportional-integral parameters such as the preset proportional coefficient and the preset integral coefficient of the proportional-integral controller can be adjusted within the first dead time and the second dead time.

[0108] For example, if only one proportional-integral controller controls the first and second fast-switching bridge arm switches during the first and second dead bands, then the proportional-integral parameter of this proportional-integral controller can be set relatively large during the first dead band, while the proportional-integral parameter of this proportional-integral controller can be enhanced during the second dead band, setting a larger proportional-integral parameter than that during the first dead band. In this way, the purpose of controlling the first and second fast-switching bridge arm switches during the first and second dead bands by a single proportional-integral controller can be achieved. For specific control methods, see other embodiments. This can reduce costs.

[0109] In one possible implementation, see Figure 2 , determining the first dead time and the second dead time according to the switching period of the pulse signal at which the zero crossing point is located, including:

[0110] Step 1005: Determine whether each zero-crossing point of the input AC power corresponds to a switching period of the pulse signal.

[0111] Since the direction and magnitude of the AC power input to the totem pole bridgeless power factor correction circuit will produce periodic changes in unit time, there will be a situation where the instantaneous voltage or instantaneous current of the input AC power is 0, which is the zero-crossing point of the input AC power.

[0112] Within a period of time, the input AC power may have multiple zero-crossing points, and the pulse signal may also have multiple switching cycles within this period of time. Therefore, by determining the switching cycle of the pulse signal corresponding to each zero-crossing point of the input AC power, the pulse signal and the zero-crossing point of the AC power can be placed in the same time dimension.

[0113] Step 1006: The zero-crossing point corresponds to a plurality of switching cycles before the switching cycle of the pulse signal as the first dead time.

[0114] It can be seen that the first dead time is a period of time before any zero-crossing point of the input AC power. Specifically, the first dead time can be a plurality of switching cycles of the pulse signal before any zero-crossing point of the input AC power.

[0115] Optionally, the number of multiple switching cycles preceding the switching cycle of the pulse signal corresponding to the zero crossing point can be set according to actual needs. Generally, 8 or 10 switching cycles preceding the switching cycle of the pulse signal corresponding to the zero crossing point can be used as the first dead time. Of course, any other possible number of switching cycles can also be selected as the first dead time. This embodiment of the present application is not limited to this.

[0116] Step 1007: The plurality of switching cycles after the switching cycle in which the zero-crossing point corresponds to the pulse signal is used as the second dead time.

[0117] It can be seen that the second dead time is a period of time after any zero-crossing point of the input AC power.

[0118] Optionally, the number of multiple switching cycles after the switching cycle of the pulse signal corresponding to the zero crossing point can be set according to actual needs. Generally, 8 or 10 switching cycles after the switching cycle of the pulse signal corresponding to the zero crossing point can be used as the second dead time. Of course, any other possible number of switching cycles can also be selected as the second dead time. This embodiment of the present application is not limited to this.

[0119] It is worth noting that each zero crossing point of the input alternating current within a period of time corresponds to a first dead time and a second dead time. In addition, the time length of the second dead time is equal to the time length of the first dead time. For example, the 10 switching cycles before the switching cycle of the pulse signal corresponding to the zero crossing point are used as the first dead time, then the 10 switching cycles after the switching cycle of the pulse signal corresponding to the zero crossing point are needed as the second dead time. In this way, it is possible to ensure that the control time before the zero crossing point and after the zero crossing point is symmetrical, and the stability of the zero crossing current spike suppression can be improved. In this way, it is convenient to subsequently control the first slow switching bridge arm switch, the second slow switching bridge arm switch, the first fast switching bridge arm switch and the second fast switching bridge arm switch respectively within the first dead time and / or the second dead time.

[0120] In one possible implementation, see Figure 3 , controlling the phase-locked loop to disconnect the first slow-switching bridge arm switch and the second slow-switching bridge arm switch during the first dead time and the second dead time, comprising:

[0121] Step 1008: Monitor in real time through the phase-locked loop whether the period of the pulse signal corresponding to the phase of the current input AC power is within the first dead time or the second dead time.

[0122] In this way, it can be determined in real time and accurately whether the input AC power enters the first dead time or the second dead time set in advance.

[0123] Step 1009: If yes, control the phase-locked loop to turn off the first slow-switching bridge arm switch and the second slow-switching bridge arm switch.

[0124] Optionally, the phase-locked loop may output a specific control signal to control the first slow-switching bridge arm switch and the second slow-switching bridge arm switch to be alternately disconnected or alternately turned on.

[0125] It is worth noting that, when it is determined in real time and accurately that the input AC power enters the first dead time or the second dead time set in advance, the first slow-switching bridge arm switch and the second slow-switching bridge arm switch are alternately disconnected. In this way, it is possible to reliably avoid the first slow-switching bridge arm switch, the second slow-switching bridge arm switch, the first fast-switching bridge arm switch and the second fast-switching bridge arm switch from being turned on at the same time, thereby ensuring the safety of the totem pole bridgeless power factor correction circuit.

[0126] In one possible implementation, see Figure 4 , controlling the first fast-switching bridge arm switch and the second fast-switching bridge arm switch by the first proportional-integral controller within the first dead time, including:

[0127] Step 1010: Determine the duty cycle of each switching cycle of the pulse signal within the first dead time, and obtain a first duty cycle signal.

[0128] Optionally, the first duty cycle signal may be a pulse signal whose duty cycle is adjusted to a specific duty cycle, and the specific duty cycle may be the duty cycle of each switching cycle of the pulse signal determined within the first dead time. This embodiment of the present application does not limit this.

[0129] Step 1011 : controlling the first fast-switching bridge arm switch and the second fast-switching bridge arm switch to soft-start within the first dead time according to the first duty cycle signal through the first proportional-integral controller.

[0130] By adjusting the duty cycle of the pulse signal, duty cycle control, also known as electronically controlled pulse width modulation technology, can be achieved. Then, the first proportional-integral controller can be used to control the first fast-switching bridge arm switch and the second fast-switching bridge arm switch according to the first duty cycle signal to achieve soft start within the first dead time.

[0131] In this way, the surge current of the totem pole bridgeless power factor correction circuit can be reduced, and damage to components in the totem pole bridgeless power factor correction circuit can be avoided, thereby improving the stability and safety of zero-crossing current spike suppression.

[0132] In one possible implementation, see Figure 5 , determining the duty cycle of each switching cycle of the pulse signal within the first dead time, and obtaining a first duty cycle signal, including:

[0133] Step 1012: Determine a first duty cycle of the pulse signal in at least one switching cycle before the first dead time.

[0134] Step 1013: Determine a second duty cycle of the pulse signal in at least one switching cycle after the first dead time.

[0135] Step 1014: Adjust the duty cycle of each switching period of the pulse signal within the first dead time according to the first duty cycle and the second duty cycle to obtain the first duty cycle signal.

[0136] Optionally, the duty cycle of each switching period of the pulse signal within the first dead time is increasing.

[0137] For example, assuming that the first dead time is 10 switching cycles before the switching cycle of the pulse signal corresponding to a zero crossing point of the input alternating current, then the first duty cycle can be the duty cycle of the pulse signal determined in one switching cycle before the first dead time, and the second duty cycle can be the duty cycle of the pulse signal determined in one switching cycle after the first dead time.

[0138] Then, the duty cycle G1[value] of the fast switching tube in each switching cycle within the first dead time can be calculated using the following formula (1).

[0139] The following formula (1) is as follows:

[0140]

[0141] Where k represents the order of the switching cycles corresponding to the zero-crossing point within an input AC cycle within each switching cycle of the pulse signal, and value represents the value-th switching cycle within an AC power cycle. G1[k-10] represents the duty cycle of the k-10th switching cycle, and G1[k+1] represents the duty cycle of the k+1th switching cycle. The k-10th switching cycle is the switching cycle before soft start, that is, the switching cycle before the first dead time. The k+1th switching cycle is the switching cycle after soft start, that is, the switching cycle after the first dead time.

[0142] In addition, the calculated first duty cycle and the second duty cycle can be corrected and enhanced by using the first proportional-integral controller. This embodiment of the present application does not limit this.

[0143] Optionally, the first duty cycle signal can be obtained by adjusting the duty cycle of the pulse signal to the duty cycle G1[value], which is not limited in the embodiment of the present application.

[0144] This allows for smooth duty cycle changes before and after the zero crossing of the first and second fast-switching bridge arm switches, thus avoiding current spikes caused by sudden duty cycle changes. This reduces zero-crossing current spikes and improves zero-crossing smoothness, thereby reducing input current harmonics and improving power factor and efficiency.

[0145] In one possible implementation, see Figure 6 , controlling the first fast-switching bridge arm switch and the second fast-switching bridge arm switch within the second dead time by the second proportional-integral controller, comprising:

[0146] Step 1015: Determine the duty cycle of each switching cycle of the pulse signal within the second dead time using the second proportional-integral controller to obtain a second duty cycle signal. Using the second proportional-integral controller with a larger proportional-integral parameter to generate the second duty cycle signal can further improve current tracking performance.

[0147] Step 1016: Determine the duty cycle of each switching period of the pulse signal within the second dead time through the first proportional-integral controller, and obtain a third duty cycle signal.

[0148] That is, the duty cycle of each switching period of the pulse signal within the second dead time can be determined by the first proportional-integral controller within the second dead time, and a third duty cycle signal can be obtained.

[0149] Optionally, the third duty cycle signal can be obtained by adjusting the duty cycle of the pulse signal to determine the duty cycle of each switching cycle of the pulse signal within the second dead time through the first proportional-integral controller, which is not limited in this embodiment of the present application.

[0150] Exemplarily, the third duty cycle signal can also be calculated using the above formula (1). In this case, the k-10th switching cycle in formula (1) is a switching cycle before the second dead time. The k+1th switching cycle is a switching cycle after the second dead time.

[0151] Step 1017: Obtain the fourth duty cycle signal according to the second duty cycle signal and the third duty cycle signal.

[0152] Specifically, the fourth duty cycle signal can be obtained by superimposing the second duty cycle signal and the third duty cycle signal, which is not limited in the embodiment of the present application.

[0153] Step 1018: Control the first fast-switching bridge arm switch and the second fast-switching bridge arm switch to start within the second dead time according to the fourth duty cycle signal through the second proportional-integral controller.

[0154] This improves the current's ability to track the voltage, specifically by strengthening current tracking during the second dead time, and thus improving the performance of tracking the current setpoint near the zero crossing. This reduces the current spike at the zero crossing and improves the smoothness of the zero crossing, thereby reducing input current harmonics and improving power factor and efficiency.

[0155] In one possible implementation, see Figure 7 , determining the duty cycle of each switching cycle of the pulse signal within the second dead time by the second proportional-integral controller, and obtaining a second duty cycle signal, including:

[0156] Step 1019: Determine the current set value and the current sampling value of each switching cycle, and determine the duty cycle of each switching cycle of the pulse signal within the second dead time through the second proportional-integral controller.

[0157] Optionally, the current set value may refer to a current value that a person skilled in the art expects to obtain from the totem pole bridgeless power factor correction circuit. The current sampling value may refer to a current value actually sampled from the totem pole bridgeless power factor correction circuit or a current value actually output by the totem pole bridgeless power factor correction circuit.

[0158] Step 1020: Calculate the duty cycle of each switching cycle of the pulse signal within the second dead time according to the current set value, the current sampling value, the preset proportional coefficient and the preset integral coefficient of the second proportional-integral controller, and obtain a second duty cycle signal.

[0159] Optionally, the preset proportional coefficient may be an error proportional coefficient of the second proportional-integral controller. The preset integral coefficient may be an integral proportional coefficient of the second proportional-integral controller.

[0160] For example, the duty cycle G2[value] of each switching period of the pulse signal within the second dead time can be calculated using the following formula (2).

[0161] The following formula (2) is as follows:

[0162] G2[value]=K P2 (sin[value]-sin pre [value])+K i2 ∫0 t (sin[value]-sin pre [value])dt

[0163] Among them, sin[value] is the current given value of the value-th switching cycle, sin pre [value] is the current sampling value of the valueth switching cycle. K P2 is the error proportional coefficient of the second proportional-integral controller, K i2 is the integral proportional coefficient of the second proportional-integral controller.

[0164] After executing step 1020 , steps 1016 and 1017 may be continued.

[0165] For example, the duty cycle signal G of the fourth duty cycle signal can be obtained by superimposing the second duty cycle signal and the third duty cycle signal using the following formula (3): total .

[0166] The following formula (3) is as follows:

[0167] G total =G2[value]+G3[value]

[0168] Among them, G2[value] can represent the second duty cycle signal mentioned above, and G3[value] can represent the third duty cycle signal mentioned above.

[0169] In this way, a fourth duty cycle signal can be obtained for controlling the disconnection of the first fast-switching bridge arm switch and the second fast-switching bridge arm switch during the second dead time, facilitating subsequent operations. This can improve the current tracking voltage effect, specifically strengthening current tracking during the second dead time, thereby improving the performance of tracking the current setpoint near the zero crossing point.

[0170] This application also provides a totem pole bridgeless power factor correction circuit, see Figure 8 The totem pole bridgeless power factor correction circuit includes a digital controller M, a first proportional integral controller PI1, a second proportional integral controller PI2, a third proportional integral controller PI3, a phase-locked loop PLL, a first fast-switching bridge arm switch S1, a second fast-switching bridge arm switch S2, a first slow-switching bridge arm switch S3, a second slow-switching bridge arm switch S4, a capacitor C, a load R, an inductor L, and an adder Q.

[0171] The adder Q is used to input the bus voltage and the reference voltage, and obtain the deviation between the bus voltage and the reference voltage.

[0172] The output end of the third proportional-integral controller PI3 is connected to the first input end of the digital controller M, the input end of the third proportional-integral controller PI3 is connected to the output end of the adder Q, the input end of the third proportional-integral controller PI3 is used to input the deviation between the bus voltage and the reference voltage, and the output end of the third proportional-integral controller PI3 is used to output the reference current amplitude.

[0173] The first output end of the phase-locked loop PLL is connected to the second input end of the digital controller M, the third input end of the digital controller M is used to input the operating voltage, the output end of the digital controller M is used to connect to the first input end of the first proportional-integral controller PI1 and the second proportional-integral controller PI2, the negative phase input end of the amplifier U1 is connected to the second input end of the first proportional-integral controller PI1 and the second proportional-integral controller PI2, and the output ends of the first proportional-integral controller PI1 and the second proportional-integral controller PI2 are both used to output the first control signal or the second control signal for controlling the first fast-switching bridge arm switch S1 and the second fast-switching bridge arm switch S2.

[0174] The second output end of the phase-locked loop PLL is connected to the non-inverting input end of the comparator U2. The output end of the phase-locked loop PLL is used to output a third control signal for controlling the first slow switching bridge arm switch S3 and the second slow switching bridge arm switch S4. The output end of the amplifier U1 is connected to the input end of the phase-locked loop PLL.

[0175] The positive phase input terminal of the amplifier U1 is connected to the first end of the inductor L, the second end of the inductor L is respectively connected to the first end of the first fast switching bridge arm switch S1 and the first end of the second fast switching bridge arm switch S2, the second end of the first fast switching bridge arm switch S1 is connected to the first end of the first slow switching bridge arm switch S3, the second end of the second fast switching bridge arm switch S2 is connected to the first end of the second slow switching bridge arm switch S4, the second end of the first slow switching bridge arm switch S3 and the second end of the second slow switching bridge arm switch S4 are both connected to the negative phase input terminal of the amplifier U1, the third end of the first slow switching bridge arm switch S3 and the third end of the second slow switching bridge arm switch S4 are used to input the third control signal, and the third end of the first fast switching bridge arm switch S1 and the third end of the second fast switching bridge arm switch S2 are used to input the first control signal or the second control signal.

[0176] The first plate of the capacitor C is connected to the first end of the first fast-switching bridge arm switch S1, the second plate of the capacitor C is connected to the second end of the second fast-switching bridge arm switch S2, the load R is connected in parallel with the capacitor C, and the two ends of the load R are used to input the bus voltage.

[0177] Optionally, the first slow-switching bridge arm switch S3 is a first NMOS transistor, and the second slow-switching bridge arm switch S4 is a second NMOS transistor.

[0178] Optionally, the first fast-switching bridge arm switch S1 is a third NMOS transistor, and the second fast-switching bridge arm switch S2 is a fourth NMOS transistor.

[0179] Optionally, the amplification factor of the amplifier U1 may be 1, that is, the amplifier U1 may be a follower. Of course, the amplification factor of the amplifier U1 may also be any other value, which is not limited in the embodiment of the present application.

[0180] In addition, the digital controller M is used to execute the various steps in the above-mentioned zero-crossing current spike suppression method.

[0181] In the totem pole bridgeless power factor correction circuit, closed-loop control of voltage outer loop and current inner loop is adopted. The voltage outer loop control inputs the bus voltage Vbus and the reference voltage Vbus_ref into the adder Q, and the deviation between the bus voltage Vbus and the reference voltage Vbus_ref obtained by the adder Q is input into the input end of the third proportional integral controller PI3. The reference current amplitude of the current inner loop is calculated by the third proportional integral controller PI3.

[0182] In addition, the reference current amplitude of the inner current loop is input into the digital controller M, the signal sinθ of the phase-locked loop PLL is input into the digital controller M, the input working voltage Vac / the amplitude Vac_max of the working voltage is input into the digital controller M, and the digital controller M calculates the reference current amplitude of the inner current loop, the product of the signal sinθ and the working voltage Vac / the amplitude Vac_max of the working voltage to obtain the reference current Iref.

[0183] The digital controller M inputs the reference current Iref into the first proportional-integral controller PI1, and inputs the input current Iac into the first proportional-integral controller PI1. The first proportional-integral controller PI1 compares the reference current Iref with the input current Iac, and adopts average current control to calculate the on-time Ton of the first fast-switching bridge arm switch S1 and the second fast-switching bridge arm switch S2 in the current switching cycle, and outputs corresponding first control signals and second control signals to the first fast-switching bridge arm switch S1 and the second fast-switching bridge arm switch S2, respectively.

[0184] In addition, the comparator U2 can be used to compare the input voltage Vac with the zero voltage. When Vac is greater than 0, the first slow-cut bridge arm switch S3 is turned on and the second slow-cut bridge arm switch S4 is turned off. When Vac is less than 0, the first slow-cut bridge arm switch S3 is turned off and the second slow-cut bridge arm switch S4 is turned on.

[0185] It is worth noting that the digital controller M executes the various steps in the above-mentioned zero-crossing current spike suppression method to achieve the functions and effects of the above-mentioned zero-crossing current spike suppression method, which will not be elaborated here.

[0186] In a possible manner, the functions of the first proportional-integral controller PI1 and the second proportional-integral controller PI2 may also be implemented by the same proportional-integral controller.

[0187] For example, assuming that the functions of the first proportional-integral controller PI1 and the second proportional-integral controller PI2 can be implemented by a proportional-integral controller PI0, then in the totem pole bridgeless power factor correction circuit, the output end of the proportional-integral controller PI0 is connected to the first input end of the digital controller M, the input end of the proportional-integral controller PI0 is used to input the bus voltage and the reference voltage, and the output end of the proportional-integral controller PI0 is used to output the reference current.

[0188] In addition, the digital controller M can also input the reference current Iref into the proportional-integral controller PI0, and input the input current Iac into the proportional-integral controller PI0. The proportional-integral controller PI0 compares the reference current Iref and the input current Iac, and adopts average current control to calculate the conduction time Ton of the first fast-switching bridge arm switch S1 and the second fast-switching bridge arm switch S2 in the current switching cycle, and outputs the corresponding first control signal and second control signal to the first fast-switching bridge arm switch S1 and the second fast-switching bridge arm switch S2, respectively.

[0189] In one possible approach, see Figure 8 The totem pole bridgeless power factor correction circuit also includes a driving circuit.

[0190] The input end of the drive circuit is connected to the second proportional-integral controller PI2, the first output end of the drive circuit is connected to the third end of the first fast-switching bridge arm switch S1, and the second output end of the drive circuit is connected to the third end of the second fast-switching bridge arm switch S2.

[0191] In this case, after calculating the on-time Ton of the first fast-switching bridge arm switch S1 and the second fast-switching bridge arm switch S2 in the current switching cycle, the second proportional-integral controller PI2 can output corresponding electrical signals to the drive circuit, and then the drive circuit generates signals V S1 Output to the third terminal of the first fast switching bridge arm switch S1, generating a signal V S2 Output to the third end of the second fast switching bridge arm switch S2 to control the first fast switching bridge arm switch S1 and the second fast switching bridge arm switch S2 respectively. That is, the first control signal and / or the second control signal can be output to the third end of the second fast switching bridge arm switch S2 to control the first fast switching bridge arm switch S1 and the second fast switching bridge arm switch S2 respectively. S1 and signal V S2 to achieve.

[0192] Signal V S1 and signal V S2Can be complementary control signals.

[0193] In this way, precise control of the first fast-switching bridge arm switch S1 and the second fast-switching bridge arm switch S2 can be achieved within the first dead time and the second dead time.

[0194] In one possible approach, see Figure 8 , the totem pole bridgeless power factor correction circuit also includes an inverter.

[0195] The output end of the comparator U2 is connected to the third end of the first slow-switching bridge arm switch S3 and the input end of the inverter respectively, and the output end of the inverter is connected to the third end of the second slow-switching bridge arm switch S4.

[0196] In this case, the output end of the comparator U2 can directly output the third control signal to the third end of the first slow switching bridge arm switch S3 and the input end of the inverter, and then the inverter outputs the corresponding electrical signal to the second slow switching bridge arm switch S4 according to the third control signal.

[0197] For example, the signal V can be directly output to the third terminal of the first slow switching bridge arm switch S3. S3 , outputs a signal V to the third terminal of the second slow switching bridge arm switch S4 S4 That is, the third control signal can be passed through the signal V S3 and signal V S4 to achieve.

[0198] In this way, precise control of the first slow-switching bridge arm switch S3 and the second slow-switching bridge arm switch S4 can be achieved.

[0199] Figure 9 This is a schematic diagram of the dead time provided in the embodiment of the present application, see Figure 9 , Figure 9Curve u in the figure represents the input voltage curve of the totem pole bridgeless power factor correction circuit over one AC power cycle. Vac represents the input voltage value, and value represents the switching cycle corresponding to the current time. On the Value axis, 0 represents the start of the AC power cycle, corresponding to time t0; 10 represents the 10th switching cycle of the AC power cycle, corresponding to time t1; q represents the last switching cycle of the AC power cycle, corresponding to time t6; q-10 represents the 10th switching cycle before the last switching cycle of the AC power cycle, corresponding to time t5; k represents the switching cycle in which a zero crossing occurs at time t3; k-10 represents the 10th switching cycle before the switching cycle in which a zero crossing occurs at time t3, corresponding to time t2; and k+10 represents the 10th switching cycle after the switching cycle in which a zero crossing occurs at time t3, corresponding to time t4. That is, times t0-t6 correspond to a complete AC power cycle. This AC power cycle contains three zero crossings, corresponding to times t0, t3, and t6.

[0200] Assume that the 10 switching cycles before any zero-crossing point is used as the first dead time, and the 10 switching cycles after any zero-crossing point is used as the second dead time. In this case, the first proportional-integral controller and / or the second proportional-integral controller determines in real time whether the switching cycle corresponding to the current phase of the input voltage vac is one of the 10 switching cycles before any zero-crossing point. For example, Figure 9 Any switching cycle between t2-t3 and t5-t6, or determine whether the switching cycle corresponding to the current phase of the input voltage vac is 10 switching cycles after any zero crossing point, for example Figure 9 Any switching cycle between t0-t1 and t3-t4. If the current switching cycle does not belong to any of the 10 switching cycles before and after the zero crossing point, for example, Figure 9 At moments t1-t2 and t4-t5, the third proportional-integral controller PI3 is used to generate a reference current amplitude as the input of the first proportional-integral controller PI1. The first proportional-integral controller PI1 then generates complementary control signals based on the reference current amplitude to control the first fast-switching bridge arm switch S1 and the second fast-switching bridge arm switch S2.

[0201] The first dead time is inserted 10 switching cycles before any zero crossing, for example Figure 9 The moments t2-t3 and t5-t6 are the first dead time, and the second dead time is inserted in 10 switching cycles after any zero crossing point. For example Figure 9The second dead time, t0-t1 and t3-t4, is used to turn off the first slow-switching arm switch S3 and the second slow-switching arm switch S4. This prevents the first slow-switching arm switch, the second slow-switching arm switch, the first fast-switching arm switch, and the second fast-switching arm switch from being turned on simultaneously, ensuring the safety of the totem pole bridgeless power factor correction circuit.

[0202] A soft start control is inserted within the first dead time. The first proportional-integral controller uses a soft start strategy based on real-time current feedback to generate complementary control signals for the first fast-switching bridge arm switch S1 and the second fast-switching bridge arm switch S2, such as the first duty cycle signal obtained by equation (1), so that the first fast-switching bridge arm switch S1 and the second fast-switching bridge arm switch S2 can achieve soft start. In this way, the duty cycle changes of the first fast-switching bridge arm switch and the second fast-switching bridge arm switch before and after the zero crossing point can be smoothed, thereby avoiding current spikes caused by sudden duty cycle changes.

[0203] During the second dead time, the output of the first proportional-integral controller is superimposed on the output of the second proportional-integral controller having a larger proportional-integral parameter to generate complementary control signals for the first fast-switching bridge arm switch S1 and the second fast-switching bridge arm switch S2. For example, the fourth duty cycle signal obtained by the second proportional-integral controller according to equation (3) above controls the first fast-switching bridge arm switch S1 and the second fast-switching bridge arm switch S2 to be activated during the second dead time. This improves the effect of current tracking voltage, specifically, strengthens current tracking during the second dead time, and thereby improves the performance of tracking the current setpoint near the zero crossing point.

[0204] In this way, the current peak at the zero-crossing point can be reduced and the smoothness of the zero-crossing point can be improved, thereby achieving the effect of reducing input current harmonics and improving power factor and efficiency.

[0205] exist Figure 9 Based on this, continue to see Figure 10 , Figure 10 It is a schematic diagram of the principle of the zero-crossing current spike suppression method provided in an embodiment of the present application. Figure 9 The time t2-t4 includes the first dead time and the second dead time, wherein t3 is the time when the input voltage crosses zero. Figure 10 China-Israel correspondence Figure 9 The following description will be made using the period from time t2 to time t4 as an example.

[0206] like Figure 10 As shown in (a), the signal V S1 is the control signal for controlling the first fast switching bridge arm switch S1, signal V S2In order to control the control signal of the second fast-switching bridge arm switch S2, between time t2 and time t3, that is, within the first dead time, the first fast-switching bridge arm switch S1 and the second fast-switching bridge arm switch S2 are soft-started by the first proportional-integral controller PI1. Between time t3 and time t4, that is, within the second dead time, the first fast-switching bridge arm switch S1 and the second fast-switching bridge arm switch S2 are controlled by the second proportional-integral controller PI2.

[0207] In addition, from Figure 10 As shown in (a), the signal V S1 and signal V S2 is a complementary control signal. And, the signal V S1 and signal V S2 The duty cycle in the first dead time is different from the duty cycle in the second dead time. Moreover, whether in the first dead time or the second dead time, the signal V S1 and signal V S2 The duty cycle of the signal V can be changed according to the above formula (1), (2) and (3). S1 and signal V S2 The duty cycle is calculated, and this embodiment of the present application does not limit this.

[0208] For example, when the signal V S1 When the signal V S2 When the signal V S1 When the signal V is low, the first fast switching bridge arm switch S1 can be disconnected. S2 When is low level, the second fast switching bridge arm switch S2 may be disconnected. Figure 10 As can be seen from (a) in FIG. 1 , the first fast-switching bridge arm switch S1 and the second fast-switching bridge arm switch S2 can be alternately turned on and off.

[0209] like Figure 10 As shown in (b), the signal V S3 is the control signal of the first slow switching bridge arm switch S3, signal V S4is the control signal for the second slow-switching bridge arm switch S4. Furthermore, before time t2, signals VS3 and VS4 are input to the first slow-switching bridge arm switch S3 and the second slow-switching bridge arm switch S4, respectively, to control the first slow-switching bridge arm switch S3 to be turned on and the second slow-switching bridge arm switch S4 to be turned off. It is not until time t4 that signals are input to control the first slow-switching bridge arm switch S3 to be turned on and the second slow-switching bridge arm switch S4 to be turned off. Therefore, between time t2 and time t4, the first slow-switching bridge arm switch S3 and the second slow-switching bridge arm switch S4 are both turned off, i.e., the first slow-switching bridge arm switch S3 and the second slow-switching bridge arm switch S4 are both turned off during the first dead time and the second dead time.

[0210] like Figure 10 As shown in (c), V ac is the curve representing the input voltage, i ac To characterize the input current curve, from V ac and i ac The curve of the input current curve intuitively shows that there is no current spike near the zero crossing point at time t3, and the input current transition is smooth near the zero crossing point at time t3. It can be seen that the zero crossing current spike suppression method provided by the embodiment of the application can reduce the zero crossing current spike and improve the smoothness of the zero crossing, thereby achieving the effect of reducing input current harmonics and improving power factor and efficiency.

[0211] The following describes the device and computer-readable storage medium used to execute the zero-crossing current spike suppression method provided by the present application. The specific implementation process and technical effects are described above and will not be repeated below.

[0212] Figure 11 This is a schematic diagram of the structure of a zero-crossing current spike suppression device provided in an embodiment of the present application, see Figure 11 , the device comprises:

[0213] The determination module 201 is configured to determine a first dead time and a second dead time according to a switching period of a pulse signal corresponding to a zero-crossing point.

[0214] The slow-switching bridge arm disconnection module 202 is configured to control the phase-locked loop to disconnect the first slow-switching bridge arm switch and the second slow-switching bridge arm switch during the first dead time and the second dead time.

[0215] The first fast-switching bridge arm control module 203 is configured to control the first fast-switching bridge arm switch and the second fast-switching bridge arm switch by using the first proportional-integral controller within the first dead time.

[0216] The second fast-switching bridge arm control module 204 is configured to control the first fast-switching bridge arm switch and the second fast-switching bridge arm switch within the second dead time by using the second proportional-integral controller.

[0217] The above-mentioned device is used to execute the method provided in the above-mentioned embodiment. Its implementation principle and technical effect are similar and will not be repeated here.

[0218] The above modules can be one or more integrated circuits configured to implement the above methods, such as one or more application-specific integrated circuits (ASICs), one or more microprocessors, or one or more field programmable gate arrays (FPGAs). For another example, when a module is implemented by scheduling program code through a processing element, the processing element can be a general-purpose processor, such as a central processing unit (CPU) or other processor that can call program code. For another example, these modules can be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0219] An embodiment of the present application further provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.

[0220] Optionally, the present application further provides a program product, such as a computer-readable storage medium, comprising a program, which is used to execute any of the above-mentioned zero-crossing current spike suppression method embodiments when executed by a processor.

[0221] In the several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interface, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0222] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0223] In addition, the functional units in various embodiments of the present invention may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or hardware plus software functional units.

[0224] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) or a processor (English: processor) to perform some steps of the methods of various embodiments of the present invention. The aforementioned storage medium includes: a USB flash drive, a mobile hard disk, a read-only memory (English: Read-Only Memory, abbreviated: ROM), a random access memory (English: Random Access Memory, abbreviated: RAM), a magnetic disk or an optical disk, and other media that can store program code.

[0225] The above are only specific embodiments of the present application, but the scope of protection of this application is not limited to them. Any changes or substitutions that can be easily conceived by any person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

[0226] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A method for suppressing a zero-crossing current spike, characterized in that: A digital controller is applied to a totem pole bridgeless power factor correction circuit, wherein the totem pole bridgeless power factor correction circuit comprises: the digital controller, a first proportional integral controller, a second proportional integral controller, a phase-locked loop, a first slow-switching bridge arm switch, a second slow-switching bridge arm switch, a first fast-switching bridge arm switch, and a second fast-switching bridge arm switch. The method comprises: Determine a first dead time and a second dead time according to the switching cycle of the pulse signal corresponding to the zero crossing point; wherein the first dead time is a plurality of switching cycles before the switching cycle of the pulse signal corresponding to the zero crossing point, and the second dead time is a plurality of switching cycles after the switching cycle of the pulse signal corresponding to the zero crossing point; Controlling the phase-locked loop to disconnect the first slow-switching bridge arm switch and the second slow-switching bridge arm switch during the first dead time and the second dead time; Controlling the first fast-switching bridge arm switch and the second fast-switching bridge arm switch by the first proportional-integral controller within the first dead time; controlling the first fast-switching bridge arm switch and the second fast-switching bridge arm switch within the second dead time by the second proportional-integral controller; The controlling the first fast-switching bridge arm switch and the second fast-switching bridge arm switch within the second dead time by the second proportional-integral controller includes: Determining the duty cycle of each switching period of the pulse signal within the second dead time by the second proportional-integral controller, and obtaining a second duty cycle signal; determining the duty cycle of each switching period of the pulse signal within the second dead time by the first proportional-integral controller, and obtaining a third duty cycle signal; Obtaining a fourth duty cycle signal according to the second duty cycle signal and the third duty cycle signal; The first fast-switching bridge arm switch and the second fast-switching bridge arm switch are controlled by the second proportional-integral controller according to the fourth duty cycle signal to start within the second dead time.

2. The method for suppressing zero-crossing current spikes according to claim 1, wherein: The determining of the first dead time and the second dead time according to the switching period of the pulse signal at which the zero crossing point is located comprises: Determining that each zero-crossing point of the input alternating current corresponds to a switching period of the pulse signal; The zero-crossing point corresponds to a plurality of switching cycles before the switching cycle of the pulse signal as the first dead time; The plurality of switching cycles after the switching cycle in which the zero-crossing point corresponds to the pulse signal is used as the second dead time.

3. The method for suppressing zero-crossing current spikes according to claim 1, wherein: The controlling the phase-locked loop to disconnect the first slow-switching bridge arm switch and the second slow-switching bridge arm switch during the first dead time and the second dead time comprises: monitoring in real time by the phase-locked loop whether the period of the pulse signal corresponding to the phase of the current input alternating current is within the first dead time or the second dead time; If so, the phase-locked loop is controlled to turn off the first slow-switching bridge arm switch and the second slow-switching bridge arm switch.

4. The method for suppressing zero-crossing current spikes according to claim 1, wherein: The controlling the first fast-switching bridge arm switch and the second fast-switching bridge arm switch by the first proportional-integral controller within the first dead time includes: Determining the duty cycle of each switching period of the pulse signal within the first dead time, and obtaining a first duty cycle signal; The first proportional-integral controller controls the first fast-switching bridge arm switch and the second fast-switching bridge arm switch to soft-start within the first dead time according to the first duty cycle signal.

5. The method for suppressing zero-crossing current spikes according to claim 4, wherein: Determining the duty cycle of each switching period of the pulse signal within the first dead time and obtaining a first duty cycle signal includes: determining a first duty cycle of the pulse signal in at least one switching cycle before the first dead time; determining a second duty cycle of the pulse signal in at least one switching period after the first dead time; The duty cycle of each switching period of the pulse signal within the first dead time is adjusted according to the first duty cycle and the second duty cycle to obtain the first duty cycle signal.

6. The method for suppressing zero-crossing current spikes according to claim 1, wherein: The step of determining the duty cycle of each switching period of the pulse signal within the second dead time by the second proportional-integral controller and obtaining a second duty cycle signal includes: Determining a current set value and a current sampling value of each switching cycle, and determining a duty cycle of each switching cycle of the pulse signal within the second dead time by the second proportional-integral controller; According to the current set value, the current sampling value, the preset proportional coefficient and the preset integral coefficient of the second proportional-integral controller, the duty cycle of each switching cycle of the pulse signal within the second dead time is calculated to obtain a second duty cycle signal.

7. A totem pole bridgeless power factor correction circuit, characterized in that: The circuit includes a digital controller, a first proportional-integral controller, a second proportional-integral controller, a third proportional-integral controller, a phase-locked loop, a first slow-switching bridge arm switch, a second slow-switching bridge arm switch, a first fast-switching bridge arm switch, a second fast-switching bridge arm switch, an amplifier, a comparator, a capacitor, an inductor, a load, and an adder; The adder is used to input the bus voltage and the reference voltage, and obtain the deviation between the bus voltage and the reference voltage; The output end of the third proportional-integral controller is connected to the first input end of the digital controller, the input end of the third proportional-integral controller is connected to the output end of the adder, the input end of the third proportional-integral controller is used to input the deviation, and the output end of the third proportional-integral controller is used to output a reference current; The first output end of the phase-locked loop is connected to the second input end of the digital controller, the third input end of the digital controller is used to input an operating voltage, the output end of the digital controller is used to be connected to the first input end of the first proportional-integral controller and the first input end of the second proportional-integral controller, respectively, the negative phase input end of the amplifier is connected to the second input end of the first proportional-integral controller and the second input end of the second proportional-integral controller, and the output ends of the first proportional-integral controller and the second proportional-integral controller are both used to output a first control signal or a second control signal for controlling the first fast-switching bridge arm switch and the second fast-switching bridge arm switch; The second output end of the phase-locked loop is connected to the non-inverting input end of the comparator, the output end of the phase-locked loop is used to output a third control signal for controlling the first slow-switching bridge arm switch and the second slow-switching bridge arm switch, and the output end of the amplifier is connected to the input end of the phase-locked loop; The positive phase input terminal of the amplifier is connected to the first end of the inductor, the second end of the inductor is connected to the first end of the first fast switching bridge arm switch and the first end of the second fast switching bridge arm switch respectively, the second end of the first fast switching bridge arm switch is connected to the first end of the first slow switching bridge arm switch, the second end of the second fast switching bridge arm switch is connected to the first end of the second slow switching bridge arm switch, the second end of the first slow switching bridge arm switch and the second end of the second slow switching bridge arm switch are both connected to the negative phase input terminal of the amplifier, the third end of the first slow switching bridge arm switch and the third end of the second slow switching bridge arm switch are used to input the third control signal, and the third end of the first fast switching bridge arm switch and the third end of the second fast switching bridge arm switch are used to input the first control signal or the second control signal; The first electrode plate of the capacitor is connected to the first end of the first fast-switching bridge arm switch, the second electrode plate of the capacitor is connected to the second end of the second fast-switching bridge arm switch, the load is connected in parallel with the capacitor, and both ends of the load are used to input the bus voltage; The digital controller is used to execute the zero-crossing current spike suppression method according to any one of claims 1 to 6.

8. The totem pole bridgeless power factor correction circuit according to claim 7, wherein: The first slow switching bridge arm switch is a first NMOS transistor, the second slow switching bridge arm switch is a second NMOS transistor, the first fast switching bridge arm switch is a third NMOS transistor, and the second fast switching bridge arm switch is a fourth NMOS transistor.

9. The totem pole bridgeless power factor correction circuit according to claim 7, wherein: The circuit further includes a driving circuit; The input end of the drive circuit is connected to the second proportional-integral controller, the first output end of the drive circuit is connected to the third end of the first fast-switching bridge arm switch, and the second output end of the drive circuit is connected to the third end of the second fast-switching bridge arm switch; The circuit further includes an inverter; The output end of the comparator is connected to the third end of the first slow-switching bridge arm switch and the input end of the inverter respectively, and the output end of the inverter is connected to the third end of the second slow-switching bridge arm switch.

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