Direct drive power control

Abstract

A power control circuit comprising a power supply and a load, the load being synthesized by an impedance synthesizer comprising two-terminal impedance elements connected in series and grouped into impedance modules. The impedance elements in each impedance module have equal values, while the impedance elements between modules have a ratio uniquely defined by the number of impedance elements in the impedance module. A plurality of switches associated with the impedance elements short-circuit a selected number of impedance elements under control of a first analog signal, which can be pre-processed by an analytic function. The analog signal is converted to a digital signal by an analog-to-digital converter, then level shifted to control the switches associated with the impedance elements, so that the amount of power delivered to the load can be controlled by the first analog signal. Pulse width modulation is deployed to further control the power by a second analog signal, with the additional benefit of overload protection.

Description

Background Technology

[0001] Related applications

[0002] This application is a continuation-in-part of International Application No. PCT / IB2013 / 058250, filed September 3, 2013, which claims priority to U.S. Provisional Application No. 61 / 696,238, filed September 3, 2012, and U.S. Provisional Application No. 61 / 734,948, filed December 7, 2012.

[0003] This application is also a continuation-in-part of U.S. Application No. 14 / 423,712 (now U.S. Patent No. 9,543,925), filed on February 25, 2015.

[0004] This application is also a continuation-in-part of Chinese application number 20138004493.9 filed on September 3, 2013;

[0005] This application also claims priority to U.S. Provisional Application No. 62 / 316,740, filed April 1, 2016; U.S. Provisional Application No. 62 / 423,763, filed November 17, 2016; and U.S. Provisional Application No. 62 / 452,900, filed January 31, 2017.

[0006] The contents of each of these applications are explicitly incorporated into this paper by reference. Invention Field

[0007] This invention generally relates to apparatus and methods for power control, and more particularly to power control for direct drive.

[0008] Description of related technologies

[0009] When electrical power, voltage, or current is applied to a load, there are essentially many key issues regarding the efficient transfer of energy from the power source to the load.

[0010] First, the voltage or current level from the power supply should be suitable for the load, as loads are typically designed to operate normally only within a certain range of voltage or current levels. Second, the characteristics of the power supply voltages that certain loads can accept should be specified, such as DC or AC, specific frequencies, and waveforms. Third, the output impedance of the power supply should be designed to handle all connected loads. Failure to meet any of these requirements may result in impaired operational performance or even destructive damage to the power supply and / or the load.

[0011] Over the decades, a wide variety of electrical and electronic systems and methods have been developed to address the aforementioned problems. These include power transformers for raising or lowering AC voltage levels, DC-DC or AC-DC converters for providing DC voltage supply, and DC-AC or AC-AC converters for providing AC voltage power, with or without frequency variations, to suit a variety of loads.

[0012] However, there exists a class of electrical or electronic devices that do not require the aforementioned conversion processes involving transformers or converters to operate normally. This is called direct drive. These devices are directly connected to the power supply without any current isolation or change in the power supply voltage characteristics. When polarity is important, a rectifier can be used to provide DC power from an AC power source without disrupting the current connection. Except for the need for a switch, the electromotive force from the power supply is applied directly to the load, and current flows directly from the power supply to the load. In other words, we define direct drive as a current connection between the load and the power supply via a switch (including a rectifier that can be considered a switch), but without any other device potentially altering the characteristics of the power supply.

[0013] The clear benefit of direct drive is the elimination of power losses introduced to facilitate current isolation, such as those through transformers and / or converters, or those typically present in switching-mode AC-DC converters. The only power loss occurs in the switching process, but this can be quite low, especially when the switching frequency is low. This translates to high overall energy efficiency. Furthermore, system costs are reduced because the need for components is significantly reduced when current isolation is not required; there is no voltage scaling, waveform or frequency conversion, etc. Often, the reactive components associated with power switching are also reduced. This means a lower likelihood of electromagnetic interference (EMI). Therefore, we can say that direct drive generally implies high efficiency, low cost, and no EMI.

[0014] However, direct drive can be risky when the stability of the power supply voltage is uncertain. This is especially true when the supply comes from the public grid. Any excessive fluctuations in the power supply voltage (even short-term) can put the load at risk of damage or malfunction. This problem can be further amplified when the load is non-linear, as exemplified by solid-state LED lamps. It is well known that for this type of device, small changes in the power supply voltage can lead to large changes in the load current, to the point that the load and / or power supply may be damaged.

[0015] Therefore, for functional requirements and system protection, controlling the method of power delivered to the load via direct drive is crucial. According to fundamental electrical principles, the power delivered to the load is proportional to the square of the voltage applied to the load divided by the load impedance; or, it is proportional to the square of the load current multiplied by the load impedance. Therefore, the total amount of power delivered to the load via direct drive can be controlled by controlling the load impedance, and / or by controlling the duty cycle of the load current through the switch operation.

[0016] To control the impedance of a load, an efficient method has been invented called a voltage-controlled impedance synthesizer, abbreviated as VCZS, as described in U.S. Patent No. 9,543,925, which is a continuation-in-part of that application. However, since synthesis is achieved through switching, the fineness of impedance control will depend on the number of switches deployed. Therefore, to achieve the desired level of fineness, the required number of switches may be excessive and practically unacceptable.

[0017] Furthermore, to achieve controlled impedance in power applications, high-voltage level floating switching is required, thus necessitating dynamic high-voltage level shifting to drive the floating switches. Additionally, due to the interaction between switches, very high dV / dt noise pulses exist not only on the power lines, which are typically directly exposed to noise. This presents a significant challenge for the design of related control circuitry, which appears to be absent in existing technologies.

[0018] In addition, to address the risk of excessive deviation in power supply voltage or load current, it is necessary to develop protection measures for the load and power supply.

[0019] Therefore, the object of the present invention is to develop an economical and efficient method for power control via direct drive, enabling efficient and reliable operation of the load device despite the aforementioned challenges. In view of the above, other advantages will become apparent to those skilled in the art to which this invention pertains, and the invention is described herein with reference to the accompanying drawings, which form a part of the invention, including a description of the invention and some typical preferred embodiments of the principles of the invention, wherein:

[0020] Figure 1 A block diagram showing the power control principle of direct drive.

[0021] Figure 2 This is a block diagram representing a voltage-controlled impedance synthesizer.

[0022] Figure 3 A block diagram illustrating how to deploy a voltage-controlled impedance synthesizer for power control via direct drive is shown.

[0023] Figure 4 A block diagram with a level shifter is shown below. Figure 3 As shown

[0024] Figure 5 A block diagram illustrating the principle of direct drive power control is shown.

[0025] Figure 6A Block diagram of a power control system based on impedance / admittance synthesis

[0026] Figure 6B Block diagram of a power control system based on impedance / admittance synthesis

[0027] Figure 7A A block diagram of a power control system with constant load current is shown.

[0028] Figure 7B A block diagram of a power control system with constant load voltage is shown.

[0029] Figure 7C A block diagram of a power control system with constant load current is shown.

[0030] Figure 8 A block diagram of a constant power control system is shown.

[0031] Figure 9 A block diagram showing the square function of power control is provided.

[0032] Figure 10 A block diagram showing another square function of power control is shown.

[0033] Figure 11 A block diagram of the multiplication function is shown.

[0034] Figure 12 A block diagram showing the division function is provided.

[0035] Figure 13A A block diagram of pulse width modulation control of the current is shown.

[0036] Figure 13B A block diagram of pulse width modulation control of the current is shown.

[0037] Figure 14 Current control curve using pulse width modulation

[0038] Figure 15 A block diagram showing the pulse width modulation control of the voltage is displayed.

[0039] Figure 16 Circuit of level shifter

[0040] Figure 17 Circuit implementation of level shifter

[0041] Figure 18refer to Figure 17 waveform

[0042] Figure 19 refer to Figure 17 The waveform contains noise current.

[0043] Figure 20 This is a block diagram of a voltage level shifter as an embodiment of the present invention.

[0044] Figure 21 This is an explanation Figure 20 Flowchart of the operation of the voltage level shifter

[0045] Figure 22 Examples of voltage offset detectors

[0046] Figure 23 Example of a discharge switch

[0047] Figure 24 This is a block diagram of another voltage level shifter as an embodiment of the present invention.

[0048] Figure 25 This is a block diagram of another voltage level shifter as an embodiment of the present invention.

[0049] Figure 26 This is a block diagram of another voltage level shifter as an embodiment of the present invention.

[0050] Figure 27 Examples of voltage-controlled current generators

[0051] Figure 28 Examples of current-controlled bleeder switches

[0052] Figure 29 The block diagram of a direct-drive power control system is shown as an embodiment of the present invention.

[0053] Figure 30 The block diagram of a direct-drive power control system is shown as an embodiment of the present invention.

[0054] Figure 31 The block diagram of a direct-drive power control system is shown as an embodiment of the present invention.

[0055] Figure 32 The block diagram of a direct-drive power control system is shown as an embodiment of the present invention. Detailed Implementation

[0056] The basic principle of this invention can be achieved through Figure 1The block diagram is used for illustration. As shown, the power supply PWRS supplies power to the power load PWLD, which is typically a load with a fixed impedance, but can also be a load with a controllable impedance, implemented by a voltage-controlled impedance synthesizer (VCZS), as depicted in U.S. Patent No. 9,543,925, of which this application is a continuation-in-part. As described below, impedance synthesis is one way to control power in a direct-drive system. It is recommended to insert a pulse-width modulation switch (PWMS) between the power supply and the load to "cut off" the current through the load. In some embodiments of the invention, such as... Figure 1 As shown, the voltage-controlled impedance synthesizer can be controlled by the analog signal ASIG, while the pulse width modulation switch is controlled by the digital signal DSIG.

[0057] As described in U.S. Patent No. 9,543,925, an impedance synthesizer provides progressively monotonically variable impedance values ​​essentially as a function of a control voltage. The synthesizer includes at least one two-terminal impedance module connected in series with multiple impedance modules; between the two terminals of each impedance module, at least one two-terminal impedance element is connected in series with multiple impedance modules; wherein all impedance elements in each impedance module have substantially the same impedance value; the impedance values ​​of the impedance elements between the impedance modules are in the following ratio: Z1:Z2:Z3:......Zm:... In ascending order, Z1:Zm = 1:Π(Ni+1) where i = 1 to m-1, Zm is the impedance value of each impedance element in the m-th impedance module, Ni is the total number of impedances in the i-th impedance module, and Π is a mathematical multiplication operator; a control device short-circuits a predetermined number of impedance elements via multiple switches according to an analog control voltage.

[0058] Figure 2 This is a block diagram illustrating the basic operating principle of an impedance synthesizer in one operating mode. As shown in the figure, impedance Z is generated under the analog control signal ASIG. VCZS For example, for an impedance value proportional to the size of the ASIG in the design, the control signal is converted into a multi-bit digital signal by an analog-to-digital converter (ADC), which then controls the switching on and off of switches inside the digital impedance synthesizer (DZS) to obtain the impedance Z. VCZS ,like Figure 3An exemplary circuit is shown. This circuit illustrates a voltage-controlled impedance synthesizer (VCZS) comprising an analog-to-digital converter (ADC) with binary digital outputs D0, D1, D2, and D3. The binary format of the digital outputs is required to drive the impedance modules shown. According to one of the many possible design configurations in U.S. Patent No. 9,543,925, each has a single impedance element Z1, Z2, and Z3 with a binary ratio. The most significant bit D0 is coupled to switch a chopper or PWM switch (PWMS), while the least significant bit D3 is coupled to switch Z3, which has the lowest impedance value among the three impedance elements Z1, Z2, and Z3. Therefore, the total load impedance presented to the power supply is Za when all four switches are closed, and infinite when all switches are open. Note that pulse width modulation is not designed in the following discussion because the switches are simply activated by the binary signal D0. When ASIG exceeds a certain value, the PWMS switch is designed to be shut down by D0 as a protection device. However, in order to achieve fine control through PWM, it will be necessary to control the switches independently, which will be discussed later.

[0059] It's also important to note that the switches are floating, meaning they each operate at voltage levels dependent on the states of other switches and the supply voltage. Therefore, the converter's ADC output may not be able to handle these varying and often very high voltage levels, such as tens or even hundreds of volts. This necessitates a dynamic level shifter, such as... Figure 4 As shown. The digital outputs D0 to D3 from the ADC are shifted from the level shifter VLSH to the corresponding digital outputs D0f to D3f, each outputting to the voltage level of the corresponding driven switch.

[0060] For loads that accept waveform-distorted current, such as some lighting or heating equipment, the timing of the load connection to the power supply can be controlled by tangency. Furthermore, tangency can be performed at frequencies substantially higher than the supply frequency, an operation often referred to as pulse-width modulation (PWM), synchronized or asynchronous with the supply voltage. For the purposes of this invention, PWM generally refers to tangency at any frequency, including frequencies substantially higher than the supply frequency, and synchronization with the supply is not required.

[0061] PWM allows for precise control of the duty cycle of the power applied to the load, which is typically not achievable through impedance synthesis alone. Therefore, by combining a voltage-controlled impedance synthesizer with phase-cutting or pulse-width modulation methods, the following objectives of this invention are achieved:

[0062] 1. Limit the power delivered to the load at high input voltages;

[0063] 2. Overvoltage protection;

[0064] 3. Overcurrent protection;

[0065] 4. Over-temperature protection;

[0066] 5. Improve the power factor of nonlinear loads;

[0067] 6. The reduction in instantaneous power at the peak of the power supply voltage balances the fluctuations in the load output, which is generally desirable, for example, in the case of lighting. This means that the flicker of the light output will therefore be reduced.

[0068] Figure 5 A simplified block diagram illustrates this combination. The power load PWLD, synthesized by VCZS, is controlled by analog signal ASIG1. The PWM switch PWMS is controlled by analog signal ASIG2 via pulse width modulation driver PWMD.

[0069] For ease of discussion, we will only examine the power control of impedance / admittance synthesis for now, leaving pulse width modulation for later discussion.

[0070] Power control using synthesized impedance / admittance can be divided into two different circuit configurations, as follows: Figure 6A and Figure 6B The block diagram is shown below. Note that for Figure 6A Impedance / admittance is controlled by a single control signal VI, which is processed by the function generator FGEN. For Figure 6B Impedance / admittance is also controlled by the control signal VI, but with an additional signal of a predetermined threshold Vth. This threshold helps to easily set the control objectives of the power control system.

[0071] refer to Figure 6A The power supply PWRS provides a power supply voltage V (and thus load voltage) or a power supply current I (and thus load current) to the load PWLD, which has an impedance or admittance ZY synthesized based on the voltage. Alternatively, it can be the current signal VI processed by the function generator FGEN. A function generator is specifically defined as a signal processing device with inputs and outputs, where the output is the actual analytical function of the input. For example, the desired function could be a scaling constant, square, or square root of the input signal VI. The signal VI can be a constant (fixed DC) or a time-varying signal, and can be an external signal or a signal from the power supply circuit, such as the load voltage or current supplied by the power supply or a controlled voltage.

[0072] refer to Figure 6B The power supply PWRS provides a power supply voltage V or a power supply current I to the load PWLD, which has an impedance or admittance ZY, synthesized based on the difference between a voltage or current signal VI and a predetermined threshold Vth. The difference is obtained by comparing the signal VI with the threshold Vth using a comparator COMP. Figure 6ASimilar to signal VI, signal VI can be a constant (fixed DC) or time-varying signal. It can be an external signal, a signal from the power supply circuit (such as the load voltage or current supplied by the power supply), or a controlled signal. Through feedback control, the impedance / admittance ZY can be driven to change in one direction to minimize the difference, that is, to make VI closer to Vth. As an application example, if VI represents the load current, then the load current is controlled to be close to the value set by Vth.

[0073] First refer to Figure 6A Use the circuit configuration to examine some illustrative circuit examples.

[0074] For the case where the function of FGEN is a scaling constant K, Table 1 summarizes the various equations related to the load voltage V and load current I. Note that for impedance / admittance modules powered by voltage or current, there are four combinations of voltage-current relationships since the impedance / admittance value is controlled by the load voltage or load current. Voltage and current are related through constants, square roots, or square functions. There is also a function that is indeterminate, meaning that a true function cannot be established.

[0075]

[0076] Table 1

[0077] Note the binary nature of the circuit topology. For each identical mathematical relation, the roles of V and I, Z and Y are interchangeable. Also note that the square and square root functions established between V and I may be deployed for power control or signal processing, as will be further illustrated with examples.

[0078] In some exemplary embodiments of the present invention, by setting the impedance of the electrical load PWLD to be proportional to the load voltage V1, the load current is controlled to be constant regardless of the power supply voltage. Figure 7A The block diagram is shown, where the function generator is labeled Kx, x is the input, K is a constant feature of the function generator FGEN, and K also depends on the design of Z1: (For simplicity, the detector of V1 is omitted in the block diagram)

[0079] Z1 = K.V1

[0080] I1=V1 / Z1=V1 / (K.V1)=1 / K is a constant

[0081] In other embodiments of the invention, when the power supply is a current source and it is desirable to maintain a constant voltage across the load regardless of the power supply current, the following can be deployed: Figure 7B The circuit configuration is shown in the figure. The inverse multiplication function K / x is deployed for the function generator FGEN:

[0082] Z1 = K / (H.I1) where H is the constant characteristic of the IDET current detector.

[0083] V1=I1.Z1=I1.K / (H.I1)=K / H is a constant.

[0084] The inverse function of multiplication can be derived from, for example: Figure 12 The circuit implementation shown will be discussed later.

[0085] By using voltage-controlled impedance / admittance, now referencing Figure 8 This describes the delivery of constant power from a voltage source, regardless of the source voltage. As shown in the figure, Z1 is the impedance of the power load, PWLD, constructed using a voltage-controlled impedance synthesizer VCZS. Now, Z1 is synthesized under the control of V1 through a function generator FGEN with a square function K.x2, i.e.

[0086] Z1 = K.V1 2 ,

[0087] Therefore, the power supply P on the load PWLD is:

[0088] P = V1 2 / Z1=V1 2 / (K.V1 2 ) = 1 / K is a constant.

[0089] The square function K·x² can be realized using the combined impedance or admittance listed in Table 1. For example... Figure 9 As shown, Y1 is the admittance generated by the voltage-controlled admittance synthesizer VCYS. Y1 will generate a current.

[0090] Note: Due to the binary characteristics of the circuit, the operation of the voltage-controlled admittance synthesizer (VCYS) can be easily derived from the operation of the voltage-controlled impedance synthesizer (VCZS). Typically, the synthesis of admittance values ​​involves the steps of connecting one or more two-terminal admittance modules in parallel; connecting one or more two-terminal admittance elements with equal admittance values ​​in parallel within each admittance module; wherein the admittance elements in all admittance modules have the same quality factor; wherein the admittance values ​​have ratios Y1:Y2:Y3:......Ym:...... in ascending order, Y1:Ym=1:Π(Ni+1) where i=1 to m-1, Ym is the admittance value of each admittance element in the m-th admittance module, Ni is the total number of admittances in the i-th admittance module, and Π is a mathematical multiplication operator; converting analog voltages into multiple digital signals; and opening multiple admittance elements by controlling multiple digital signals of multiple controllable switches associated with the admittance elements; thus, the admittance value is controlled by the analog voltage.

[0091] Note that Y1 is controlled by V1 and adjusted by a constant H, while Z1 is controlled by I2 and adjusted by a constant K. Driven by V1, VCYS transmits I2, which is proportional to the square of V1.

[0092] (Note that for simplicity, the I2 detector has been omitted from the block diagram.)

[0093] Z1 = I2.K

[0094] Y1 = V1.H

[0095] I2 = V1.Y1

[0096] Therefore, the power P of the load PWLD is:

[0097] P = V1.I1 = V1.V1 / Z1 = V1 2 / K.I2=V1 2 / (K.V1.Y1)=V1 2 / (K.V1.V1.H)=1 / (HK)

[0098] That is, P = 1 / (HK), which is a constant.

[0099] Please note that Y1 only serves a signal processing function, and therefore minimum power consumption was designed in practice.

[0100] By utilizing the binary property of circuits, a current-carrying power supply can be similarly controlled to deliver constant power. Similarly, by utilizing the binary property, a square function can be achieved using voltage-controlled impedance synthesis. This can be done through... Figure 10 The circuit configuration is used to demonstrate this. A current source provides a current I1. It can be verified that the voltage V2 across the impedance Z1 is proportional to the square of I1, making the power transferred to the load PWLD 1 / (HK), a constant.

[0101] Typically, if an external symbol V2 is used to control an admittance synthesizer powered by voltage V1, such as Figure 11 As shown in the block diagram, the multiplication function of V1 and V2 can be implemented. (See figure.)

[0102] I1 = V1.Y1

[0103] Y1 = K.V2, resulting in

[0104] I1 = K.V1.V2, meaning I1 is a function of the product of V1 and V2.

[0105] Note that in the special case where V1 remains constant, I1 is proportional to V2.

[0106] Similarly, division can be achieved by using voltage-controlled impedance synthesis, such as... Figure 12 The block diagram is shown below:

[0107] I1=V1 / Z1

[0108] Z1 = K.V2

[0109] I1 = (V1 / V2) / K, meaning I1 is a function of the quotient of V1 and V2.

[0110] Note that in the special case where V1 remains constant, I1 = H / V2 has a multiplicative inverse function relationship, that is, I1 is inversely proportional to V2.

[0111] The above discussion focused on V1 as a voltage source driving admittance or impedance. Through circuit duality, multiplication and division can also be achieved by using a current source I1 that drives the synthesized admittance / impedance. The derived equations are summarized in Table 2.

[0112]

[0113] Table 2

[0114] Note again the binary property of circuit topology. For every identical mathematical relation, the roles of V and I, Z and Y are interchangeable.

[0115] Now let's examine it. Figure 6B Some illustrative circuit examples of circuit configurations. Although Figure 7A An example of constant current control is shown, but Figure 7C Performs the same function as a constant current, but instead according to Figure 6B This is achieved through circuit configuration.

[0116] like Figure 7C As shown, the load current I1 is measured by the current detector IDET, and the output signal VI represents the current I1. VI is compared to a predetermined threshold Vth by the comparator COMP. When VI is low, the output of COMP is low, and the impedance Z1 is low. However, as the load current increases, for example due to an increase in the supply voltage and the load voltage V1, VI eventually exceeds Vth, causing the output of COMP to rise. This leads to an increase in the load impedance Z1, resulting in a decrease in the load current. Therefore, it can be seen that by forming a negative feedback loop, as long as there is sufficient loop gain, the load current I1 can remain constant even if the supply voltage changes.

[0117] Similarly, if the power measurement on the load impedance Z1 is replaced with VI, a configuration similar to [the one described above] can be deployed. Figure 7C The circuit is designed to provide constant load power.

[0118] Having discussed power control by controlling load impedance or admittance, let’s examine a power control method through direct drive, namely pulse width modulation.

[0119] If you have already referred to Figure 5 The pulse width modulation driver (PWMD) generates a switching drive signal with a duty cycle controlled by the analog signal ASIG2. For ease of discussion, we will temporarily assume the load to be one of the fixed impedances, i.e., the control signal ASIG1 of the impedance synthesizer VCZS is a constant voltage. Depending on the design purpose, ASIG2 can be a signal representing a voltage or current that needs to be monitored and / or controlled. As an exemplary embodiment of the invention, Figure 13A A block diagram of the pulse width modulation driver in the system is shown. This system enables both load current regulation and overcurrent protection through pulse width modulation.

[0120] As shown in the figure, power is supplied from the power supply PWRS to the load PWLD via a PWM switch PWMS. The load current is detected by a detector IDET with an output signal VI. PWMS, under the control of the driver PWMD, cuts off the load current based on the magnitude of VI, which represents the load current level. Signal VI is processed through two paths. One path is through a function generator FGEN and a low-pass filter LPF. Signal VI is preprocessed by the function generator using a predetermined function, such as a scaling constant, a square or logarithmic function, or any function required by the design. It is then averaged by the low-pass filter LPF to produce the average or quasi-DC value of the preprocessed signal of VI.

[0121] Another path is through comparator COMP1, which reacts only when the peak voltage of VI exceeds a predetermined threshold Vth1, immediately boosting the output of COMP1. The rising edge of the COMP1 output is coupled to trigger the pulse expander PEXT, which generates a pulse of a preset width. The pulse expander can be implemented by an edge-triggered monostable oscillator, or simply by rapidly charging but slowly discharging a capacitor.

[0122] The signals from the low-pass filter (LPF) and pulse expander are combined by an analog or circuit ANOR, whose output comparator COMP2 is compared with a second predetermined threshold Vth2. If the combined signal level exceeds Vth2, the output of comparator COMP2 will go low, thereby cutting off the PWMS switch.

[0123] For normal operation where the overcurrent condition is not reached, the COMP1 output is low because Vth1 is designed to be high enough that VI will not be exceeded. In standby mode, the COMP1 output is low.

[0124] When the load current is low, the output of VI is also lower than Vth2, the output of COMP2 is high, and the switch PWMS remains on.

[0125] When the load current increases and VI also increases, the output of LPF will exceed Vth2, causing the output of COMP2 to drop, immediately shutting off the PWMS switch. The load current drops to zero, and so does VI. However, due to the delay effect of the low-pass filter, the output voltage of LPF takes some time to drop, so the PWMS switch will remain off for a period of time until the output voltage is below Vth2, at which point the PWMS switch is turned on again. When the threshold Vth2 is exceeded again, the PWMS switch turns off again after a period of time. Thus, a relaxation oscillation is established, turning the PWMS switch on and off. As long as the supply voltage and load impedance of the PWMS remain constant, the oscillation will stabilize until the LPF output approaches Vth2. It can be seen that the load current is in the form of current pulses; the larger the load current pulse height, the lower the modulation duty cycle of the PWMS switch. The circuit then enters a current-limiting mode, where the load current is maintained at a constant average value determined by Vth2.

[0126] When the load current rises abnormally, such as when the load is short-circuited or when the power supply voltage spikes, VI rises, but the circuit characteristics of LPF will not be able to respond quickly enough to shut down the switching PWMS. This is precisely when the peak detection COMP1 comes into play. When VI exceeds Vthl, the output of COMP1 immediately rises, triggering the pulse extender PEXT. Then, the output of the analog OR circuit ANOR goes high, and the output of comparator COMP2 goes low, immediately shutting down the PWMS, and the off-time is continuously extended by the pulse extender PEXT. As a result, the on-time of the switching PWMS is very short but the off-time is long, i.e., the duty cycle of the switch is very low. Therefore, despite the very high peak current, the average load current is also very low, thus ensuring protection of the load and power supply from excessive power consumption.

[0127] In some embodiments of the present invention, the actual design of a pulse expander is as follows: Figure 13B As shown in the figure, the pulse expander is implemented by diode D1, capacitor C1, and resistor R1. When the current signal VI exceeds the threshold Vth1, the output of the first comparator COMP1 rises to a high voltage and quickly charges C1 through diode D1. The diode acts as a rectifier charger, meaning that when the output of comparator COMP1 goes low, the capacitor does not discharge in reverse to the output of comparator COMP1.

[0128] Once charging begins, the high voltage on C1 reduces the output of comparator COMP2, thus turning off the PWMS switch. The current signal VI immediately becomes zero, reducing the output of comparator COMP1. However, this has no effect on the capacitor voltage where diode D1 is located, as diode D1 is now reverse biased. Instead, the capacitor discharges through resistor R1 for a period of time until the voltage across the capacitor falls below the second threshold voltage Vth2, and when the output of comparator COMP2 rises, the PWMS switch turns on again. By appropriately selecting the values ​​of C1 and R1, a predetermined time period for turning off the PWMS switch is achieved, which is the preset pulse width of the pulse extender PEXT.

[0129] Note that by using diode D1, the outputs from comparator COMP1 and low-pass filter LPF are effectively coupled together via an analog-OR function. Therefore, when VI is low and before exceeding the first threshold Vth1, the output of LPF fully functions in the control loop of pulse width modulation of the load current.

[0130] It should also be noted that capacitor C1 and resistor R1 can actually be designed into the low-pass filter LPF. In fact, they can be the Thevenin equivalent capacitance and resistance at the output of the low-pass filter LPF.

[0131] The performance of this current control and overcurrent protection scheme can be achieved through... Figure 14 The graph further illustrates this. The X-axis represents the peak amplitude of the load current Ipk, while the Y-axis represents the switching duty cycle DTCC of the PWMS switch. At low peak load currents, the PWMS duty cycle is set to d1 = 100%, meaning the PWMS is continuously on along curve a. When the load current rises to I1, relaxation oscillation begins at a predetermined value (threshold Vth2), and the DTCC decreases as the peak load current increases. The circuit then enters current-limiting mode along curve b. When the peak load current reaches a predetermined value (threshold Vth1) I2, peak detection COMP1 is activated, causing the DTCC to rapidly decrease from d2 to a very low value (d3), entering overcurrent protection mode along curve c.

[0132] It is evident from the above discussion that the threshold Vth1 needs to be higher than the threshold Vth2.

[0133] While the circuit techniques described above are applied to current control, the same principles apply to voltage control, as in some embodiments of this invention. This is due to... Figure 15 The circuit diagram illustrates that the voltage across the load PWLD is detected as a voltage signal VV by a voltage detector VDET. Except for the scaling difference (not shown), VV is applied in a manner similar to VI in a circuit used for current control, as... Figure 13AAs shown. Voltage control and overvoltage protection are implemented in a similar manner to current control and overcurrent protection.

[0134] In other embodiments of the invention, the power of the load is measured as a signal controlling the pulse width modulation driver (PWMD). The power is then limited to a level predetermined by a threshold Vth2, and overcurrent protection is applied when the load power exceeds a value predetermined by a threshold Vth1.

[0135] A technique for dynamic level shifting is now proposed.

[0136] In high-voltage drives, level shifting is deployed so that the high-side circuitry can be controlled by control signals from the low side. A cost-effective method for signal transmission from the low side to the high side is to use a current link between the two sides, with the current generated by a voltage-controlled current generator on the low side. The current can then be further converted to voltage using a current-to-voltage converter to drive the high-side circuitry.

[0137] Although the following discussion concerns level shifting in the common direction from the low-voltage side to the high-voltage side, the reverse, i.e. from the high side to the low side, is equally feasible.

[0138] For digital control signals, another method of level shifting is through signal coupling via a capacitor between the low and high sides. In response to a digital control signal from the low side, a latch on the high side is triggered to switch. One advantage of this method is that power consumption occurs only for the brief period of time during which the latch is triggered to change state. However, the latch may be susceptible to false triggering in noisy environments, such as when a sudden change in high voltage occurs in the associated circuit network.

[0139] High-voltage level shifting is typically used to control the power switch via digital control signals from the low-voltage side. Figure 16 A simplified circuit diagram of this arrangement is shown. The shift circuit shown consists of two parts: a low-side LVS and a high-side HVS. The signal to be shifted, Sigin, is connected to the gate of transistor Q1, which acts as a current source to deliver current to the high-side resistive load R1. Similarly, an inverted Sigin signal output from the inverter gate GIN is applied to drive a second transistor Q2 to deliver another current to the second resistive load R2. Thus, two complementary signals, Sigh1 and Sigh2, are generated on the high side synchronously with the low-side signal Sigin. These two complementary signals are used to drive the SR latch LATC to provide Sigout as the output signal of the voltage level shifter.

[0140] Sigout is typically used to drive the high-side power switch (not shown). Alternatively, to reduce power consumption, a latch can be triggered to change its state via a narrow pulse from the low side. This can be achieved by driving level-shifting transistors Q1 and Q2 with pulses derived from the input signal Sigin at their positive and negative edges, respectively.

[0141] like Figure 16 As shown, the digital filter DFIL is located before the SR latch LATC. This is a common practice in the prior art, enabling digital filters to remove common-mode noise that may have been introduced into the circuit network.

[0142] When the high voltage is switched on and off, the sudden change in voltage, expressed at a very high voltage slew rate as dV / dt, will be due to the presence of parasitic capacitances (e.g., as shown in the image). Figure 16 The high common-mode noise current spikes (CS1 and CS2 associated with switching devices Q1 and Q2) caused by these spikes can corrupt signals and potentially render control circuits inoperable when coupled to them. To address this issue, various solutions have been devised in the prior art, such as the solution disclosed in patent US8957721, which deploys a differential comparator with a high common-mode rejection ratio, and patent US7495482, which deploys a digital filter to eliminate noise caused by high-voltage fluctuations.

[0143] However, high noise current spikes coupled to semiconductor switching devices such as BJTs or MOSFETs can overdrive the devices to deep saturation, resulting in a considerable time required for subsequent state changes based on control signals. Neither analog nor digital filters can solve the problems caused by overdriven switching devices, thus limiting switching speed. Therefore, the object of this invention is to eliminate the adverse effects of noise current spikes caused by high-voltage offsets.

[0144] Figure 17 This is a simplified diagram of the basic circuit used in a preferred embodiment of the invention. The low-side transistor Q1 and resistor R1 form a current generator controllable by the input signal Sigin. Current from the drain electrode flows through resistor R2 on the high-side, generating a voltage signal Sigout that drives transistor Q2. The source of transistor Q2 is connected to the high-voltage power supply HV via resistor R2. In other words, the signal Sigin, as Sigout, is shifted from the low-voltage side to the high-voltage side via a voltage level shifter VLS. As an example application, Sigout is coupled to drive a power switch formed by transistor Q2. Therefore, Sigin controls the high-side switch to deliver current Io through load R3.

[0145] Figure 17The circuit diagram also shows capacitor CS1, a parasitic capacitor of Q1 located between the source and drain. Although typically small in capacitance, this capacitor is subjected to a high voltage HV from the high-voltage side HVS. For any reason, a sudden change in high voltage can cause a high current to flow to charge or discharge the capacitor, resulting in noise current spikes that interfere with the operation of the current generator formed by Q1 and R1. Furthermore, a large current spike through resistor R2 implies a large voltage spike coupled to transistor Q2. Therefore, the transistor may be overdriven due to spike oversaturation. More details on the effects follow.

[0146] Figure 18 The various waveforms involved in the operation are shown. Curve a) is the high-voltage power supply HV, which is noiseless but varies at low frequencies and is typically used in rectified power supplies. Curve b) is the input control signal Sigin, which is actually shifted to the high-voltage side as Sigout. Curve c) shows the output current Io. Curve d) is cleanly cut off according to the control signal Sigin.

[0147] Figure 19 The same situation is shown, but noise problems are caused by voltage spikes carried by the supply voltage. For example... Figure 17 The parasitic capacitor CS1 and resistor R2 connected in series can be considered as a differentiating circuit. If there is any rapid change in the supply voltage HV, the voltage shift is differentiated to provide a large current and thus generate a large voltage spike across resistor R2. A spike of either polarity, depending on the polarity of dV / dt, will be added to the signal Sigout, which is thus disrupted, as shown by curve c).

[0148] like Figure 19 As shown, curve a) of voltage HV contains noise pulses labeled 1 to 4, where pulses 1 to 3 are positive pulses and pulse 4 is a negative pulse. Due to noise pulse 1, Sigout, as shown in curve c), is disrupted by two noise spikes corresponding to the positive and negative edges of the pulse. Since Sigin is high at this time, only the negative spike has a real effect on Sigout, causing Io to decrease incorrectly, as shown in curve d). For pulse 2, the first positive spike is added to high Vigout, while the negative spike is added to low Sigout. Neither has any effect on Io. For pulse 3, only the positive peak incorrectly turns on Io when Sigin is low, while the negative spike has no effect. For pulse 4, which is a negative pulse, the first negative spike turns off Io when it should be on, while the second spike is positive, turning on Io when it should be off without such a noise pulse.

[0149] The conclusion drawn from the above observations is that rapid shifts in the power supply voltage cause noise voltage spikes on the level-shifted signal, the effect of which depends on the polarity of the shift relative to the signal state. The resulting current pulses are typically very large, rendering traditional filtering or compensation methods ineffective. An alternative approach is necessary.

[0150] As one of the preferred embodiments of the present invention, the voltage level shifter includes a voltage-controlled current generator operating at a first voltage level and an input line coupled to receive an input signal to be shifted; a current-to-voltage converter operating at a second voltage level and an output signal coupled to an output line; wherein a current output from the current generator is coupled to the input of the voltage converter; and a discharge device for eliminating noise current spikes caused by voltage offset between the first and second voltage levels; thus, the output signal substantially replicates the input signal without being affected by noise current spikes.

[0151] With the help of Figure 20 The block diagram illustrates the operating principle of a preferred embodiment of the present invention. The three parts of the network shown—the low-voltage side LVS and the high-voltage side HVS—together form a voltage level shifter, while the high-voltage network HVN is an application example of the shifter. The signal labeled Sigin is the input signal, while Sigout is the output signal of the level shifter.

[0152] If you have already referred to Figure 17 As explained in the circuit diagram, the basic components of a level shifter are a voltage-controlled current generator (VIG) and a current-to-voltage converter (IVC) controlled by the input signal Sigin at a low voltage level. The IVC can be simply a resistor whose voltage drop is the high-voltage signal output Sigout. The problem primarily stems from the parasitic capacitor Cs connected in parallel with the current generator VIG.

[0153] Two bleeder switches are used to eliminate positive and negative noise current spikes when the current generator is turned off and on respectively.

[0154] When the current generator is off, i.e., when Sigin is low, its inverted signal through the inverter gate GIN prepares the positive voltage offset detector PVD to detect a positive voltage offset or +dV / dt of the high-voltage power supply HV. Once a positive offset at a predetermined rate is detected, a pulse of sufficient width is generated to turn on the forward discharge switch BSP, thereby short-circuiting the voltage converter IVC during the pulse period. At this time, the induced current through the parasitic capacitor Cs is diverted away from the voltage converter. When Sigin is low, Sigout remains low.

[0155] When the current generator is on, i.e., when Sigin is high, the negative voltage offset detector NVD is ready to detect a negative voltage offset or -dV / dt of the high-voltage power supply HV. Once a negative offset at a predetermined rate is detected, a pulse of sufficient width is generated to turn on the negative discharge switch BSN, thereby short-circuiting the current generator VIG during the pulse period. At this time, the charge in the parasitic capacitor Cs is rapidly discharged by the switch, preventing the voltage converter IVC from discharging when HV is lower than the voltage of Cs. With Sigin constant, Sigout remains high.

[0156] It is important to ensure that the discharge time is long enough to cover induced noise current spikes. To ensure this, the voltage offset detector should be designed to provide an output pulse of sufficient width to control the discharge for a sufficiently long time. Furthermore, the voltage offset detector is shown connected between the high-voltage (HV) and ground, rather than between HV and any other voltage source on the low-voltage side, which is typically more regulated in actual circuits, and any fluctuations therein are much smaller compared to the high-voltage (HV). Therefore, detecting the voltage offset of the high-voltage (HV) relative to ground is virtually the same as detecting the offset of the high-voltage (HV) by referencing any other voltage on the low-voltage side.

[0157] Using the discharge action described above, in response to the high voltage shift between the two voltage levels, Sigout follows Sigin via a voltage level shifter, unaffected by noise current spikes caused by the voltage shift.

[0158] The operating sequence of the above level shifters can also be achieved through... Figure 21 The flowchart below illustrates this circuit. It begins by closing the discharge switches BSP and BSN (indicated by the down arrow), and the input signal Sigin is tested to be either high or low. If Sigin is low, switch BSP will open (up arrow) once +dV / dt is detected. If Sigin is high, switch BSN will open once -dV / dt is detected. Sigout clears the corrupted output. BSP and BSN then close to prepare for the next round of discharge.

[0159] In order to achieve, Figure 22Possible voltage offset detector circuits deployed in some embodiments of the invention are shown. Circuit a) is a CR differentiator output controlled by an NPN transistor switch, and circuit b) is also a CR differentiator, with the capacitor being a parasitic capacitor of the NPN transistor (not shown). However, its control is via a PNP transistor, requiring a control signal of reverse polarity compared to circuit a). Circuit c) uses a PNP transistor instead of the required capacitor. Circuit d) uses two MOSFETs, one for the capacitor and the other for control. It should be understood that for circuits a) through d) above, the output from the voltage offset detector is pulse-shaped, in addition to the value of CR, the slew rate, and the amplitude of the noise pulse at the input. A higher slew rate results in a larger output pulse amplitude. A larger noise pulse amplitude results in a wider output pulse width. Therefore, a separate timer can be designed to drive the bleed switch for a sufficiently long time in a particular design case. Circuit e) can be used for this purpose as shown, with a monostable multivibrator triggered by the differentiator output. Thus, by designing and selecting a monostable multivibrator, the output of the voltage offset detector is a pulse of a predetermined width.

[0160] Figure 23 A practical switching device for current discharge is shown. Device a) is an NPN transistor, device b) is a PNP transistor, device c) is an N-MOSFET, and device d) is a P-MOSFET.

[0161] In another preferred embodiment of the present invention, a voltage level shifter is provided for level shifting between two voltage levels, comprising: an input terminal for receiving a signal at a reference low voltage level; an inverter converting the signal into signal 2; current sources 1 and 2, each controllable by signal 1; current source 3, controllable by signal 2; a switch 1 connected between the high voltage level and current source 3, controllable by current source 1; a switch 2 connected between the high voltage level and current source 2, controllable by current source 3; and an output terminal coupled to receive two current sources as output current; thereby, the output current is controlled by signal 1.

[0162] With the help of Figure 24 The block diagram illustrates the operating principle of this preferred embodiment of the invention. Three circuit networks are shown: the low-voltage side LVS and the high-voltage side HVS together form the voltage. A level shifter is also shown, with the high-voltage network HVN illustrating an application example of the shifter. The signal Sigin is the input signal, and Iout is the output signal of the level shifter.

[0163] If you have already referred to Figure 17As explained in the circuit diagram, the basic element of a level shifter is a voltage-controlled current generator controlled by the input signal Sigin at a low voltage level. Current from the current generator passes through a resistor on the high-voltage side to generate a voltage signal Sigout, which is used as the output signal of the level shifter at a high voltage level. However, if the level shifter is used for a current-driven device, the output of the level shifter needs to be in the form of a current Iout. However, the problem of parasitic capacitance in parallel with the current generator VIG still exists.

[0164] refer to Figure 24 The level shift is performed from the low-voltage side LVS to the high-voltage side HVS, relative to ground GND and the high-voltage power supply HV, respectively. For ease of explanation, it is assumed that HV has a positive high-voltage power supply, but this is usually not necessary, as long as the correct polarity type of components is deployed for the relevant circuit network.

[0165] The input to the level shifter circuit is Sigin, a two-level digital signal, and the output is Iout, whose waveform will be the same as Sigin's waveform but at the high voltage level (HV). As an example application, Iout is used to drive a current-driven power switch (PSW), such as... Figure 24 The PNP power supply BJT shown is connected to the power load PWLD and draws current Io from the high-voltage power supply HV.

[0166] As shown in the low-voltage side LVS diagram, the input signal Sigin is coupled to directly drive two current generators, VIG1 and VIG2. Sigin is also inverted and coupled by the inverter gate GIN to drive a third current generator, VIG3. For the actual implementation of the current generators, please refer to [reference needed]. Figure 27 The example shown. In practice, since both VIG1 and VIG2 are driven by the same input signal Sigin, they can be combined into a single current generator output, which is then split into two currents, I1 and I2, through appropriate circuitry.

[0167] On the high-voltage side HVS, the output terminal is connected to the output of current generator VIG2. Switch SW3 is coupled between the high-voltage level HV and the output terminal, and it can be turned on under the control of current generator VIG3 to short-circuit the output to the high-voltage level HV. However, the current from VIG3 can be bypassed by switch SW1, which is itself controlled by the current from VIG1. For the actual implementation of the current-driven switch, please refer to [reference needed]. Figure 28 The example shown.

[0168] Now let's explain how the level shifting circuit works. For example... Figure 24As shown, when Sigin is low, VIG1 and VIG2 are deactivated, so currents I1 and I2 are zero. Simultaneously, VIG3 is activated and current I3 is turned on. Since I1 is zero, SW1 is turned on, allowing I3 to activate SW3, causing SW3 to close and short-circuiting the output to the high voltage level HV. Therefore, the output current Iout is zero. Even if any noise pulses are present on HV, Iout remains zero due to the short circuit of SW3.

[0169] When the input Sigin goes high, VIG1 and VIG2 are activated, thus currents I1 and I2 conduct. Simultaneously, VIG3 is deactivated, and current I3 becomes zero. Since I1 is on, SW1 is closed, preventing I3 from activating SW3, thus opening SW3. Currently, I2 flows to the output as Iout.

[0170] When HV changes very abruptly, induced noise pulses will couple to the output current Iout. The pulse width of these noise pulses is determined by a time constant proportional to the product of the stray capacitance on VIG2 and the output resistance of the level shifter, in which case the input resistance of the switch PSW is... Figure 2 The value is marked as RB. 24. If the resistance is low enough, the time constant will be very low for the BJT as a power switch PSW, and the noise pulse will have a very narrow width.

[0171] Therefore, the power switch PWS may not respond to such short pulses that depend on the signal current Iout, thus protecting the level shifter from dV / dt noise.

[0172] In another preferred embodiment of the invention, a voltage level shifter is provided for level switching between two voltage levels, comprising: two current sources from a low voltage level, each controlled by signal 1 and its inverted signal 2; a voltage limiting device coupled between a first current source and a high voltage level; a capacitor, the first terminal of which is coupled to a common node of the first current source and the voltage limiting device via a rectifier, and the second terminal of which is coupled to the high voltage level; and a discharge device coupled in parallel with the capacitor, the discharge device being controllable by a second current source; wherein the first current source is configured to charge the capacitor via a rectifier, and the second current source is configured to drive the discharge device to discharge the capacitor; thereby, the voltage across the capacitor is controlled by signal 1.

[0173] In this configuration, the relatively large input capacitance of the power MOSPET's gate is utilized for level shifting. In short, the capacitor is rapidly charged and discharged in sync with the input control signal Sigin. A specific arrangement is made where the charging current is rectified, i.e., discharge along the charging path is prevented, thus shielding the level shifter's output signal from noise pulses on the high-voltage power supply HV.

[0174] Reference Figure 25 The block diagram shows that the digital signal Sigin, which needs to be level-shifted, is applied to the first current generator VIG1, while the inverted signal, obtained through the operation of the inverter gate GIN, is applied to the second current generator VIG2. For the actual implementation of the current generators, please refer to [reference needed]. Figure 27 The example shown.

[0175] When Sigin is high, current I1 is generated by VIG1 and passed to voltage limiting device DZ, which in this case is a Zener diode DZ with a predetermined rated voltage. Therefore, a voltage equal to the rated value is established across the Zener diode. Simultaneously, because the inverted Sigin control input applied to VIG2 is low, the current I2 from VIG2 is zero. When I2 is zero, the discharge switch SW2, connected in parallel with capacitor CG, is open. The capacitor is rapidly charged to a value equal to the voltage across Zener diode DZ minus the voltage drop across diode DR, formed, for example, by a voltage buffer VBUF and a rectifier diode DR cascaded in series as shown. The charging state is maintained as long as the input Sigin remains high.

[0176] When Sigin goes low, I1 drops to zero, and the voltage across Zener diode DZ also drops, causing rectifier diode DR to be reverse biased. On the other hand, VIG2 is enabled to generate current I2, which turns on switch SW2 and short-circuits capacitor CG, causing the capacitor to discharge rapidly to zero voltage.

[0177] Therefore, the voltage across capacitor CG, i.e., the output of level shifter Sigout relative to the high-voltage power supply HV, is synchronously controlled by Sigin. For example... Figure 25 As shown, as an application example, Sigout can be coupled to a power switch PSW driven by a drive voltage, such as a P-channel MOSFET, to turn on the power supply load PWLD and draw current Io from the high-voltage power supply HV.

[0178] When Sigin is at a high current and current I1 is conducting, capacitor CG is charged to the voltage limited by diode DZ. If HV changes abruptly at that time, the presence of stray capacitance (not shown) in parallel with VIG1 will cause a noise current pulse. The current pulse can be added to or subtracted from current I1 depending on the direction of the change in voltage HV. Due to the characteristics of the Zener diode, an increase in current will not raise the voltage across diode DZ too much. On the other hand, reducing the current to a sufficiently low value, or even to a negative value, will cause the voltage across DZ to fall below the nominal Zener voltage. However, the rectifier charger prevents capacitor CG from discharging through the charging path, so the voltage across capacitor CG remains completely unaffected. Sigout remains high.

[0179] When Sigin is at a low current and current I1 is off, capacitor CG discharges to zero voltage through switch SW3. If HV changes suddenly at that time, the presence of stray capacitance in parallel with VIG1 will cause a noise current pulse. However, since SW3 is closed, any possible induced current flowing through diode DR will be bypassed by SW3 and will not charge capacitor CG. Sigout remains low.

[0180] Can be deployed as Figure 25 The exemplary circuit shown is for driving a P-channel MOSFET. For an N-channel MOSFET, a gate signal with opposite polarity is required, and can be generated by, for example... Figure 26 The modified circuit shown provides the following. As shown, a floating bias voltage VB is connected to the low side of the switch PSW, which is the source of the N-channel MOSFET. VB is selected so that its voltage is close to the Zener voltage of DZ. Therefore, the gate signal is equal to the voltage of VB minus the voltage across capacitor CG. As the voltage across CG switches between zero and the Zener voltage of DZ, the gate voltage switches between VB and zero.

[0181] For the actual implementation of level shifting circuits Figure 27 Examples of current generators used for voltage control are shown. In each circuit diagram a), b), and c), the generated current I1 is approximately equal to the voltage of the control signal Sigin (minus the base-emitter voltage) divided by the value of resistors R1, R2, or R3. Specifically, in circuit b), capacitor C1 helps to boost the output current at the rising edge of the current, thereby accelerating the rising and falling transitions of the level shifter output Sigout or Iout.

[0182] Examples of circuits for current-controlled switches include... Figure 28 As shown. In circuit a), the input current I1 turns on transistor T1, which acts as a switch. Similarly, in circuit b), a MOSFET is used instead of a switch. The gate voltage required to drive the MOSFET is obtained through the voltage drop across resistor R2 caused by the current I1.

[0183] By implementing the key components discussed, we can now examine some exemplary embodiments of the invention for power control via direct drive.

[0184] Figure 29 This is a block diagram of a power control system as an embodiment of the present invention, showing the key components therein:

[0185] As an electrical energy source, a power supply PWRS is typically characterized by its electromotive force, internal impedance, waveform, and frequency.

[0186] For general discussion, the power supply is not limited to AC or DC. Power supply control systems are, in principle, capable of handling both AC and DC power supplies. However, when rectifiers are present, it is assumed the power supply is AC, and for normal load operation, DC power may or may not be filtered. Furthermore, when deploying a resonant network, it should be assumed the power supply is AC and has a fixed dominant frequency. Additionally, unless otherwise stated, the power supply is a voltage source with negligible internal impedance. However, if it is a current source, for ease of discussion, its internal impedance can be assumed to be infinite.

[0187] The reactive (inductor-capacitor or LC) network LCNW provides power factor correction, power limiting, and / or EMI filtering. It is worth noting that by making the LC network resonate at the supply frequency, a high-impedance power supply is formed, and in some embodiments of the invention, it will be used for direct drive.

[0188] The rectifier RECT converts AC power supply voltage to DC voltage for control of general power electronic devices;

[0189] The load PWLD, whose impedance (or admittance) is synthesized by a voltage-controlled impedance synthesizer (VCZS), is coupled to the rectifier via a PWM (pulse width modulation) switch (PWMS); in some embodiments of the invention, such as Figure 29 As shown, the impedance of the load PWLD is controlled by the power supply voltage of the RECT rectifier.

[0190] The pulse width modulation driver PWMD responds to the output of the current detector IDET, where IDET is the current flowing through the load PWLD;

[0191] Under the control of voltage detector VDET, the impedance of load PWLD can be controlled according to the power supply voltage. In some embodiments of the invention, the impedance is controlled proportionally to the instantaneous value of the power supply voltage, resulting in a constant current through the load, independent of the magnitude of the power supply voltage. In some other embodiments of the invention, the impedance is controlled to be proportional to the square of the instantaneous value of the power supply voltage, resulting in a constant load power, independent of the magnitude of the power supply voltage.

[0192] Under the control of the driver PWMD, the duty cycle of the PWM switch PWMS can be modulated to control the current through the load PWLD. In some embodiments of the present invention, and through the design of the driver PWMD, the current can be kept constant within a predetermined range, and the current can be cut off for protection when a predetermined threshold is exceeded.

[0193] Note that under the control of the voltage-controlled impedance synthesizer VCZS, the load PWLD can be considered as a single element with an impedance of variable value ZVCZS. Furthermore, the PWM switch PWMS further modulates the impedance. Assuming the duty cycle of the PWM switch is DTCC, and ignoring the impedance of the reactive network LCNW and the rectifier RECT, the load impedance seen from the power supply side is ZVCZS / DTCC.

[0194] Figure 30 The operating principle of an exemplary embodiment of the present invention is illustrated, wherein the load is driven by a constant current, independent of changes in the supply voltage. As shown in the block diagram, the load current is detected by an IDET, whose output is coupled to a predetermined reference IREF to a PWM driver PWMD. By controlling the duty cycle of the on-time of the switch PWMS, the load current is controlled to be equal to IREF, independent of the supply voltage.

[0195] Figure 31 The operating principle of another exemplary embodiment of the invention is illustrated, wherein the power supply load PWLD is driven by the power supply current. The reactive network LCNW essentially consists of at least one capacitor and one inductor connected to resonate at the power supply frequency. At resonance, this reactive network presents a very high impedance to the rectifier RECT and the load PWLD (theoretically infinite under the condition of lossless resonant capacitor C1 and lossless resonant inductor L1). Therefore, the power supply PWRS, together with the reactive network, can be considered as a current source supplying current to the load PWLD, having an effective impedance at the input of the rectifier. However, through the tangential operation of the PWM switch PWMS controlled by the driver PWMD, the voltage across the rectifier output is forced to follow a fixed voltage reference VREF. Therefore, by selecting the reference VREF, the load PWLD can operate at voltages lower or higher than the power supply voltage. In effect, the reactive network is loaded by a “constant voltage load,” i.e., a circuit with “Zener diode” characteristics, where the constant voltage device is driven by a constant current. Therefore, with a constant current from the reactive network and a fixed voltage at the rectifier input, the power delivered to the load PWLD through the rectifier remains constant regardless of the impedance characteristics of the load PWLD.

[0196] As mentioned earlier, a rectifier (RECT) is used to convert the AC supply voltage to DC voltage for ease of control of general-purpose power electronic devices, since most of these devices operate at a single voltage. However, for high-power operation, the rectifier dissipates a considerable amount of energy due to its ohmic drop. Therefore, in some embodiments of the invention, the AC current is directly controlled without rectifying the AC voltage from the AC supply ACPS. The PWM switch (PWMS) needs to be capable of AC operation. Similar to performing... Figure 30 The circuit shown has a constant current function; the AC version is in... Figure 32As shown, an AC switching PWMS can be implemented using a pair of MOSFETs connected in anti-series. However, the load PWLD also needs to operate under AC voltage.

[0197] Although the invention and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the invention as described. For example, a particular transistor implementation of the circuit of the invention may differ from the examples provided herein, while still remaining within the scope of the invention. As some further examples, the specified direction of current, the polarity of voltage can be reversed, and the source and drain of a MOS transistor or the emitter and collector of a BJT can be interchanged. Through the duality of the circuit, the actions of current and voltage, impedance and admittance, inductance and capacitance, etc., can be interchanged. Essentially, the discussions contained herein are intended to serve as a basic description. It should be understood that the specific discussions may not explicitly describe all possible embodiments; many alternatives are implicit, and it may also not fully explain the general nature of the invention, and may not explicitly show how each feature or element can actually represent a broader function or multiple alternatives or equivalent elements. Likewise, these are implicitly included in this disclosure. In the case of the invention being described in device-oriented terms, each element of the device implicitly performs a function. Neither the description nor the terminology is intended to limit the scope of the invention.

Claims

1. A circuit suitable for performing arithmetic operations, wherein the arithmetic operations include multiplication, division, square root, or square, comprising: A three-terminal circuit element having a driving terminal, a control terminal, and a common terminal, wherein: The circuit element has an impedance or admittance characteristic parameter between the driver and the common terminal, which is selected to be proportional to a variable control signal applied to the control terminal. The circuit element is coupled to receive a variable drive signal between a drive and a common terminal, the drive signal being selectable from a variable voltage source or a variable current source, resulting in a complementary current or voltage response of the circuit element. A measuring device is used to determine the current or voltage response of a circuit element to a selected drive signal, wherein the current or voltage response is the result of an arithmetic operation between a control signal and a drive signal, the arithmetic operation being predefined based on the choice between the characteristic impedance or admittance of the circuit element and the choice between a variable voltage source or a variable current source of the drive signal.

2. The circuit according to claim 1, wherein: Select a current source to provide the drive signal; Select the characteristic impedance for circuit elements; Therefore, the voltage response of the measured circuit element is proportional to the product of the drive signal and the control signal.

3. The circuit according to claim 1, wherein: Select a voltage source to provide the drive signal; Select characteristic admittances for circuit elements; Therefore, the current response of the measured circuit element is proportional to the product of the drive signal and the control signal.

4. The circuit according to claim 1, wherein: Select a current source to provide the drive signal; Select characteristic admittances for circuit elements; This allows us to measure the voltage response of circuit elements, which is proportional to the quotient of the drive signal and the control signal.

5. The circuit according to claim 1, wherein: Select a voltage source to provide the drive signal; Select the characteristic impedance for circuit elements; This allows us to measure the current response of the circuit elements, which is proportional to the quotient of the drive signal and the control signal.

6. The circuit according to claim 1, wherein: Select a voltage source to provide the drive signal; The control signal is the current response of a circuit element to a drive signal; Select the characteristic impedance for circuit elements; Thus, the current response of the measured circuit element is proportional to the square root of the driving signal.

7. The circuit according to claim 1, wherein: Select a current source to provide the drive signal; The control signal is the voltage response of a circuit element to a drive signal; Select characteristic admittances for circuit elements; Thus, the voltage response of the measured circuit element is proportional to the square root of the driving signal.

8. The circuit according to claim 1, wherein: Select a voltage source to provide the drive signal; The control signal is a drive signal; Select characteristic admittances for circuit elements; Thus, the current response of the measured circuit element is proportional to the square of the driving signal.

9. The circuit according to claim 1, wherein: Select a current source to provide the drive signal; The control signal is a drive signal; Select the characteristic impedance for circuit elements; Thus, the voltage response of the measured circuit element is proportional to the square of the driving signal.

10. The circuit according to any one of claims 1 to 9, wherein, The circuit element includes an analog-to-digital converter with an input and an output, the input being coupled to receive the control signal and the output being coupled to drive the switching of a plurality of controllable digital impedance or admittance synthesizers, wherein the synthesized impedance or admittance is the impedance or admittance of the circuit element.

11. The circuit of claim 10, wherein the circuit element further comprises a function generator coupled to preprocess the control signal with a predetermined function before it is input to the analog-to-digital converter.

12. An arithmetic operation method, wherein the arithmetic operation includes multiplication, division, square root, or square, comprising the following steps: Construct a three-terminal circuit element with a driving terminal, a control terminal, and a common terminal, wherein the circuit element has a characteristic impedance or admittance parameter between the driving terminal and the common terminal, and the characteristic impedance or admittance is selected to be proportional to the variable control signal. A variable drive signal is coupled to a circuit element between the drive and a common terminal. The drive signal can be selected from a variable voltage source or a variable current source, resulting in a complementary current or voltage response of the circuit element. Couple the control signal to the control terminal; Determine the current or voltage response of the circuit element to the selected drive signal, wherein the current or voltage response is the result of an arithmetic operation between the control signal and the drive signal, which is predefined based on the choice between the characteristic impedance or admittance of the circuit element and the choice between the variable voltage source or the variable current source of the drive signal.

13. The method according to claim 12, wherein: Select a current source to provide the drive signal; Select the characteristic impedance for circuit elements; Therefore, the voltage response of the measured circuit element is proportional to the product of the drive signal and the control signal.

14. The method according to claim 12, wherein: Select a voltage source to provide the drive signal; Select characteristic admittances for circuit elements; Therefore, the current response of the measured circuit element is proportional to the product of the drive signal and the control signal.

15. The method according to claim 12, wherein: Select a current source to provide the drive signal; Select characteristic admittances for circuit elements; This allows us to measure the voltage response of circuit elements, which is proportional to the quotient of the drive signal and the control signal.

16. The method of claim 12, wherein: Select a voltage source to provide the drive signal; Select the characteristic impedance for circuit elements; This allows us to measure the current response of the circuit elements, which is proportional to the quotient of the drive signal and the control signal.

17. The method according to claim 12, wherein: Select a voltage source to provide the drive signal; The control signal is the current response of a circuit element to a drive signal; Select the characteristic impedance for circuit elements; Thus, the current response of the measured circuit element is proportional to the square root of the driving signal.

18. The method according to claim 12, wherein: Select a current source to provide the drive signal; The control signal is the voltage response of a circuit element to a drive signal; Select characteristic admittances for circuit elements; Thus, the voltage response of the measured circuit element is proportional to the square root of the driving signal.

19. The method according to claim 12, wherein: Select a voltage source to provide the drive signal; The control signal is a drive signal; Select characteristic admittances for circuit elements; Thus, the current response of the measured circuit element is proportional to the square of the driving signal.

20. The method of claim 12, wherein: Select a current source to provide the drive signal; The control signal is a drive signal; Select the characteristic impedance for circuit elements; Thus, the voltage response of the measured circuit element is proportional to the square of the driving signal.

21. The method of any one of claims 12 to 20, wherein the circuit element comprises an analog-to-digital converter having an input and an output, the input being coupled to receive the control signal and the output being coupled to drive the switching of a plurality of controllable digital impedance or admittance synthesizers, wherein the synthesized impedance or admittance is the impedance or admittance of the circuit element.

22. The method of claim 21, wherein the circuit element further comprises a function generator coupled to preprocess the control signal with a predetermined function before it is input to the analog-to-digital converter.

23. A power supply control circuit, comprising: A power supply A load coupled to a power source, wherein the impedance of the load can be controlled by an analog signal; The arithmetic operation circuit according to claim 8 or 9 is characterized in that the driving signal is the voltage across the load terminals, and the measurement response of the circuit element is the analog signal; This keeps the power transmitted to the load constant.

24. A power control method, comprising the following steps: Couple the load to the power supply, where the impedance of the load can be controlled by an analog signal; According to the arithmetic operation method of claim 19 or 20, the voltage across the load is converted as a driving signal into a measured response of the circuit element as an analog signal; This keeps the power transmitted to the load constant.

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