Borrowing type successive approximation analog-to-digital converter adopting back propagation neural network for calibration

Abstract

The invention discloses a borrowing type successive approximation analog-to-digital converter adopting a back propagation neural network for calibration. The borrowing type successive approximation analog-to-digital converter comprises a system composed of a positive and negative capacitance digital-to-analog converter adopting a three-stage split bridge type capacitor array, a bootstrap sampling switch, an automatic return-to-zero comparator, an SAR logic control unit, an original-to-binary module and a BPNN calibration engine. Bootstrap sampling switches are respectively arranged at the tail ends of the positive and negative capacitance digital-to-analog converters, a comparator is connected with the output ends of the two, and the output is connected with an SAR logic control unit; the original-to-binary module converts the code generated by the SAR logic control unit into a binary code; and a BPNN calibration engine receives the code and performs calibration calculation by using a trained back propagation neural network model. By implementing the converter disclosed by the invention, hardware implementation can be simplified while high performance is ensured, so that the ADC realizes efficient and accurate signal conversion under a 180-nanometer BCD process, and power consumption and cost are reduced.

Description

Technical Field

[0001] This invention relates to the field of analog-to-digital converter technology, and more particularly to a borrowed successive approximation analog-to-digital converter using backpropagation neural network calibration. Background Technology

[0002] With the development of semiconductor technology, the continuous shrinking of feature sizes has significantly improved the performance of digital systems. This advancement has also driven the need for innovation in the design of ADCs (Analog-to-Digital Converters). Particularly in SAR (Successive Approximation Register) ADCs and their mixed-signal processing architectures, a significant trend is to shift more signal processing tasks from the analog domain to the digital domain in order to achieve more efficient processing and higher resolution.

[0003] However, without fine-tuning or calibration, traditional SAR ADCs are often affected by capacitance mismatch, which limits their resolution to typically no more than 8 to 10 bits. Furthermore, sampling thermal noise, comparator noise, and other device noise are also significant factors affecting the effective resolution of the ADC. In the early stages, analog calibration methods dominated due to the power consumption issues of digital logic circuits. These methods, by introducing additional analog circuitry to measure and mitigate capacitance mismatch, effectively eliminated static nonlinear errors, but often resulted in decreased conversion speed and increased circuit noise.

[0004] Therefore, digital calibration technology has gradually become mainstream in recent years because it can provide an effective calibration solution without sacrificing speed or increasing noise. In addition, several other techniques have been proposed to improve the effective resolution and linearity of ADCs, such as calibration-free methods using fault-tolerant architectures, symmetry, and redundant designs, as well as fast window switching techniques, which aim to improve ADC linearity and reduce chip area without increasing total capacitance.

[0005] Oversampling is also a widely used technique to improve signal-to-noise ratio and effective resolution. By sampling the input signal at a frequency higher than the Nyquist rate, oversampling can extend the quantization noise to a wider spectral range, making it easier to remove out-of-band noise using digital filtering and decimation techniques. However, this method results in higher power consumption and higher bandwidth requirements for the analog front-end circuitry.

[0006] While the aforementioned technologies excel in their respective fields, they generally lack versatility and are difficult to apply across ADC architectures. Recently, neural network-based calibration algorithms have begun to be integrated into ADC designs, demonstrating strong adaptability and accuracy. These algorithms extract error information by analyzing the ADC's input and output data, exhibiting good noise resistance. However, their practical application also faces challenges such as difficulty in obtaining training samples and high hardware costs.

[0007] Therefore, it is necessary to design a new analog-to-digital converter that simplifies hardware implementation while ensuring high performance, enabling the ADC to achieve efficient and accurate signal conversion using 180nm BCD technology, while reducing power consumption and cost. Summary of the Invention

[0008] The purpose of this invention is to overcome the shortcomings of the prior art and provide a borrowed successive approximation analog-to-digital converter that uses backpropagation neural network calibration.

[0009] To solve the above-mentioned technical problems, the objective of this invention is achieved through the following technical solution: A borrowed successive approximation analog-to-digital converter (ADC) using backpropagation neural network calibration is provided, comprising: a positive capacitor ADC, a negative capacitor ADC, two identical bootstrap sampling switches, an automatic zeroing comparator, a SAR logic control unit, a raw-to-binary module, and a BPNN calibration engine; the positive capacitor ADC and the negative capacitor ADC each employ a three-stage split bridge capacitor array.

[0010] Each of the positive capacitor digital-to-analog converter and the negative capacitor digital-to-analog converter has a bootstrap sampling switch at its end;

[0011] The two input terminals of the comparator are respectively connected to the output terminals of the positive capacitor digital-to-analog converter and the negative capacitor digital-to-analog converter;

[0012] The SAR logic control unit is connected to the output of the comparator;

[0013] The raw-to-binary module is connected to the SAR logic control unit and is used to convert the raw code generated by the SAR logic control unit into the final binary output code.

[0014] The BPNN calibration engine includes a calibration module based on a backpropagation neural network, which receives the binary output code from the raw to binary module, performs calibration calculations using a trained neural network model, and outputs the final calibrated result.

[0015] The further technical solution is as follows: the positive capacitor digital-to-analog converter has a redundant design for the most effective bit capacitor; the positive capacitor digital-to-analog converter includes several capacitor units, each capacitor unit is connected to the input voltage, reference voltage or ground through a switch, and the capacitor units are distributed according to binary weights.

[0016] The further technical solution is as follows: the negative capacitor digital-to-analog converter has a redundant design for the most effective bit capacitor; the negative capacitor digital-to-analog converter includes several capacitor units, each capacitor unit is connected to the input voltage, reference voltage or ground through a switch, and the capacitor units are distributed according to binary weights.

[0017] The further technical solution is as follows: the positive capacitor digital-to-analog converter and the negative capacitor digital-to-analog converter each include a 2LSB virtual capacitor, and the 2LSB virtual capacitor is connected to the bootstrap sampling switch.

[0018] The further technical solution is as follows: the automatic zeroing comparator includes a static four-stage preamplifier and a dynamic latch; each stage of the preamplifier adopts automatic zeroing technology to reduce the comparator offset and low-frequency flicker noise; the output of the preamplifier is connected to the dynamic latch.

[0019] The further technical solution is as follows: the BPNN calibration engine includes a three-layer BP neural network, which includes an input layer, a hidden layer and an output layer, wherein the hidden layer includes neurons.

[0020] The further technical solution is as follows: the hidden layer includes a neuron, and the BPNN calibration engine uses a linear activation function.

[0021] Its further technical solution is as follows: the calibration process of the BPNN calibration engine includes:

[0022] The binary output code is interpolated to increase data density, and periodic error features are extracted by sine fitting to form input data;

[0023] The input data is passed through a BP neural network with a single hidden layer. The computation process is simplified by using a linear activation function. The BP neural network optimizes the calibration performance by adjusting a limited number of weights and bias parameters. Based on the feedback of the loss function, the weights and biases are updated by the backpropagation algorithm to minimize the prediction error and output the final calibrated result.

[0024] The further technical solution is as follows: the BPNN calibration engine includes several multiplexers and one adder; the several multiplexers are respectively connected to the adder.

[0025] Furthermore, to overcome the shortcomings of the prior art, the present invention also provides a method for operating the above-mentioned borrowed successive approximation analog-to-digital converter using backpropagation neural network calibration, characterized in that it includes:

[0026] The input signal is sampled into the capacitor arrays of the positive capacitor digital-to-analog converter and the negative capacitor digital-to-analog converter through a bootstrap sampling switch;

[0027] The SAR logic control unit controls the switching states in the capacitor array to successively approximate the voltage value of the input signal;

[0028] The comparator compares the output voltages of the positive capacitor digital-to-analog converter and the negative capacitor digital-to-analog converter, and outputs the comparison result;

[0029] The SAR logic control unit generates the control signal for the next stage based on the comparison results, until all comparisons are completed;

[0030] The raw-to-binary module converts the raw code generated by the SAR logic control unit into binary output code.

[0031] The BPNN calibration engine calibrates the binary output code and outputs the final calibration result.

[0032] The advantages of this invention compared to existing technologies are as follows: By integrating a positive capacitor digital-to-analog converter, a negative capacitor digital-to-analog converter, a bootstrap sampling switch, an automatic zero-return comparator, a SAR logic control unit, a raw-to-binary module, and a BPNN calibration engine, this invention simplifies hardware design while ensuring high performance using a three-stage split bridge capacitor array. In particular, the BPNN calibration engine can perform calibration calculations on the original code using a trained neural network model, effectively improving the accuracy and efficiency of signal conversion while reducing hardware complexity and power consumption. Using 180nm BCD technology, this design not only achieves efficient and accurate signal conversion but also significantly reduces cost and energy consumption, embodying the design philosophy of achieving hardware simplification and economic optimization while maintaining or improving performance.

[0033] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1A circuit schematic diagram of a borrowed successive approximation analog-to-digital converter with backpropagation neural network calibration provided for an embodiment of the present invention;

[0036] Figure 2 This is a schematic diagram of the circuit structure of an existing analog-to-digital converter.

[0037] Figure 3 This is a schematic diagram of the circuit structure of the positive capacitor digital-to-analog converter and the negative capacitor digital-to-analog converter provided in the embodiments of the present invention;

[0038] Figure 4 The circuit schematic diagram of the bootstrap sampling switch provided in the embodiment of the present invention;

[0039] Figure 5 The circuit diagram of the automatic zero-reset comparator provided in the embodiment of the present invention;

[0040] Figure 6 This is a schematic diagram of the topology of the second-order zero-adjustment technique provided in an embodiment of the present invention;

[0041] Figure 7 A schematic diagram of BP neural network calibration provided in an embodiment of the present invention;

[0042] Figure 8 This is a schematic diagram of off-chip training of BPNN provided in an embodiment of the present invention;

[0043] Figure 9 A schematic diagram illustrating the variations of DNL, ​​INL, and SNDR under different numbers of calibration MSB capacitors provided in an embodiment of the present invention;

[0044] Figure 10 The mapping relationship between bin code, source code, DCOMP and DOUT provided in the embodiments of the present invention;

[0045] Figure 11 This is a schematic diagram of the proposed off-chip training for BPNN calibration provided in an embodiment of the present invention;

[0046] Figure 12 A schematic diagram illustrating the hardware implementation of the BPNN calibration algorithm provided in an embodiment of the present invention;

[0047] Figure 13 A schematic diagram illustrating the percentage error when applying different decimal places, provided in an embodiment of the present invention;

[0048] Figure 14 A schematic diagram of the calibrated ADC spectrum at a frequency of 50kHz provided in an embodiment of the present invention;

[0049] Figure 15 This is a schematic diagram of the calibrated ADC spectrum at a frequency of 480kHz, provided in an embodiment of the present invention.

[0050] Figure 16 This is a schematic diagram showing the simulated DNL and INL before and after calibration, as provided in an embodiment of the present invention. Detailed Implementation

[0051] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0052] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0053] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0054] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0055] With advancements in semiconductor technology and the shrinking of feature sizes, SAR ADC designs are increasingly shifting signal processing tasks from the analog domain to the digital domain in pursuit of higher performance and resolution. However, factors such as capacitor mismatch and noise limit the resolution of traditional SAR ADCs to typically no more than 8 to 10 bits. Early methods mitigated these effects through analog calibration, but often sacrificed speed and increased noise. In recent years, digital calibration techniques have become mainstream due to their ability to provide effective calibration solutions without sacrificing performance. Furthermore, calibration-free methods employing fault-tolerant architectures, symmetry, and redundant designs, along with fast window switching and oversampling techniques, have improved the effective resolution and linearity of ADCs, although the latter increases power consumption and the bandwidth requirements of the analog front-end. These advancements have collectively driven significant improvements in ADC performance.

[0056] To address this, embodiments of the present invention provide a borrowed successive approximation analog-to-digital converter (ADC) calibrated using a backpropagation neural network. This simplifies hardware implementation while maintaining high performance, enabling the ADC to achieve efficient and accurate signal conversion using a 180nm BCD process, while reducing power consumption and cost.

[0057] Specifically, efficient and accurate signal conversion is achieved by integrating a positive-to-negative capacitance digital-to-analog converter, a bootstrap sampling switch, an auto-zero comparator, a SAR logic control unit, a raw-to-binary module, and a BPNN calibration engine. In particular, the positive-to-negative capacitance digital-to-analog converter employs redundant design and virtual capacitors to reduce the impact of capacitance mismatch, and the BPNN calibration engine utilizes a simplified three-layer neural network structure for error calibration, reducing hardware complexity. Furthermore, the auto-zero comparator uses a static preamplifier and dynamic latches to reduce offset and noise. The entire system, built on a 180nm BCD process, not only ensures high performance but also effectively reduces power consumption and cost, thus providing a solution that simplifies hardware implementation while maintaining high accuracy and efficiency.

[0058] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0059] Please see Figure 1 A borrowed successive approximation analog-to-digital converter (ADC) with backpropagation neural network calibration is characterized by comprising: a positive capacitor ADC, a negative capacitor ADC, two identical bootstrap sampling switches, an automatic zeroing comparator, a SAR logic control unit, a raw-to-binary module, and a BPNN calibration engine; the positive capacitor ADC and the negative capacitor ADC each employ a three-stage split bridge capacitor array.

[0060] Each of the positive capacitor digital-to-analog converters and the negative capacitor digital-to-analog converters has a bootstrap sampling switch at its end.

[0061] The two input terminals of the comparator are connected to the output terminals of the positive capacitor digital-to-analog converter and the negative capacitor digital-to-analog converter, respectively;

[0062] The SAR logic control unit is connected to the output of the comparator;

[0063] The raw-to-binary module connects to the SAR logic control unit and is used to convert the raw code generated by the SAR logic control unit into the final binary output code.

[0064] The BPNN calibration engine includes a calibration module based on a backpropagation neural network, which receives the binary output code from the raw binary module and performs calibration calculations using a trained neural network model to output the final calibrated result.

[0065] In this embodiment, both the positive capacitor digital-to-analog converter and the negative capacitor digital-to-analog converter employ three-stage split bridge capacitor arrays. This design helps improve redundancy and reduce capacitor mismatch errors. Each capacitor cell is connected to the input voltage, reference voltage, or ground via a switch, with the most significant bit (MSB) capacitor specially designed to increase redundancy.

[0066] Both the positive-capacitor digital-to-analog converter and the negative-capacitor digital-to-analog converter have an identical bootstrap sampling switch at the end. These switches are used to ensure that the signal is not distorted during sampling and to reduce the total sampling capacitance requirement.

[0067] The automatic zero-return comparator includes a static preamplifier and a dynamic latch, which can significantly reduce offset voltage and low-frequency flicker noise, thereby improving conversion accuracy.

[0068] The SAR logic control unit is connected to the output of the comparator and is responsible for generating the control signal for the next stage based on the comparison result, guiding the successive approximation process until all comparisons are completed.

[0069] The raw-to-binary module is connected to the SAR logic control unit and its function is to convert the raw code generated by the SAR logic control unit into the final binary output code.

[0070] The BPNN calibration engine is a calibration module based on a backpropagation neural network. It primarily receives the binary output code from the raw binary module and performs calibration calculations using a pre-trained neural network model. Notably, this design uses only nine parameters to complete on-chip calibration, significantly reducing hardware overhead and power consumption. The calibrated ADC performance is significantly improved, with notable improvements in key metrics such as differential nonlinearity (DNL), integral nonlinearity (INL), signal-to-noise ratio (SNDR), and distortion-free dynamic range (SFDR).

[0071] In summary, the analog-to-digital converter in this embodiment achieves efficient and accurate signal conversion by cleverly combining hardware design with neural network algorithms, while maintaining low power consumption and cost. This design is particularly suitable for applications with high requirements for both performance and cost.

[0072] Specifically, a backpropagation neural network (BPNN) calibration mechanism is integrated. Core architecture analysis shows that this ADC includes a positive capacitor digital-to-analog converter (CDAC), a negative capacitor digital-to-analog converter, two identical sets of bootstrap sampling switches, an automatic zero-return comparator, a SAR logic control unit, a raw-to-binary conversion module, and a BPNN calibration engine. The CDAC employs a unique three-stage split-bridge capacitor array structure, and the MSB capacitors are segmented to increase redundancy.

[0073] To overcome the mismatch problem in traditional ADCs, a BPNN mismatch calibration scheme is proposed. This scheme utilizes a backpropagation neural network with a linear activation function, requiring only 9 parameters after off-chip training to achieve efficient calibration. Experimental results show that after calibration, the ADC's differential nonlinearity (DNL) is improved from ±1 LSB to +1.03 / -0.81 LSB, the integral nonlinearity (INL) is optimized from ±4.51 LSB to +0.75 / -0.72 LSB, the signal-to-noise ratio (SNDR) is improved by 8.03 dB, and the distortion-free dynamic range (SFDR) is improved by 38.15 dB. The entire system is fabricated using a 180 nm bipolar complementary metal-oxide-semiconductor (BCD) process and is powered by a single 1.8 V supply.

[0074] By redesigning the three-stage capacitor-to-digital-to-analog converter (CDAC) and adjusting the scaling of each segment, calibration of a redundant 16-bit successive approximation register (SAR) analog-to-digital converter was successfully achieved using only nine neural network parameters. This significantly simplifies hardware complexity and power consumption.

[0075] By combining the most significant bit (MSB) capacitor weight reassembly with the proposed weight borrowing method, redundancy is ensured in all binary codes. This strategy avoids performance waste and guarantees the accuracy of data conversion when using neural networks for ADC calibration.

[0076] The adoption of a two-stage automatic zeroing technique significantly reduces the comparator's offset voltage, and the use of equivalent sampling virtual capacitors reduces the total sampling capacitance requirement. Furthermore, this embodiment proposes a 16-bit 1MS / s SARADC based on backpropagation neural network calibration. It innovatively employs a split-bridge capacitor array and borrows weights from the virtual capacitors, ensuring that each binary code corresponds to at least two original codes, further enhancing redundancy and reliability.

[0077] In one embodiment, please refer to Figure 2 and Figure 3 The positive capacitance digital-to-analog converter features a redundant design for the most effective bit capacitor. The positive capacitance digital-to-analog converter includes several capacitor units, each of which is connected to the input voltage, reference voltage, or ground via a switch. The capacitor units are distributed according to binary weights.

[0078] In one embodiment, please refer to Figure 2 and Figure 3 The negative capacitance digital-to-analog converter features a redundant design for the most effective bit capacitor. The negative capacitance digital-to-analog converter includes several capacitor units, each of which is connected to the input voltage, reference voltage, or ground via a switch. The capacitor units are distributed according to binary weights.

[0079] In this embodiment, when the comparator makes an incorrect decision due to factors such as the capacitor-to-analog converter not being fully stable, comparator noise, or other factors, a redundancy mechanism can correct these errors in subsequent comparison steps. Traditionally, such as Figure 2 As shown, an N-bit successive approximation analog-to-digital converter requires N comparisons. However, with redundancy, the number of comparisons (M) for a redundant N-bit SARADC exceeds N. This means that after all comparisons are completed, the M-bit redundant digital output code (raw code) must be converted into an N-bit binary digital output code (binary code). It is worth noting that multiple different raw codes can uniquely correspond to the same binary code.

[0080] There are three main redundancy techniques. The first is based on traditional binary distributed capacitor arrays, which achieve redundancy by replicating one or more capacitors. This method results in a total capacitor weight exceeding a power of 2, potentially leading to changes in the least significant bit (LSB) when converting the M-bit raw code output by the comparator to N-bit binary code. To mitigate this problem, a digital error correction (DEC) algorithm is currently used to convert the raw code. However, this method limits the swing of the input signal. Therefore, a method is proposed to achieve redundancy by splitting the most significant bit (MSB) capacitor, ensuring that the total capacitor weight remains a power of 2, thus avoiding the problem of unequal least significant bits.

[0081] The first two redundancy techniques are also known as binary redundancy techniques, while the third is called non-binary redundancy techniques. Non-binary redundancy techniques require that the weight of each capacitor be known in advance and stored in memory.

[0082] In this embodiment, a novel 16-bit three-stage capacitive digital-to-analog converter (CDAC) is proposed based on binary redundancy technology, ensuring redundancy in all binary digital codes. For a 16-bit fully differential architecture, the total weight required for half of the CDAC is 2. 15 =32768 LSB. Figure 2 The schematic of a traditional (4+4+7) bit three-stage CDAC is shown, with the capacitors in each CDAC segment arranged in binary order. By designing bridging capacitors and virtual capacitors, the weight scaling ratio of each CDAC segment is 1 / 16.

[0083] The proposed three-level redundant CDAC with weighted borrowing, such as Figure 3 As shown, the weight scaling ratios of CDAC1 to CDAC2 and CDAC2 to CDAC3 are respectively given by the formulas... and Given: CCDAC1,tot represents the total capacitance of CDAC1, CCDAC2,tot represents the total capacitance of CDAC2, and C CDAC1,eqv represents the capacitance of CDAC1 equivalent to CDAC2, i.e.: To achieve redundancy, the MSB capacitor is split, with the CDAC3 MSB capacitor divided into two parts: 62Cu + 2Cu (Cu represents a unit capacitor). Since the scaling ratio of CDAC1 to CDAC3 is 1 / 256, the weight represented by 2Cu in CDAC3 is 2 × 256 LSB = 512 LSB. First, 256 LSB is allocated to the least significant bit (LSB) of CDAC3, and the remaining 256 LSB is shared by CDAC1 and CDAC2. Figure 3 The total weight of CDAC1 is 1+1+2+3+6+11=24LSB, so an additional 8LSB is allocated. The remaining 256-8=248LSB is allocated to CDAC2.

[0084] Meanwhile, the MSB capacitor of CDAC2 borrows 8 LSB (2Cu) from CDM2, bringing its total weight to 128 + 96 + 8 = 232 LSB. The 8 LSB borrowed from CDM2 makes the total weight of the half-side CDAC capacitor 2^15 + 8 = 32776 LSB, expanding the quantization range of the ADC from 0 to 65535 to 0 to 65551. For example, to obtain the bin code 65535, the comparator's M judgments must all be 1, meaning the original code must be all 1s. However, due to the 8 LSB borrowing weight, 65535 can correspond to multiple different original codes, achieving redundancy for all binary codes.

[0085] Furthermore, since the weights are borrowed from the dummy signal, the least significant bit (LSB) of the fully differential SAR ADC remains unchanged, still being 2V_REF / 2. N The 8LSB extended weight not only improves the effectiveness and accuracy of BPNN calibration, but also ensures that even in extreme cases, increasing the weight by 8LSB will not cause the top-plate voltage of the CDAC3 to exceed the power rail.

[0086] Redundancy reduces the drive stress on the reference buffer and the settling time requirements of the CDAC circuit. However, it does not change the mismatch between the actual and ideal weights of each unit capacitor, failing to mitigate capacitor mismatch in the CDAC and thus leading to nonlinearity. Nevertheless, considering the area trade-offs, this effect is acceptable and can be reduced through calibration.

[0087] In one embodiment, the positive capacitance digital-to-analog converter and the negative capacitance digital-to-analog converter described above each include a 2LSB virtual capacitor, which is connected to a bootstrap sampling switch.

[0088] To alleviate the driving pressure on the ADC input, the CDAC3 proposed in this embodiment adds a 2LSB virtual capacitor compared to the traditional three-stage CDAC. During the sampling phase, this 2-bit capacitor is connected to a bootstrap switch, enabling it to sample both CDAC1 and CDAC2, thus limiting the total sampling capacitance to 128Cu. Furthermore, a baseboard sampling switching algorithm based on common-mode voltage (VCM) is employed. After sampling, the positive and negative input signals of the comparator are immediately compared.

[0089] In one embodiment, to further improve the linearity of the sampled signal, a bootstrap switch is introduced into the system, such as... Figure 4 As shown, when the input signal changes, the bootstrap switch ensures that the gate-source voltage (VGS) remains constant, helping to maintain a more stable on-resistance and thus improving dynamic linearity. Simultaneously, by using a differential architecture, channel charge injection can be kept constant and eliminated as common-mode noise. This approach not only improves the overall system performance but also reduces nonlinear distortion caused by input signal variations. Therefore, combining these design improvements not only effectively reduces the driving load on the ADC input but also significantly improves the linearity and stability of the sampled signal.

[0090] In one embodiment, please refer to Figure 5 and Figure 6 The auto-zero comparator includes a static four-stage preamplifier and a dynamic latch; each stage of the preamplifier uses auto-zero technology to reduce comparator offset and low-frequency flicker noise; the output of the preamplifier is connected to the dynamic latch.

[0091] like Figure 5 As shown, this comparator employs a static four-stage preamplifier and a dynamic latch architecture. Each preamplifier stage utilizes auto-zeroing technology to reduce offset and low-frequency flicker noise. Taking A1 as an example, as... Figure 6 As shown, a second-order auto-zeroing technique is used here. GM2 is added to the first-order auto-zeroing to further reduce offset and flicker noise, while GM4 is used to eliminate the offset introduced by GM2.

[0092] The working principle is as follows:

[0093] First stage (SW0 on): In this stage, the output voltage of GM2 can be expressed as -GM2R2VOS2-GM4R2(VOUT2,ph1+VOS4)=VOUT2,ph1;

[0094] After simplification, we get

[0095] Second stage (SW1 on, SW0 off): At this time, the output voltages of GM1 and GM2 are given by VOUT1,ph2 = -GM1R1VOS1 - GM6R1(-VOUT2,ph2+VOS3) and VOUT2,ph2 = -GM2R2(VOUT1,ph2+VOS2) - GM4R2(VOUT2,ph1+VOS4), respectively. Substituting VOUT1,ph2 = -GM1R1VOS1 - GM3R1(-VOUT2,ph2+VOS3) into VOUT2,ph2 = -GM2R2(VOUT1,ph2+VOS2) - GM4R2(VOUT2,ph1+VOS4) and simplifying the process, we obtain...

[0096] The third stage (SW2 is on, SW0 and SW1 are off): The output voltage of GM1 can be expressed as VOUT1,ph3 = -GM1R1(VIN+VOS1)-GM3R1(-VOUT2,ph2+VOS3);

[0097] Will Substituting the result into VOUT1,ph3=-GM1R1(VIN+VOS1)-GM3R1(-VOUT2,ph2+VOS3), and considering that GM4R2 and GM2R2 are not infinite, the offset cannot be completely eliminated. The actual equivalent input offset voltage is given by VOUT2,ph2≈(VOS1+VOS3).

[0098] This design not only reduces comparator offset and low-frequency flicker noise but also improves the overall system performance and stability. Nevertheless, completely eliminating offset remains a challenge due to limitations in practical circuit component parameters. However, the method described above significantly reduces the impact of offset, improving the accuracy and reliability of signal processing.

[0099] For a raw-to-bin module, in an N-bit M-order redundant fully differential successive approximation (SAR) analog-to-digital converter (ADC), the binary output code (denoted as DB) of this type of ADC can be calculated according to the following formula: Here, D Ri Represents the original code, while w i This indicates the weight of each comparison capacitor.

[0100] Furthermore, the second term in the above equation can be further decomposed into two parts: Among them, w i + and w i - They are defined as follows: Based on these definitions, we have: Therefore, DB can be restated as: Given that this system borrows 8 least significant bits (LSBs) of weight, this means that in application... The result obtained needs to be subtracted from the value corresponding to these 8 LSBs. In other words, when finally determining the value of DB, an amount equivalent to 8 LSBs needs to be subtracted from the result obtained by formula (15) to accommodate the adjustment brought about by this borrowing mechanism. Only after this processing can the DB value accurately reflect the actual binary output code after considering the influence of the 8 LSB extended weight.

[0101] For the SAR logic control unit, the AR logic control unit is responsible for guiding the ADC to perform a series of comparison operations, controlling the comparators to determine whether each bit is "1" or "0". This process involves progressively determining the final binary output code DB based on the relationship between the input voltage and the reference voltage.

[0102] The SAR logic control unit also needs to handle redundancy weights w i The allocation and adjustment of w. This includes calculating w. i + and w i - This ensures that these weights are accurately reflected in the final output code DB. In particular, in the case of redundant designs, the logic control unit must correctly apply these weights to compensate for any possible errors or inaccuracies.

[0103] Because of the use of an 8 least significant bits (LSB) weighting mechanism, the SAR logic control unit needs to adjust the final result appropriately. This means that after completing all comparisons and weight calculations, it also needs to subtract a value equivalent to 8 LSBs from the final output code DB to obtain the correct output result.

[0104] Considering equation (15) and the restatement of DB, the SAR logic control unit should support efficient algorithm implementation in order to quickly and accurately complete the transformation from the original code D. Ri The conversion to binary output code (DB). This efficiency is crucial for improving the overall operating speed of the ADC.

[0105] In summary, the SAR logic control unit plays a crucial role in SARADC. It not only needs to precisely control the analog-to-digital conversion process, but also needs to flexibly handle complex weight adjustments and specific hardware features such as LSB borrowing mechanisms, thereby ensuring the accuracy and reliability of the final output results.

[0106] In one embodiment, such as Figure 7 and Figure 8As shown, the BPNN calibration engine includes a three-layer BP neural network, which consists of an input layer, a hidden layer, and an output layer. The hidden layer contains neurons.

[0107] In one embodiment, such as Figure 7 and Figure 8 As shown, the hidden layer consists of a single neuron, and the BPNN calibration engine uses a linear activation function.

[0108] In this embodiment, as Figure 7 and Figure 8 As shown, there are two main neural network (NN) calibration algorithms: the first method directly predicts the target calibration result using the neural network [26–28, 32]; while the second method corrects the output code of the actual analog-to-digital converter (ADC) by using a compensation signal [29–31, 33, 34]. This paper chooses the second strategy because it typically provides more information when the number of parameters is limited and is well-suited for effective calibration of redundant ADCs.

[0109] Before the calibration process begins, the neural network needs to be trained to learn the mapping relationship between inputs and outputs. Only then can the trained NN be applied to the ADC calibration. Due to the difficulty of obtaining the ground truth and the complexity of the training algorithm, the training process of the NN is often implemented in software. A block diagram of an ADC system based on NN calibration is shown below. Figure 7 As shown in the diagram, in this system, the ADC samples and converts the input sinusoidal signal VIN to generate M-bit raw code. After 2K samplings, these 2K raw codes are sent to the NN for off-chip training. Subsequently, the parameters of the trained NN are stored. Then, all the raw codes converted by the ADC are input to both the raw code-to-binary converter and the trained NN, and their outputs are summed to obtain the final calibrated ADC output DOUT.

[0110] Furthermore, off-chip training schemes based on sinusoidal fitting BP neural networks (BPNN) include... Figure 8As shown in the diagram. Specifically, 2K raw codes are first sent to a Raw-to-Binary converter to generate 2K bin codes. These bin codes are then used for sine fitting to obtain an ideal discrete sine signal. y(k) represents the difference between the ideal discrete sine signal and the actual ADC output, which is also the training target of the BPNN. This difference is the error. By backpropagating the error between y(k) and f(k), the parameters of the BPNN (including weights and biases) can be continuously adjusted during multiple iterations. Finally, the DCOMP value corresponding to each raw code can be calculated using the trained BPNN parameters. In this way, the calibration accuracy of the ADC can be improved, while hardware overhead and power consumption can be effectively reduced.

[0111] like Figure 8 As shown, a simple three-layer backpropagation neural network (BPNN) is used, consisting of an input layer (m neurons), a hidden layer (n neurons), and an output layer (1 neuron). Even with such a simple BPNN, without considering the parameters required for normalization, it still contains mn+2m+1 parameters, which is a considerable burden for hardware implementation. Therefore, it is necessary to optimize the BPNN to reduce hardware costs.

[0112] For an N-bit M-order successive approximation (SAR) ADC, the least significant bit (LSB) capacitor mismatch can be ignored because these weights are small. In the proposed capacitor-to-analog converter (CDAC) design, the capacitor weights in CDAC1 are small enough that calibration is unnecessary. However, the per-bit capacitance in CDAC3, although small, requires calibration due to the large weight scaling (7 bits in total). For CDAC2, since the unit capacitance weight is four times that of CDAC1 and the mismatch increases, calibration or partial calibration is also required. By adjusting the scaling ratio of the three-stage CDAC, not only can the mismatch be reduced, but the number of capacitors requiring calibration can also be reduced.

[0113] In this embodiment, when using only one hidden layer neuron and all activation functions are linear, the calibration effect of the BPNN is equivalent to that of a traditional three-layer BPNN. This is because ADC nonlinear correction is essentially a linear fitting task. Therefore, adopting this simplified structure can significantly reduce hardware implementation requirements.

[0114] A simulation experiment was conducted using a 5m×5m MIM capacitor (with random mismatch) fabricated using a 180nm process. The simulation employed an idealized comparator and ignored the effects of noise. Figure 9This paper demonstrates the changes in differential nonlinearity (DNL), integral nonlinearity (INL), and signal-to-noise ratio (SNDR) when calibrating 6 to 12 MSB (most significant bit) capacitors (where 0 indicates no calibration). The results show that when only 6 or 7 MSB capacitors are calibrated, the DNL value reaches -1 LSB, indicating missing bits. However, when calibrating 8-bit or higher MSB capacitors using a BPNN (backpropagation neural network), the performance improvements in DNL, ​​INL, and SNDR tend to stabilize; therefore, we determined the number of neurons in the input layer to be 8.

[0115] It's worth noting that with only one hidden layer neuron and all activation functions being linear, the calibration performance of a BPNN is identical to that of a traditional three-layer BPNN. This is because when we use a neural network to calibrate an ADC, we are essentially adjusting the nonlinear characteristics of the ADC to linear ones. Therefore, we only need to consider the linear fitting capability of the neural network, without needing to focus on its nonlinear fitting capability. This means that linear calibration can be achieved using simple hidden layer neurons and linear activation functions, significantly reducing the complexity of the calibration network's hardware implementation.

[0116] The aforementioned BPNN-based calibration method is particularly suitable for ADCs with redundant designs. For N-bit ADCs without redundancy, a situation may arise where some bin codes are transformed into different bin codes after compensation, resulting in gaps in the original bin code positions. In other words, after BPNN training, 2 N Only one bin code can generate 2 N There are 2 DCOMP values. If two DOUTs (i.e., bincode plus DCOMP) are equal, the total number of distinct DOUTs will be less than 2. N This can lead to code loss issues. Conversely, in an ADC with redundancy, a total of 2 can be generated. M 2 source codes. After training, a total of 2... M One DCOMP value to compensate for 2 N 1 bin code, thus obtaining a total of 2 M These are the compensated DOUT values, some of which may be the same. These 2 M One DOUT value is assigned to 2 N Within each bin, the total number of different DOUTs is less than 2. N The probability is almost zero, effectively avoiding code loss. This mapping relationship is as follows: Figure 10 As shown.

[0117] First, the weight borrowing technique increases the redundancy at full scale, ensuring that a bin code close to full scale can correspond to at least two or more original codes. Second, during the sine fitting process, by making the amplitude of the analog sinusoidal signal input to the analog-to-digital converter (ADC) greater than the range of interest (±VREF), the probability of original codes appearing close to the ADC's full scale within that range can be increased. This redundancy is achieved through most significant bit (MSB) capacitor recombination, while the least significant bit (LSB) equals 2VREF / 2^16. Therefore, the 16-bit ADC designed in this paper does not result in performance waste.

[0118] The proposed BPNN calibration scheme is as follows: Figure 11 As shown, an m×1×1 BPNN is used to calibrate a 16-bit, 20-step fully differential SAR ADC (m=8 in this example). The activation functions for both the hidden and output layers are f(x) = x. Since the sinusoidal signal input to the ADC slightly exceeds the quantization range, linear interpolation is required for the truncated portion to recover the sinusoidal signal. The mean squared error (MSE) loss function E(k) = 1 / 2(y(k) - f(k))^2 is used to handle the difference between y(k) and f(k) of the BPNN. To obtain better training results, the input (denoted as dRi, i=1...m) and the target (y(k)) of the training set are normalized.

[0119] The trained parameters include the weights w1, 1, w2, 1, ..., wm, 1 from the input layer to the hidden layer; the weights w1, 2 from the hidden layer to the output layer; and the biases b1 from the input layer to the hidden layer and b2 from the hidden layer to the output layer. The following are the steps for calculating DCOM using the trained BP neural network:

[0120] The normalization method is as follows:

[0121] The inverse normalization method is as follows:

[0122] Where x is the data vector to be normalized, x max and x min These are the maximum and minimum values ​​of x, respectively. For d... Ri After normalization, we get d i As shown below: d i =2d Ri -1;

[0123] Substituting the above formulas into the BPNN, we obtain y1, y2, and D sequentially. COMP : y2=b2+w 1,2 y1;D COMP =f -1(y); Let b′=b′2+w′ 1，2 b1; w = w 1，2 w i (i = 1...m), resulting in a total of m+1 parameters, which are then stored on the chip. Since dRi is either 0 or 1, on-chip computation can be performed using only a few adders. This simplifies hardware implementation and improves efficiency. Furthermore, this approach ensures effective ADC calibration even under high-precision requirements, enhancing its performance.

[0124] In one embodiment, the calibration process of the BPNN calibration engine described above includes:

[0125] The binary output code is interpolated to increase data density, and periodic error features are extracted through sine fitting to form the input data;

[0126] The input data is passed through a BP neural network with a single hidden layer. The computation process is simplified by using a linear activation function. The BP neural network optimizes the calibration performance by adjusting a limited number of weights and bias parameters. Based on the feedback of the loss function, the weights and biases are updated by the backpropagation algorithm to minimize the prediction error and output the final calibrated result.

[0127] The BPNN calibration engine consists of several multiplexers and one adder; the multiple multiplexers are connected to the adder respectively.

[0128] Furthermore, the hardware implementation of the proposed calibration algorithm is as follows: Figure 12 As shown. In the software-based training phase, pre-trained and pre-computed parameters are used in the calibrated hardware implementation. Hardware operation requires only m multiplexers (MUX) and one adder. When d Ri When the value is 1, the MUX selects the corresponding data for processing. Then, an adder sums all the selected data to complete the final calculation. To reduce register usage, determining the data width of the parameters is crucial. Especially for the integer part, the maximum possible D must be known. COMP This value reflects the maximum degree of nonlinearity of the SARADC caused by capacitance mismatch and is roughly equivalent to the maximum value of the integral nonlinearity (INL). According to Figure 9 The data shows that the maximum INL is less than 10 LSB, therefore D is determined. COMP The integer part of the parameter has a width of 4 bits.

[0129] For the fractional part, modeling analysis was performed in MATLAB to determine how the fractional width of the parameters affects the calibration results. First, the parameters were converted to binary format, and then the fractional part was progressively reduced to 1 to 8 bits. (Iteration 2) 20The original code is used to obtain calibration compensation values ​​after reducing the number of decimal places. Based on the comparison of these compensation values ​​with the original parameters, the percentage of error can be calculated. The results are as follows: Figure 13 As shown, 8 decimal places are sufficient for good error control. Since the parameters are signed, an additional sign bit is added to the most significant bit (MSB). Therefore, each parameter stored in the chip consists of 1 sign bit, 4 integer bits, and 8 decimal places. Considering there are a total of 9 calibration parameters, the total number of register resources used is 117. This method not only simplifies hardware design but also ensures high-precision calibration results.

[0130] Please see Figure 14 and Figure 15 The successive approximation register analog-to-digital converter (SARADC) simulation is based on a 180nm BCD process and powered by a single 1.8V supply. Before calibration, a 10kHz sine wave slightly larger than full scale is input to the ADC to obtain 2... 14 =16384 data points, and these data were used to train the parameters of the backpropagation neural network (BPNN). Figure 14 and Figure 15 This demonstrates the spectral signal analysis results of a SARADC for a sinusoidal wave. Specifically, Figure 14 (a) and Figure 14 (b) shows the uncalibrated data Fast Fourier Transform (FFT) spectra at low-frequency and Nyquist inputs, respectively. Figure 15 (a) and Figure 15 (b) presents the results after calibration using the BPNN algorithm. Figure 14 As can be seen, after calibration of the 50kHz input signal, the signal-to-noise ratio dynamic range (SNDR) improved from 81.44dB to 89.87dB, and the distortion-free range (SFDR) increased from 86.09dB to 124.24dB. Similarly, for the 480kHz input signal, the SNDR increased from 81.44dB to 89.88dB, and the SFDR increased from 86.09dB to 123.55dB. This demonstrates that the proposed BPNN calibration algorithm can effectively calibrate the SARADC of the input signal within the Nyquist bandwidth.

[0131] like Figure 16As shown, a code density method was employed with a low-frequency sine wave as input to evaluate differential nonlinearity (DNL) and integral nonlinearity (INL). The peak DNL of the uncalibrated ADC was +1 / -1 least representable bits (LSB), which decreased to +1.03 / -0.81 LSB after calibration. The peak INL of the uncalibrated ADC was +4.51 / -4.51 LSB, which decreased to +0.75 / -0.72 LSB after calibration. Table 1 summarizes the comparison with other analog-to-digital converter (ADC) neural network (NN) calibration algorithms, showing that the proposed 16-bit ADC has only one more neuron in the input layer, and the amount of training data is four times that of a 12-bit ADC. Compared with previous work, this embodiment achieves the best balance in terms of NN architecture, hardware overhead, and calibration capability.

[0132] Furthermore, this embodiment increases the total capacitance of CDAC2 by redesigning the three-stage capacitor digital-to-analog converter (CDAC) and adjusting the proportion of each segment, thereby further reducing the number of parameters required for the BPNN calibration algorithm. By combining weight recombination and weight borrowing methods with the most significant bit (MSB) capacitor, redundancy of all binary codes is achieved, ensuring no performance waste occurs when applying NN calibration. Simulation results show that this ADC requires only 9 NN parameters to complete calibration, and the signal-to-noise ratio distortion ratio (SNDR) and spectral distortion ratio (SFDR) are improved by 8.03 dB and 38.15 dB, respectively, after calibration. This series of improvements effectively enhances the overall performance of the ADC, demonstrating the effectiveness and superiority of the proposed BPNN calibration method.

[0133] The borrowed successive approximation analog-to-digital converter with backpropagation neural network calibration in this embodiment can be used in scenarios with 16 bits or other bit lengths, such as 18 bits, 20 bits, and 24 bits.

[0134] The aforementioned borrowed successive approximation analog-to-digital converter (ADC) employing backpropagation neural network calibration integrates a positive-capacitor ADC, a negative-capacitor ADC, a bootstrap sampling switch, an auto-zero comparator, a SAR logic control unit, a raw-to-binary module, and a BPNN calibration engine. It simplifies hardware design while maintaining high performance using a three-stage split-bridge capacitor array. In particular, the BPNN calibration engine can perform calibration calculations on the original code using a trained neural network model, effectively improving the accuracy and efficiency of signal conversion while reducing hardware complexity and power consumption. Using 180nm BCD technology, this design not only achieves efficient and accurate signal conversion but also significantly reduces cost and energy consumption, embodying a design philosophy of hardware simplification and cost-effectiveness optimization while maintaining or improving performance.

[0135] In one embodiment, a method for operating the above-described borrowed successive approximation analog-to-digital converter using backpropagation neural network calibration is also provided, comprising:

[0136] The input signal is sampled into the capacitor arrays of the positive capacitor digital-to-analog converter and the negative capacitor digital-to-analog converter through a bootstrap sampling switch;

[0137] The SAR logic control unit controls the switching states in the capacitor array to successively approximate the voltage value of the input signal;

[0138] The comparator compares the output voltages of the positive capacitor digital-to-analog converter and the negative capacitor digital-to-analog converter, and outputs the comparison result;

[0139] The SAR logic control unit generates the control signal for the next stage based on the comparison results, until all comparisons are completed;

[0140] The raw-to-binary module converts the raw code generated by the SAR logic control unit into binary output code.

[0141] The BPNN calibration engine calibrates the binary output code and outputs the final calibration result.

[0142] Specifically, firstly, the analog input signal to be converted is sampled into the capacitor arrays of the positive capacitor digital-to-analog converter (CDAC) and the negative capacitor digital-to-analog converter via a bootstrap sampling switch. Here, the bootstrap sampling switch ensures that the signal can be accurately and losslessly captured by the capacitor array.

[0143] Next, the SAR logic control unit begins operation, controlling the switch states in the capacitor array and approximating the input signal voltage value by progressively adjusting the states of these switches. This process is the core of successive approximation, and its purpose is to find the binary representation that best approximates the input voltage.

[0144] After each approximation step, the automatic zeroing comparator compares the output voltages of the positive capacitor digital-to-analog converter and the negative capacitor digital-to-analog converter, and feeds the comparison result back to the SAR logic control unit. This comparison operation is crucial for determining whether the current approximation is correct and for determining the direction of the next adjustment.

[0145] Based on the results given by the comparator, the SAR logic control unit generates the control signal for the next stage and continues to adjust the switching state of the capacitor array until all the predetermined number of comparisons is completed or the preset accuracy requirement is reached.

[0146] Once all comparison steps are completed, the raw code generated by the SAR logic control unit is passed to the raw-to-binary module, which is responsible for converting this raw code into standard binary output code.

[0147] The final step involves further calibrating the binary output code using a BPNN calibration engine. The BPNN calibration engine contains a pre-trained neural network model that identifies and corrects errors caused by hardware non-ideals, thereby improving the overall accuracy of the signal conversion. After calibration, the output is the final calibration result, representing a high-precision digital signal representation.

[0148] This approach combines the traditional SARADC architecture with advanced machine learning techniques, ensuring not only high efficiency and accuracy in the conversion process but also simplifying hardware design and reducing power consumption and cost.

[0149] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A borrow-in successive approximation analog-to-digital converter calibrated with a backpropagation neural network, characterized by, Comprise: A positive capacitance digital-to-analog converter, a negative capacitance digital-to-analog converter, two identical bootstrap sampling switches, an auto-zero comparator, a SAR logic control unit, a raw-to-binary module, and a BPNN calibration engine; the positive capacitance digital-to-analog converter and the negative capacitance digital-to-analog converter each adopt a three-stage split bridge capacitance array; Wherein, the positive capacitance digital-to-analog converter and the negative capacitance digital-to-analog converter each have one bootstrap sampling switch at the end; The two input terminals of the comparator are respectively connected to the output terminals of the positive capacitance digital-to-analog converter and the negative capacitance digital-to-analog converter; The SAR logic control unit is connected to the output terminal of the comparator; The raw-to-binary module is connected to the SAR logic control unit, and is used to convert the raw code generated by the SAR logic control unit into the final binary output code; The BPNN calibration engine comprises a calibration module based on a back propagation neural network, which is used to receive the binary output code output by the raw-to-binary module, and perform calibration calculation through a trained neural network model to output the final result after calibration.

2. The borrowed successive approximation analog-to-digital converter employing backpropagation neural network calibration of claim 1, wherein, The positive capacitance digital-to-analog converter is redundantly designed for the most significant bit capacitance; the positive capacitance digital-to-analog converter comprises a plurality of capacitance units, each of which is connected to an input voltage, a reference voltage or ground through a switch, and the capacitance units are distributed according to binary weights.

3. The borrowed successive approximation analog-to-digital converter employing backpropagation neural network calibration of claim 2, wherein, The negative capacitance digital-to-analog converter is redundantly designed for the most significant bit capacitance; the negative capacitance digital-to-analog converter comprises a plurality of capacitance units, each of which is connected to an input voltage, a reference voltage or ground through a switch, and the capacitance units are distributed according to binary weights.

4. The borrowed successive approximation analog-to-digital converter employing backpropagation neural network calibration of claim 3, wherein, The positive capacitance digital-to-analog converter and the negative capacitance digital-to-analog converter each comprise a 2LSB virtual capacitor, which is connected to the bootstrap sampling switch.

5. The borrowed successive approximation analog-to-digital converter employing backpropagation neural network calibration of claim 1, wherein, The auto-zero comparator comprises a static four-stage preamplifier and a dynamic latch; each stage of the preamplifier adopts an auto-zero technology to reduce the offset and low-frequency flicker noise of the comparator; the output of the preamplifier is connected to the dynamic latch.

6. The borrowed successive approximation analog-to-digital converter employing backpropagation neural network calibration of claim 1, wherein, The BPNN calibration engine comprises a three-layer BP neural network, which comprises an input layer, a hidden layer and an output layer, wherein the hidden layer comprises a neuron.

7. The borrowed successive approximation analog-to-digital converter employing backpropagation neural network calibration of claim 6, wherein, The hidden layer comprises one neuron, and the BPNN calibration engine uses a linear activation function.

8. The borrowed successive approximation analog-to-digital converter employing backpropagation neural network calibration of claim 7, wherein, The calibration process of the BPNN calibration engine comprises: Interpolating the binary output code to increase the data density, and extracting the periodic error characteristics through sinusoidal fitting to form input data; The input data is passed through a BP neural network containing a single hidden layer, a linear activation function is used to simplify the calculation process, and the BP neural network optimizes the calibration performance by adjusting a limited number of weight and bias parameters, and updates the weights and biases based on the loss function feedback using the back propagation algorithm to minimize the prediction error, and outputs the final result after calibration.

9. The borrowed successive approximation analog-to-digital converter employing backpropagation neural network calibration of claim 8, wherein, The BPNN calibration engine comprises a plurality of multiplexers and an adder; the plurality of multiplexers are respectively connected to the adder.

10. A method of operating a borrowed successive approximation analog-to-digital converter employing a backpropagation neural network calibration as claimed in any one of claims 1 to 9, characterized by, Comprise: An input signal is sampled into the capacitor arrays of the positive and negative capacitor digital-to-analog converters through bootstrap sampling switches; The SAR logic control unit controls the switch states in the capacitor arrays, approximating the voltage value of the input signal successively; A comparator compares the output voltages of the positive and negative capacitor digital-to-analog converters and outputs a comparison result; The SAR logic control unit generates a control signal for the next stage according to the comparison result until all comparisons are completed; A raw-to-binary module converts the raw code generated by the SAR logic control unit into a binary output code; A BPNN calibration engine calibrates the binary output code and outputs a final calibration result.

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