brake holding circuit

Abstract

The application discloses a clutching circuit, comprising: a control circuit, generating a releasing signal and a clutching signal; a first switch circuit, a control end of which is connected with the control circuit, a first communication end of which is connected with a first end of a clutching inductor of a motor, and a second communication end of which is connected with a second end of the clutching inductor; a second switch circuit, a control end of which is connected with the control circuit, a first communication end of which is connected with the second end of the clutching inductor, and a second communication end of which is grounded; and a one-way conducting circuit, a first end of which is connected with the first communication end of the second switch circuit, and a second end of which is connected with the first communication end of the first switch circuit; the two switch circuits are turned on under the control of the releasing signal, a releasing voltage is applied to both ends of the clutching inductor based on a first power supply voltage, and the releasing is realized; in the releasing state, the second switch circuit is turned off under the control of the clutching signal, a negative voltage of the releasing voltage is applied to both ends of the clutching inductor, and the clutching is realized. The application can improve the clutching response speed of the motor and improve the coasting phenomenon.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a brake circuit. Background Technology

[0002] The holding brake is the brake for a servo motor. It is also called a holding brake, which locks the motor in place when it stops, preventing the motor from moving due to external forces, i.e., slipping.

[0003] To achieve motor braking, related technologies typically utilize 220V AC relays, 24V power relays, or MOSFET switches to control the motor's power supply. However, this method of using switches to control the power supply for motor braking suffers from slow brake response and slippage, failing to meet usage requirements. Summary of the Invention

[0004] This application provides a brake to improve the brake response speed of the motor and reduce the slippage phenomenon.

[0005] To solve the above-mentioned technical problems, this application proposes a brake circuit. The brake circuit includes: a control circuit for generating a brake release signal and a brake holding signal; a first switching circuit, the control terminal of which is connected to the control circuit, the first communication terminal of which is connected to a first power supply voltage, and the second communication terminal of which is connected to a first terminal of the brake holding inductor of the motor; a second switching circuit, the control terminal of which is connected to the control circuit, the first communication terminal of which is connected to a second terminal of the brake holding inductor, and the second communication terminal of which is grounded; and a unidirectional conduction circuit, the first terminal of which is connected to the first communication terminal of the second switching circuit, and the second terminal of which is connected to the first communication terminal of the first switching circuit, wherein the conduction direction of the unidirectional conduction circuit is from the first terminal to the second terminal; the first and second switching circuits are turned on under the control of the brake release signal to apply a brake release voltage to both ends of the brake holding inductor based on the first power supply voltage, so as to release the motor brake; in the brake release state, the second switching circuit is turned off under the control of the brake holding signal to apply a negative voltage of the brake release voltage to both ends of the brake holding inductor, so as to brake the motor.

[0006] The first switching circuit includes a first NMOS transistor. The gate of the first NMOS transistor serves as the control terminal of the first switching circuit and is connected to the control circuit. The drain of the first NMOS transistor serves as the first communication terminal of the first switching circuit and is connected to the first power supply voltage. The source of the first NMOS transistor serves as the second communication terminal of the first switching circuit and is connected to the first terminal of the brake inductor. The second switching circuit includes a second NMOS transistor. The gate of the second NMOS transistor serves as the control terminal of the second switching circuit and is connected to the control circuit. The drain of the second NMOS transistor serves as the first communication terminal of the second switching circuit and is connected to the second terminal of the brake inductor. The source of the second NMOS transistor serves as the second communication terminal of the second switching circuit and is grounded. The unidirectional conduction circuit includes a first diode. The anode of the first diode serves as the first terminal of the unidirectional conduction circuit and is connected to the drain of the second NMOS transistor. The cathode of the first diode serves as the second terminal of the unidirectional conduction circuit and is connected to the drain of the first NMOS transistor.

[0007] The brake circuit further includes: a second diode, the anode of which is connected to the source of the first NMOS transistor, and the cathode of which is connected to the drain of the first NMOS transistor; and / or a third diode, the anode of which is grounded, and the cathode of which is connected to the source of the first NMOS transistor.

[0008] The brake circuit also includes an abnormality detection circuit, which is connected to the second communication terminal of the control circuit and the second switch circuit respectively, and is used to detect whether the release of the brake is abnormal. When the release of the brake is abnormal, the control circuit controls the first switch circuit and the second switch circuit to be cut off and generates a fault signal.

[0009] The anomaly detection circuit includes: a sampling circuit connected to the second communication terminal of the second switching circuit, used to acquire the open circuit detection voltage and / or overcurrent detection voltage; an anomaly judgment circuit connected to the sampling circuit, used to determine whether there is an abnormality in the release of the brake based on the open circuit detection voltage and / or overcurrent detection voltage; and an anomaly control circuit connected to both the anomaly judgment circuit and the control circuit, used to generate an anomaly signal when there is an abnormality in the release of the brake, so that the control circuit controls the first switching circuit and the second switching circuit to turn off based on the anomaly signal and generates a fault signal.

[0010] The sampling circuit includes a first resistor, one end of which is connected to the second communication terminal of the second switching circuit, and the other end of which is grounded. One end of the first resistor is the sampling point for the open circuit detection voltage.

[0011] The sampling circuit further includes: a second resistor, one end of which is connected to a second supply voltage; a third resistor, one end of which is connected to the second supply voltage; a first NPN transistor, the base of which is connected to its collector and the other end of the second resistor; a second NPN transistor, the base of which is connected to the other end of the second resistor, and the collector of which is connected to the other end of the third resistor; a fourth resistor, one end of which is connected to one end of the first resistor and the emitter of the first NPN transistor, and the other end of which is grounded; and a fifth resistor, one end of which is connected to the emitter of the second NPN transistor, and the other end of which is grounded; wherein the other end of the third resistor serves as the sampling point for the overcurrent detection voltage.

[0012] The anomaly detection circuit includes: a disconnection detection circuit connected to the sampling circuit, used to determine whether the circuit is disconnected due to a release based on the disconnection detection voltage and the disconnection reference voltage; and / or an overcurrent detection circuit connected to the sampling circuit, used to determine whether there is an overcurrent due to a release based on the overcurrent detection voltage and the overcurrent reference voltage; and a third switching circuit connected to the disconnection detection circuit and / or the overcurrent detection circuit, used to generate a disconnection overcurrent detection signal when the circuit is disconnected due to a release and / or an overcurrent due to a release, so that the anomaly control circuit generates an anomaly signal based on the disconnection overcurrent detection signal.

[0013] The third switching circuit includes a third NPN transistor, the base of which is connected to the open circuit detection circuit and / or the overcurrent detection circuit, the emitter of which is grounded, and the collector of which is connected to the abnormal control circuit to output an open circuit overcurrent detection signal to the abnormal control circuit.

[0014] The circuit for detecting a broken wire includes: a first comparator, the first input of which is connected to a sampling circuit to receive a broken wire detection voltage, and the second input of which is connected to a broken wire reference voltage; and an XOR logic circuit, the first input of which is connected to the output of the first comparator, the second input of which is connected to a control circuit to receive a release signal, and the output of which is connected to the base of a third NPN transistor.

[0015] The overcurrent detection circuit includes: a second comparator, the first input of which is connected to the sampling circuit to receive the overcurrent detection voltage, and the second input of which is connected to the overcurrent reference voltage; and a sixth resistor, one end of which is connected to the second input of the second comparator, and the other end of which is connected to the output of the second comparator and the base of the third NPN transistor.

[0016] The abnormal control circuit includes: a fourth NPN transistor, the base of which is connected to the third switching circuit to receive the open-circuit overcurrent detection signal, and the emitter of which is grounded; a seventh resistor, one end of which is connected to the base of the fourth NPN transistor; a fourth diode, the anode of which is connected to the other end of the seventh resistor; an eighth resistor, one end of which is connected to the cathode of the fourth diode and the collector of the fourth NPN transistor, and the other end of which is connected to the control circuit; a ninth resistor, one end of which is connected to the other end of the eighth resistor, and the other end of which is connected to the control terminal of the second switching circuit, wherein the resistance of the eighth resistor is less than that of the ninth resistor; a PNP transistor, the collector of which is connected to the other end of the seventh resistor, and the emitter of which is connected to the third power supply voltage; and a fifth diode, the anode of which is connected to the base of the PNP transistor, and the cathode of which is connected to the first communication terminal of the second switching circuit.

[0017] Among them, the release brake signal and the holding brake signal are PWM signals.

[0018] The brake circuit of this application utilizes a control circuit to generate a release signal, controlling the conduction of a first and a second switching circuit connected across the brake inductor to form a release loop. This applies a release voltage to the brake inductor based on a first supply voltage, releasing the motor connected to the brake inductor. At this time, the voltage at the first terminal of the brake inductor is higher than the voltage at the second terminal. Further, in the released state, the control circuit generates a brake signal to cut off the second switching circuit. Since the current in the brake inductor cannot change abruptly, the current in the brake inductor will continue through the unidirectional conduction circuit and the first switching circuit. This continuous current signal results in a higher voltage at the second terminal of the brake inductor than at the first terminal, effectively applying a negative voltage to the brake inductor. This accelerates the energy release from the brake inductor, rapidly reducing the current and achieving rapid motor braking. Therefore, this application can improve the motor's brake response speed and reduce slippage. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0020] Figure 1 This is a schematic diagram of the structure of an embodiment of the brake circuit of this application;

[0021] Figure 2 yes Figure 1 A schematic diagram of the specific circuit structure of some structures in the embodiment;

[0022] Figure 3 yes Figure 1 A schematic diagram of the specific circuit structure of another part of the structure in the embodiment;

[0023] Figure 4 This is a schematic diagram of the structure of the motor, brake circuit, and drive circuit of this application. Detailed Implementation

[0024] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be particularly noted that the following embodiments are for illustrative purposes only and do not limit the scope of the application. Similarly, the following embodiments are only some, not all, embodiments of the present application, and all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of the present application.

[0025] In the description of the embodiments of this application, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application based on the specific circumstances.

[0026] In the embodiments of this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0027] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0028] This application first proposes a brake circuit, such as Figures 1 to 4 As shown, Figure 1 This is a schematic diagram of the structure of an embodiment of the brake circuit of this application; Figure 2 yes Figure 1 A schematic diagram of the specific circuit structure of some structures in the embodiment; Figure 3 yes Figure 1 A schematic diagram of the specific circuit structure of another part of the embodiment;

[0029] Figure 4 This is a schematic diagram of the structure of the motor, brake circuit, and drive circuit of this application. The brake circuit 10 of this embodiment includes: a control circuit 11, a first switch circuit 12, a second switch circuit 13, and a unidirectional conduction circuit 14; wherein, the control circuit 11 is used to generate a brake release signal and a brake holding signal; the control terminal of the first switch circuit 12 is connected to the control circuit 11, the first communication terminal of the first switch circuit 12 is connected to the first power supply voltage VCC1, and the second communication terminal of the first switch circuit 12 is used to connect to the first terminal of the brake inductor L of the motor M; the control terminal of the second switch circuit 13 is connected to the control circuit 11, the first communication terminal of the second switch circuit 13 is used to connect to the second terminal of the brake inductor L, and the second communication terminal of the second switch circuit 13 is grounded; unidirectional conduction... The first end of the unidirectional conduction circuit 14 is connected to the first communication end of the second switching circuit 13, and the second end of the unidirectional conduction circuit 14 is connected to the first communication end of the first switching circuit 12. The conduction direction of the unidirectional conduction circuit 14 is from the first end of the unidirectional conduction circuit 14 to the second end of the unidirectional conduction circuit 14. The first switching circuit 12 and the second switching circuit 13 are turned on under the control of the brake release signal to apply a brake release voltage to both ends of the brake inductor L based on the first supply voltage VCC1, so as to release the motor brake. In the brake release state, the second switching circuit 14 is turned off under the control of the brake holding signal to apply the negative voltage of the brake release voltage to both ends of the brake inductor L, so as to brake the motor.

[0030] The motor includes a motor body and a brake inductor L, with the motor body connected to the brake inductor L via a brake cable.

[0031] In this embodiment, the control circuit 11 generates a brake release signal to control the first switching circuit 12 and the second switching circuit 13 connected across the brake inductor L to conduct, forming a brake release circuit. This allows the first supply voltage VCC1 to be applied to the brake inductor L, thus releasing the motor brake. At this time, the voltage at the first terminal of the brake inductor L is higher than the voltage at the second terminal. Furthermore, in the brake release state, the control circuit 11 generates a brake holding signal to control the second switching circuit 13 to turn off. Since the current in the brake inductor L cannot change abruptly, the current in the brake inductor L will continue through the unidirectional conducting circuit 14 and the first switching circuit 12. This continuous current signal results in a higher voltage at the second terminal of the brake inductor L than at the first terminal, effectively applying a negative voltage of the brake release voltage across the brake inductor L. This accelerates the energy release from the brake inductor L, causing the current in the brake inductor L to drop rapidly, achieving the purpose of rapid motor brake holding. Therefore, this embodiment can improve the motor's brake response speed and reduce the slippage phenomenon.

[0032] It is important to note that Figure 4 The brake circuit in this embodiment only shows the control circuit; other circuit structures are not shown. When the motor is not working, the first switch circuit 12 and the second switch circuit 13 are cut off, there is no electrical signal on the brake inductor L, and the motor is in a braked state. When the motor needs to work, the control circuit 11 first controls the first switch circuit 12 and the second switch circuit 13 to conduct, energizing the brake inductor L, releasing the motor brake, and then controls the drive circuit 101 to output a phase voltage signal to the motor M to control the motor operation. During the operation of the motor, if it is necessary to control the motor to stop, i.e., brake, the control circuit 11 first controls the drive circuit 101 to stop outputting a phase voltage signal to the motor, and then controls the second switch circuit 13 to cut off, applying a negative voltage to the brake inductor L, causing the current on the brake inductor L to drop rapidly to zero, causing the motor to brake quickly. When the motor brake release is abnormal, the control circuit 11 controls both the first switch circuit 12 and the second switch circuit 13 to cut off, making the current on the brake inductor L zero, and keeping the motor braked.

[0033] In other embodiments, the control circuit portion of the control drive circuit can be independent of the brake circuit.

[0034] In this embodiment, the control circuit 11 can be implemented as an integrated control chip such as a micro controller unit (MCU) or a non-integrated control circuit.

[0035] Optionally, the first switching circuit 12 in this embodiment includes a first NMOS transistor Q1. The gate of the first NMOS transistor Q1 serves as the control terminal of the first switching circuit 12 and is connected to the control circuit 11. The drain of the first NMOS transistor Q1 serves as the first communication terminal of the first switching circuit 12 and is connected to the first power supply voltage VCC1. The source of the first NMOS transistor Q1 serves as the second communication terminal of the first switching circuit 12 and is used to connect to the first terminal of the brake inductor L. The second switching circuit 13 includes a second NMOS transistor Q2. The gate of the second NMOS transistor Q2 serves as the control terminal of the second switching circuit 13 and is connected to the control circuit. The drain of the second NMOS transistor Q2 serves as the first communication terminal of the second switching circuit 13 and is used to connect to the second terminal of the brake inductor L. The source of the second NMOS transistor Q2 serves as the second communication terminal of the second switching circuit 13 and is grounded. The unidirectional conduction circuit 14 includes a first diode D2. The anode of the first diode D2 serves as the first terminal of the unidirectional conduction circuit 14 and is connected to the drain of the second NMOS transistor Q2. The cathode of the first diode D2 serves as the second terminal of the unidirectional conduction circuit 14 and is connected to the drain of the first NMOS transistor Q1.

[0036] In this embodiment, the release brake signal is a pulse width modulation (PWM) signal (hereinafter referred to as the first PWM signal). The holding brake signal in this embodiment can also be a pulse width modulation (PWM) signal (hereinafter referred to as the second PWM signal).

[0037] When the motor needs to release the brake, the control circuit 11 generates a first PWM signal, controlling the first NMOS transistor Q1 and the second NMOS transistor Q2 to conduct simultaneously. The duty cycle of the first PWM signal is adjusted according to the nominal release voltage of the motor to obtain the release voltage, which is then applied to both ends of the brake inductor L to release the motor. At this time, the voltage at the first end of the brake inductor L is higher than the voltage at the second end of the brake inductor L. Furthermore, in the released state, the control circuit 11 generates a brake signal, controlling the second NMOS transistor Q2 to turn off (while keeping the first NMOS transistor Q1 on). The current in the brake inductor L will freewheel through the first diode D2 and the first NMOS transistor Q1. The voltage at the second end of this freewheeling signal is higher than the voltage at the first end of the brake inductor L, which is equivalent to applying a negative voltage of the release voltage across the brake inductor L. This can accelerate the energy release in the brake inductor L, causing the current in the brake inductor L to drop rapidly, thereby improving the brake response speed of the motor.

[0038] As can be seen from the above analysis, this embodiment can adjust the brake voltage of the motor by adjusting the duty cycle of the second PWM signal, and can adjust the release voltage of the motor by adjusting the duty cycle of the first PWM signal. Therefore, this embodiment can adjust the brake voltage and brake response time, and the release voltage and release response time of the motor.

[0039] Optionally, the brake circuit 10 in this embodiment further includes a second diode D1; wherein the anode of the second diode D1 is connected to the source of the first NMOS transistor Q1, and the cathode of the second diode D1 is connected to the drain of the first NMOS transistor Q1. The second diode D1 in this embodiment can prevent the first NMOS transistor Q1 from being damaged when the first supply voltage VCC1 is overvoltage, because the second diode D1 will break down before the first NMOS transistor Q1 is damaged.

[0040] Optionally, the brake circuit in this embodiment further includes a third diode D5, the anode of which is grounded, and the cathode of which is connected to the source of the first NMOS transistor Q1. In this embodiment, the second diode D1 can prevent the second NMOS transistor Q2 from being damaged when the first supply voltage VCC1 is overvoltage, because the third diode D5 will break down before the second NMOS transistor Q2 is damaged.

[0041] Of course, in other embodiments, the brake circuit may also selectively include a second diode D1 or a third diode D5.

[0042] It should be noted that this application's Figure 1 The second diode D1 and the third diode D5 are not shown in the diagram.

[0043] Optionally, the brake circuit in this embodiment further includes an abnormality detection circuit 15, which is connected to the second communication terminals of the control circuit 11 and the second switch circuit 13 respectively, for detecting whether the brake is abnormal. When the brake is abnormal, the control circuit 11 controls the first switch circuit 12 and the second switch circuit 13 to be cut off and generates a fault signal.

[0044] In this embodiment, an anomaly detection circuit 15 detects whether the motor brake release is abnormal. When the brake release is abnormal, the control circuit 11 controls the first switch circuit 12 and the second switch circuit 13 to cut off, thus achieving motor brake engagement and automatic brake engagement when brake release is abnormal. Furthermore, the control circuit 11 can also generate a fault signal when brake engagement is abnormal, providing an automatic alarm for brake release abnormalities.

[0045] Optionally, the anomaly detection circuit 15 of this embodiment includes: a sampling circuit 151, an anomaly judgment circuit 152, and an anomaly control circuit 153; wherein, the sampling circuit 151 is connected to the second communication terminal of the second switching circuit Q2, and is used to acquire the open circuit detection voltage IV and the overcurrent detection voltage IS; the anomaly judgment circuit 152 is connected to the sampling circuit 151, and is used to determine whether there is an abnormality in the release of the circuit based on the open circuit detection voltage IV and the overcurrent detection voltage IS; the anomaly control circuit 153 is connected to the anomaly judgment circuit 152 and the control circuit 11 respectively, and is used to generate an abnormal signal when there is an abnormality in the release of the circuit, so that the control circuit 11 controls the first switching circuit 12 and the second switching circuit 13 to be turned off based on the abnormal signal, and generates a fault signal.

[0046] As can be seen from the above analysis, when the motor is in the released state, both the first switch circuit Q1 and the second switch circuit Q2 are turned on. When the motor is in the rapid braking state, the first switch circuit Q1 is also turned on. Therefore, in this embodiment, the open circuit detection voltage IV and the overcurrent detection voltage IS in the released state can be obtained by the sampling circuit 151 connected to the second communication terminal of the second switch circuit Q2.

[0047] Optionally, the sampling circuit 151 in this embodiment includes a first resistor R1. One end of the first resistor R1 is connected to the second communication terminal of the second switching circuit Q2, and the other end of the first resistor R1 is grounded. One end of the first resistor R1 is the sampling point of the disconnection detection voltage IV.

[0048] Specifically, the first resistor R1 is connected in series between the source of the second NMOS transistor Q2 and ground. That is, the first resistor R1 is connected in series throughout the entire release circuit. Therefore, the voltage across one end of the first resistor R1, i.e., the open circuit detection voltage IV, can reflect whether an open circuit abnormality has occurred in the release circuit. If the open circuit detection voltage IV is low, it can be determined that the release circuit is open, indicating a release abnormality; if the open circuit detection voltage IV is high, it can be determined that the release circuit is not open.

[0049] Optionally, the sampling circuit 151 in this embodiment further includes: a second resistor R5, a third resistor R6, a first NPN transistor Q3, and a second NPN transistor Q4; wherein, one end of the second resistor R5 is connected to the second supply voltage VCC2; one end of the third resistor R6 is connected to the second supply voltage VCC2; the base of the first NPN transistor Q3 is connected to the collector of the first NPN transistor Q3 and the other end of the second resistor R5; the base of the second NPN transistor Q4 is connected to the other end of the second resistor R5, and the collector of the second NPN transistor Q4 is connected to the other end of the third resistor R6; one end of the fourth resistor R7 is connected to one end of the first resistor R1 and the emitter of the first NPN transistor Q3, and the other end of the fourth resistor R7 is grounded; one end of the fifth resistor R8 is connected to the emitter of the second NPN transistor Q4, and the other end of the fifth resistor R8 is grounded; wherein, the other end of the third resistor R6 serves as the sampling point for the overcurrent detection voltage IS.

[0050] In this embodiment, the second resistor R5, the third resistor R6, the first NPN transistor Q3, and the second NPN transistor Q4 constitute a two-stage amplifier circuit to amplify the open-circuit detection voltage IV at one end of the first resistor R1. As the above analysis shows, if the open-circuit detection voltage IV is a high-level voltage, it can be determined that the circuit breaker release did not result in an open circuit. However, this voltage is insufficient to determine whether there is an overcurrent during the release. Therefore, this embodiment amplifies the open-circuit detection voltage IV to accurately determine whether there is an overcurrent during the release.

[0051] The first NPN transistor Q3 is pulled down to ground through the fourth resistor R7, which prevents the first NPN transistor Q3 from malfunctioning due to noise, ensuring that the first NPN transistor Q3 is effectively grounded and reliably cut off. The second NPN transistor Q4 is pulled down to ground through the fifth resistor R8, which prevents the second NPN transistor Q4 from malfunctioning due to noise, ensuring that the second NPN transistor Q4 is effectively grounded and reliably cut off.

[0052] Furthermore, the sampling circuit 151 in this embodiment may also include diodes D6 and D7; wherein, the anode of diode D6 is connected to the emitter of the first NPN transistor Q3, and the cathode of diode D6 is connected to one end of resistor R7; the anode of diode D7 is connected to the emitter of the second NPN transistor Q4, and the cathode of diode D7 is connected to one end of resistor R8. Because the internal current of an NPN transistor changes with temperature even when the input current remains constant, this embodiment can utilize diode D6 to eliminate the influence of this characteristic on the first NPN transistor Q3, and diode D7 to eliminate the influence of this characteristic on the second NPN transistor Q4.

[0053] Of course, in other embodiments, a single-stage amplifier circuit, a two-stage or higher amplifier circuit, or an amplifier circuit with other structures can be used instead of the two-stage amplifier circuit of this embodiment.

[0054] Optionally, the anomaly judgment circuit 152 of this embodiment includes: a disconnection judgment circuit 1521, an overcurrent judgment circuit 1522, and a third switching circuit 1523; wherein, the disconnection judgment circuit 1521 is connected to the sampling circuit 11 (specifically to one end of the first resistor R1, i.e., the sampling point of the disconnection detection voltage IV), and is used to determine whether the circuit is disconnected due to shunt based on the disconnection detection voltage IV and the disconnection reference voltage REF; the overcurrent judgment circuit 1522 is connected to the sampling circuit 11 (specifically to the other end of the third resistor R6, i.e., the sampling point of the overcurrent detection voltage IS), and is used to determine whether there is an overcurrent due to shunt based on the overcurrent detection voltage IS and the overcurrent reference voltage IS_REF. The third switching circuit 1523 is connected to the disconnection judgment circuit 1521 and the overcurrent judgment circuit 1522, and is used to generate a disconnection overcurrent detection signal OI-OW-TRIP when the circuit is disconnected due to shunt or when there is an overcurrent due to shunt, so that the anomaly control circuit 152 generates an anomaly signal based on the disconnection overcurrent detection signal OI-OW-TRIP.

[0055] The third switching circuit 1523 includes a third NPN transistor Q5. The base of the third NPN transistor Q5 is connected to the open circuit detection circuit 1522 and the overcurrent detection circuit 1523. The emitter of the third NPN transistor Q5 is grounded. The collector of the third NPN transistor Q5 is connected to the abnormal control circuit 153 to output an open circuit overcurrent detection signal OI-OW-TRIP to the abnormal control circuit 153.

[0056] Furthermore, the third switching circuit 1523 also includes a resistor R14, one end of which is connected to the base of the third NPN transistor Q5, and the other end of which is connected to the emitter of the third NPN transistor Q5, for providing a voltage difference between the base and emitter of the third NPN transistor Q5.

[0057] The disconnection detection circuit 1522 includes: a first comparator U2-A and an XOR logic circuit B. The first input terminal 3 of the first comparator U2-A is connected to the sampling circuit 11 (specifically to one end of the first resistor R1, i.e., the sampling point of the disconnection detection voltage IV) to receive the disconnection detection voltage IV. The second input terminal 2 of the first comparator U2-A is connected to the disconnection reference voltage REF. The first input terminal of the XOR logic circuit B is connected to the output terminal 1 of the first comparator U2-A. The second input terminal of the XOR logic circuit B is connected to the control circuit 11 to receive the release signal HVB_GATE. The output terminal of the XOR logic circuit B is connected to the base of the third NPN transistor Q5.

[0058] In this embodiment, the first input terminal 3 of the first comparator U2-A is the positive input terminal, and the second input terminal 2 of the first comparator U2-A is the negative input terminal.

[0059] When the motor brake is released (the release signal HVB_GATE is high), and there is no disconnection or overcurrent, i.e., during normal release, the disconnection detection voltage IV is high (no disconnection), the output voltage of the first comparator U2-A is high, the release signal HVB_GATE connected to the second input terminal of the XOR logic circuit B and the output voltage of the first comparator U2-A connected to the first input terminal of the XOR logic circuit B are both high, at this time, the output voltage of the XOR logic circuit B is low; and the overcurrent detection voltage IS is low (no overcurrent), the output voltage of the second comparator U1-A is low (see the description below), the third NPN transistor Q5 is cut off, the collector of the third NPN transistor Q5 is open, and there is no disconnection overcurrent detection signal OI-OW-TRIP output.

[0060] When the motor is released from the brake and disconnected (the release signal HVB_GATE is high), the disconnection detection voltage IV is low, the output voltage of the first comparator U2-A is low, the release signal HVB_GATE connected to the second input of the XOR logic circuit B is high, and the output voltage of the first comparator U2-A connected to the first input of the XOR logic circuit B is low. At this time, the output voltage of the XOR logic circuit B is high; and the overcurrent detection voltage IS is low, the output voltage of the second comparator U1-A is low (see the description below), the third NPN transistor Q5 is turned on, and the disconnection overcurrent detection signal OI-OW-TRIP output from the collector of the third NPN transistor Q5 is low.

[0061] Brake release disconnection refers to the disconnection of the brake wire connecting the motor body and the brake inductor, or the lack of connection between the motor body and the brake inductor, or the disconnection of the wire between the brake inductor and the brake circuit, or the lack of connection between the brake inductor and the brake circuit.

[0062] Furthermore, the disconnection detection circuit 1523 in this embodiment may further include: resistors R25, R15, R13, R11, R12, R9, and R16; one end of resistor R25 is grounded, and the other end of resistor R25 is connected to the first input terminal 3 of the first comparator U2-A; one end of resistor R15 is connected to the disconnection detection voltage IV, and the other end of resistor R15 is connected to the first input terminal 3 of the first comparator U2-A, for implementing voltage division at the first input terminal 3 of the first comparator U2-A; one end of resistor R12 is connected to the slack line detection voltage IV. The gate signal HVB_GATE is used to divide the voltage in this branch. One end of resistor R12 is connected to the output of the first comparator U2-A, and the other end of resistor R11 is connected to the second input of the XOR logic circuit B. One end of resistor R9 is connected to the output of the XOR logic circuit B, and the other end of resistor R9 is connected to one end of resistor R16. The other end of resistor R16 is connected to the base of the third NPN transistor Q5.

[0063] Furthermore, the disconnection detection circuit 1523 in this embodiment may further include: a resistor R10 and a capacitor C1, one end of the resistor R10 and one end of the capacitor C1 are both connected to the other end of the resistor R9, and the other ends of the resistor R10 and the capacitor C1 are both grounded. The resistor R10 and the capacitor C1 are used to filter the signal on the branch between the output terminal of the XOR logic circuit B and the base of the third NPN transistor Q5.

[0064] The overcurrent detection circuit 1523 includes a second comparator U1-A and a sixth resistor R3. The first input terminal 3 of the second comparator U1-A is connected to the sampling circuit 11 (specifically to the other end of the third resistor R6, i.e., the sampling point of the overcurrent detection voltage IS) to receive the overcurrent detection voltage IS. The second input terminal 2 of the second comparator U1-A is connected to the overcurrent reference voltage IS_REF. One end of the sixth resistor R3 is connected to the second input terminal 2 of the second comparator U1-A, and the other end of the sixth resistor R3 is connected to the output terminal 1 of the second comparator U1-A and the base of the third NPN transistor Q5.

[0065] Furthermore, the overcurrent detection circuit 1523 may also include: resistors R2 and R4. One end of resistor R2 is connected to the sampling circuit 11, and the other end of resistor R2 is connected to the first input terminal 3 of the second comparator U1-A, for voltage division of this branch; one end of resistor R4 is connected to the output terminal 1 of the second comparator U1-A, and the other end of resistor R4 is connected to the base of the third NPN transistor Q5, for voltage division of this branch.

[0066] When the motor experiences overcurrent after brake release (the brake release signal HVB_GATE is high), the open circuit detection voltage IV is high, the output voltage of the first comparator U2-A is high, the brake release signal HVB_GATE connected to the second input terminal of the XOR logic circuit B and the output voltage of the first comparator U2-A connected to the first input terminal of the XOR logic circuit B are both high. At this time, the output voltage of the XOR logic circuit B is low. However, during overcurrent, the overcurrent detection voltage IS is high, the output voltage of the second comparator U1-A is high, and the voltage is divided by resistor R14, making the voltage difference between the base and emitter of the third NPN transistor Q5 greater than 0.7V, which is low. The third NPN transistor Q5 is turned on, and the output open circuit overcurrent detection signal OI-OW-TRIP is low.

[0067] Motor overcurrent due to brake release refers to an abnormal damage to the brake inductor L, resulting in excessive overcurrent.

[0068] When the motor is not in the brake release state, i.e., when the motor is in the brake holding state, the brake release signal HVB_GATE is low, the open circuit detection voltage IV is low, the output voltage of the first comparator U2-A is low, the brake release signal HVB_GATE connected to the second input terminal of the XOR logic circuit B is low, the output voltage of the XOR logic circuit B is low, the overcurrent detection voltage IS is low, the output voltage of the second comparator U1-A is low, the third NPN transistor Q5 is cut off, the collector of the third NPN transistor Q5 is open, and there is no open circuit overcurrent detection signal OI-OW-TRIP output.

[0069] Optionally, the abnormal control circuit 153 of this embodiment includes: a fourth NPN transistor Q6, a seventh resistor R21, a fourth diode D11, an eighth resistor R24, a ninth resistor R23, a PNP transistor Q7, and a fifth diode D8; wherein, the base of the fourth NPN transistor Q6 is connected to the third switching circuit 1523 (specifically to the collector of the third NPN transistor Q5) to receive the open-circuit overcurrent detection signal OI-OW-TRIP, and the emitter of the fourth NPN transistor Q6 is grounded; one end of the seventh resistor R21 is connected to the base of the fourth NPN transistor Q6; the anode of the fourth diode D11 is connected to the other end of the seventh resistor R21; one end of the eighth resistor R24 ​​is connected to the cathode of the fourth diode D11 and... The collector of the fourth NPN transistor Q6 is connected to the control circuit 11, and the other end of the eighth resistor R24 ​​is connected to the control circuit 11. One end of the ninth resistor R23 is connected to the other end of the eighth resistor R24, and the other end of the ninth resistor R23 is connected to the control terminal (gate of the second NMOS transistor Q2) of the second switching circuit 13. The resistance of the eighth resistor R24 ​​is less than the resistance of the ninth resistor R23. The collector of the PNP transistor Q7 is connected to the other end of the seventh resistor R21, and the emitter of the PNP transistor Q7 is connected to the third power supply voltage VCC3. The anode of the fifth diode D8 is connected to the base of the PNP transistor Q7, and the cathode of the fifth diode D8 is connected to the first communication terminal of the second switching circuit (drain of the second NMOS transistor Q2).

[0070] Furthermore, the abnormal control circuit 153 of this embodiment may further include: resistor R22, capacitor C5, resistor R17, resistor R18, resistor R19, resistor R20, and a sixth diode D3; wherein, one end of resistor R22 and one end of capacitor C5 are connected to the base of the fourth NPN transistor Q6, and the other end of resistor R22 and the other end of capacitor C5 are connected to the emitter of the fourth NPN transistor Q6, for filtering the open-circuit overcurrent detection signal OI-OW-TRIP and providing a voltage difference between the base and emitter of the fourth NPN transistor Q6; one end of resistor R19 is connected to the PNP transistor Q7. The base is connected, and the other end of resistor R19 is connected to the emitter of PNP transistor Q7 to provide a voltage difference between the base and emitter of PNP transistor Q7; one end of resistor R18 is connected to the base of PNP transistor Q7, the other end of resistor R18 is connected to one end of resistor R17, the other end of resistor R17 is connected to one end of resistor R20, and the other end of resistor R20 is connected to the anode of the fifth diode D8 for voltage division in this branch; the anode of the sixth diode D3 is connected to the other end of resistor R17, and the cathode of the sixth diode D3 is connected to the emitter of PNP transistor Q7 to prevent PNP transistor Q7 from being overvoltage-damaged.

[0071] When the second NMOS transistor Q2 is working normally, its drain voltage VCE is low and the PNP transistor Q7 is turned on; when the first NMOS transistor Q1 and the second NMOS transistor Q2 are short-circuited or the brake inductor L is short-circuited, the drain voltage VCE of the second NMOS transistor Q2 is high and the PNP transistor Q7 is turned off.

[0072] When the motor is in the released brake state, the release brake signal HVB_GATE is high, the first NMOS transistor Q1 and the second NMOS transistor Q2 are turned on simultaneously, the release brake voltage is applied to the brake inductor L, the motor is released and can run, the disconnection overcurrent signal OI-OW-TRIP is high, the drain voltage VCE of the second NMOS transistor Q2 is low, the PNP transistor Q7 is turned on, so that the third supply voltage VCC3 turns on the fourth NPN transistor Q6 through the PNP transistor Q7, the seventh resistor R21, and the resistor R22. At this time, the collector of the fourth NPN transistor Q6 is low. Since the resistance value of the eighth resistor R24 ​​is less than that of the ninth resistor R23, the voltage DESAT at the other end of the eighth resistor R24 ​​is low after being divided by the release brake signal HVB_GATE through the ninth resistor R23. At this time, the control circuit 11 normally drives the second NMOS transistor Q2.

[0073] When the brake release circuit is disconnected or there is an overcurrent during brake release, the disconnection overcurrent detection signal OI_OW_TRIP is low, the fourth NPN transistor Q6 is cut off, so that the third supply voltage VCC3 is supplied to the collector of the fourth NPN transistor Q6 through the PNP transistor Q7 and the fourth diode D11. The collector of the fourth NPN transistor Q6 is high. The voltage DESAT at the other end of the eighth resistor R24 ​​is high after being divided by the brake release signal HVB_GATE through the ninth resistor R23. At this time, the control circuit 11 reports an error and simultaneously turns off the first NMOS transistor Q1 and the second NMOS transistor Q2, thereby keeping the motor in a brake-holding state.

[0074] When the first NMOS transistor Q1 and the second NMOS transistor Q2 are short-circuited, or the brake inductor L is short-circuited (or other parts of the brake release circuit are short-circuited), the drain voltage VCE of the second NMOS transistor Q2 is high, the PNP transistor Q7 is cut off, the open-circuit overcurrent detection signal OI_OW_TRIP is low, the fourth NPN transistor Q6 is cut off, and the fourth diode D11 is not conducting. At this time, the voltage DESAT divided by HVB_GATE through the resistor is high, and the voltage DESAT at the other end of the eighth resistor R24 ​​is high after the brake release signal HVB_GATE is divided by the ninth resistor R23. At this time, the control circuit 11 reports an error and simultaneously shuts down the first NMOS transistor Q1 and the second NMOS transistor Q2, thereby keeping the motor in a brake-holding state.

[0075] In other embodiments, corresponding circuits can be selectively configured based on the needs of the actual application to selectively obtain the disconnection detection voltage or the overcurrent detection voltage.

[0076] In other embodiments, other types of switching transistors may be used instead of the aforementioned switching transistors, or other types of switching transistors of the same kind (P-channel, N-channel) may be used instead of the aforementioned switching terminals, and the circuit may be adapted accordingly.

[0077] The brake circuit of this application includes: a control circuit for generating a brake release signal and a brake holding signal; a first switching circuit, the control terminal of which is connected to the control circuit, the first communication terminal of which is connected to a first power supply voltage, and the second communication terminal of which is connected to a first terminal of the brake holding inductor of the motor; a second switching circuit, the control terminal of which is connected to the control circuit, the first communication terminal of which is connected to a second terminal of the brake holding inductor, and the second communication terminal of which is grounded; and a unidirectional conduction circuit, the first terminal of which is connected to the first communication terminal of the second switching circuit, and the second terminal of which is connected to the first communication terminal of the first switching circuit, wherein the conduction direction of the unidirectional conduction circuit is from the first terminal to the second terminal; the first and second switching circuits are turned on under the control of the brake release signal to apply a brake release voltage to both ends of the brake holding inductor based on the first power supply voltage, so as to release the motor brake; in the brake release state, the second switching circuit is turned off under the control of the brake holding signal to apply a negative voltage of the brake release voltage to both ends of the brake holding inductor, so as to brake the motor. The brake circuit of this application utilizes a control circuit to generate a release signal, controlling the conduction of a first and a second switching circuit connected across the brake inductor to form a release loop. This applies a release voltage to the brake inductor based on a first supply voltage, releasing the motor connected to the brake inductor. At this time, the voltage at the first terminal of the brake inductor is higher than the voltage at the second terminal. Further, in the released state, the control circuit generates a brake signal to cut off the second switching circuit. Since the current in the brake inductor cannot change abruptly, the current in the brake inductor will continue through the unidirectional conduction circuit and the first switching circuit. This continuous current signal results in a higher voltage at the second terminal of the brake inductor than at the first terminal, effectively applying a negative voltage to the brake inductor. This accelerates the energy release from the brake inductor, rapidly reducing the current and achieving rapid motor braking. Therefore, this application can improve the motor's brake response speed and reduce slippage.

[0078] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A brake circuit, characterized in that, include: The control circuit is used to generate the brake release signal and the brake holding signal. A first switching circuit, wherein the control terminal of the first switching circuit is connected to the control circuit, the first communication terminal of the first switching circuit is connected to the first power supply voltage, and the second communication terminal of the first switching circuit is used to connect to the first terminal of the brake inductor of the motor. A second switching circuit, the control terminal of the second switching circuit is connected to the control circuit, the first communication terminal of the second switching circuit is used to connect to the second terminal of the brake inductor, and the second communication terminal of the second switching circuit is grounded; A unidirectional conduction circuit, wherein a first end of the unidirectional conduction circuit is connected to a first communication terminal of a second switching circuit, and a second end of the unidirectional conduction circuit is connected to a first communication terminal of the first switching circuit, wherein the conduction direction of the unidirectional conduction circuit is from the first end of the unidirectional conduction circuit to the second end of the unidirectional conduction circuit. The first switching circuit and the second switching circuit are configured to be turned on under the control of the brake release electrical signal, so as to apply a brake release voltage to both ends of the brake inductor based on the first power supply voltage, so as to release the motor brake; in the brake release state, the second switching circuit is configured to be turned off under the control of the brake brake electrical signal, so as to apply the negative voltage of the brake release voltage to both ends of the brake inductor, so as to brake the motor. The brake circuit further includes: An anomaly detection circuit is connected to the second communication terminal of the control circuit and the second switching circuit, respectively, and is used to detect whether the brake release is abnormal. When the brake release is abnormal, the control circuit controls the first switching circuit and the second switching circuit to be cut off and generates a fault signal.

2. The brake circuit according to claim 1, characterized in that, The first switching circuit includes a first NMOS transistor. The gate of the first NMOS transistor serves as the control terminal of the first switching circuit and is connected to the control circuit. The drain of the first NMOS transistor serves as the first communication terminal of the first switching circuit and is connected to the first power supply voltage. The source of the first NMOS transistor serves as the second communication terminal of the first switching circuit and is used to connect to the first terminal of the brake inductor. The second switching circuit includes a second NMOS transistor. The gate of the second NMOS transistor serves as the control terminal of the second switching circuit and is connected to the control circuit. The drain of the second NMOS transistor serves as the first communication terminal of the second switching circuit and is connected to the second terminal of the holding brake inductor. The source of the second NMOS transistor serves as the second communication terminal of the second switching circuit and is grounded. The unidirectional conduction circuit includes a first diode, the anode of the first diode is connected to the drain of the second NMOS transistor as the first terminal of the unidirectional conduction circuit, and the cathode of the first diode is connected to the drain of the first NMOS transistor as the second terminal of the unidirectional conduction circuit.

3. The brake circuit according to claim 2, characterized in that, Also includes: The second diode has its anode connected to the source of the first NMOS transistor and its cathode connected to the drain of the first NMOS transistor. and / or The third diode has its anode grounded and its cathode connected to the source of the first NMOS transistor.

4. The brake circuit according to claim 1, characterized in that, The anomaly detection circuit includes: A sampling circuit, which is connected to the second communication terminal of the second switching circuit, is used to acquire the open circuit detection voltage and / or overcurrent detection voltage. An anomaly detection circuit, connected to the sampling circuit, is used to determine whether a circuit breaker release anomaly is present based on the open circuit detection voltage and / or the overcurrent detection voltage. An abnormal control circuit is connected to both the abnormal judgment circuit and the control circuit. It is used to generate an abnormal signal when the brake release is abnormal, so that the control circuit controls the first switch circuit and the second switch circuit to be turned off based on the abnormal signal, and generates the fault signal.

5. The brake circuit according to claim 4, characterized in that, The sampling circuit includes: A first resistor, one end of which is connected to the second communication terminal of the second switching circuit, and the other end of which is grounded, wherein one end of the first resistor is the sampling point of the disconnection detection voltage.

6. The brake circuit according to claim 5, characterized in that, The sampling circuit also includes: The second resistor, one end of which is connected to the second power supply voltage; A third resistor, one end of which is connected to the second power supply voltage; The base of the first NPN transistor is connected to the collector of the first NPN transistor and the other end of the second resistor. The base of the second NPN transistor is connected to the other end of the second resistor, and the collector of the second NPN transistor is connected to the other end of the third resistor. A fourth resistor, one end of which is connected to one end of the first resistor and the emitter of the first NPN transistor, and the other end of which is grounded; The fifth resistor has one end connected to the emitter of the second NPN transistor, and the other end grounded. The other end of the third resistor serves as the sampling point for the overcurrent detection voltage.

7. The brake circuit according to claim 4, characterized in that, The anomaly detection circuit includes: A disconnection detection circuit, connected to the sampling circuit, is used to determine whether a disconnection has occurred based on the disconnection detection voltage and the disconnection reference voltage; and / or An overcurrent detection circuit, connected to the sampling circuit, is used to determine whether there is a release overcurrent based on the overcurrent detection voltage and the overcurrent reference voltage. The third switching circuit is connected to the disconnection judgment circuit and / or the overcurrent judgment circuit, and is used to generate a disconnection overcurrent detection signal when the circuit is released and / or when the circuit is released and there is an overcurrent, so that the abnormal control circuit generates the abnormal signal based on the disconnection overcurrent detection signal.

8. The brake circuit according to claim 7, characterized in that, The third switching circuit includes: a third NPN transistor, the base of which is connected to the open circuit detection circuit and / or the overcurrent detection circuit, the emitter of which is grounded, and the collector of which is connected to the abnormal control circuit to output the open circuit overcurrent detection signal to the abnormal control circuit.

9. The brake circuit according to claim 8, characterized in that, The disconnection detection circuit includes: A first comparator, the first input terminal of the first comparator is connected to the sampling circuit to receive the open circuit detection voltage, and the second input terminal of the first comparator is connected to the open circuit reference voltage; An XOR logic circuit is provided, wherein the first input terminal of the XOR logic circuit is connected to the output terminal of the first comparator, the second input terminal of the XOR logic circuit is connected to the control circuit to receive the release signal, and the output terminal of the XOR logic circuit is connected to the base of the third NPN transistor.

10. The brake circuit according to claim 8, characterized in that, The overcurrent detection circuit includes: The second comparator has its first input terminal connected to the sampling circuit to receive the overcurrent detection voltage, and its second input terminal connected to the overcurrent reference voltage. The sixth resistor has one end connected to the second input terminal of the second comparator and the other end connected to the output terminal of the second comparator and the base of the third NPN transistor.

11. The brake circuit according to claim 7, characterized in that, The anomaly control circuit includes: The fourth NPN transistor has its base connected to the third switching circuit to receive the open circuit overcurrent detection signal, and its emitter is grounded. The seventh resistor, one end of which is connected to the base of the fourth NPN transistor; The fourth diode, the anode of which is connected to the other end of the seventh resistor; The eighth resistor has one end connected to the cathode of the fourth diode and the collector of the fourth NPN transistor, and the other end connected to the control circuit. A ninth resistor, one end of which is connected to the other end of the eighth resistor, and the other end of which is connected to the control terminal of the second switching circuit, wherein the resistance value of the eighth resistor is less than the resistance value of the ninth resistor; The PNP transistor has its collector connected to the other end of the seventh resistor, and its emitter connected to the third power supply voltage. The fifth diode has its anode connected to the base of the PNP transistor and its cathode connected to the first communication terminal of the second switching circuit.

12. The brake circuit according to any one of claims 1 to 10, characterized in that, The release and holding brake signals are PWM signals.

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