Clock data recovery circuit and method, and display panel

Abstract

The present invention provides a clock data recovery circuit and method, and a display panel. The phase detector of the clock data recovery circuit performs baud rate sampling on a data stream sent by a front-end system through a data sampling module to obtain an initial data code; then, a data comparison module is used to determine whether the flip edge of the initial data code reaches a preset threshold. When the number of flip edges of the initial data code does not reach the preset threshold, the initial data code is modified or replaced through a data correction module so that the number of flip edges of the modified initial data code, i.e., the corrected data code, reaches the preset threshold, thereby ensuring that the number of flip edges of the data code input by the front-end system can reach the preset threshold, increasing the locking capability and anti-interference capability of the clock data recovery circuit, and avoiding the problem of the clock data recovery circuit losing lock and causing data transmission failure under low temperature or severe interference conditions.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a clock data recovery circuit and method, and a display panel. Background Art

[0002] Usually, a timing controller controls the gate drive circuit or source drive circuit on the driver chip to enable the display panel to display. The driver chip needs to lock the signal through the clock recovery (CDR) circuit and the timing controller. The clock data recovery circuit mainly relies on the flip edge of the data code sent by the timing controller to the driver chip to trigger the judgment and implement the tracking lock action. Therefore, the greater the flip rate of the data code, the faster the response speed of the clock data recovery circuit, which makes the loop bandwidth of the clock data recovery circuit larger.

[0003] However, during the data transmission process, the data encoding may be a long 0 or long 1 pattern, such as 9b encoded 111100001, and there are only two data flip edges (1 to 0 or 0 to 1), that is, the clock data recovery circuit can only rely on these two flip edges to implement tracking lock, and may not achieve the tracking lock effect. Especially in low temperature or severe interference conditions, the transmitted data may be further affected, and some of the data may be lost, resulting in fewer flip edges, which directly causes the clock data recovery circuit to lose lock, and the driver chip cannot receive normal data from the timing controller, resulting in data transmission failure.

[0004] That is, under low temperature or severe interference conditions, the current clock data recovery circuit may lose lock for data encoding with fewer flip edges, resulting in the risk of data transmission failure. Summary of the Invention

[0005] In order to solve the above problems, embodiments of the present invention provide a clock data recovery circuit and method, and a display panel.

[0006] In a first aspect, an embodiment of the present invention provides a clock data recovery circuit, comprising a phase detector, wherein the phase detector comprises a data sampling module, a data comparison module, and a data correction module connected in sequence;

[0007] The data sampling module is used to perform baud rate sampling on the data stream input by the front-end system to obtain the initial data code;

[0008] The data comparison module is used to determine whether the number of flip edges of the initial data code reaches a preset threshold, and the preset threshold is a value not less than 1;

[0009] The data correction module is used to modify or replace the initial data code to output a corrected data code when the number of flip edges of the initial data code does not reach the preset threshold, and the number of flip edges of the corrected data code reaches the preset threshold.

[0010] In some embodiments, the data correction module stores a virtual data code, the number of flip edges of the virtual data code reaches the preset threshold, and the virtual data code is used to replace the initial data code as the correction data code.

[0011] In some embodiments, the phase detector further includes an edge sampling module and a phase calibration module; wherein the time interval between the nth edge sampling clock of the edge sampling module and the n-1th data sampling clock and the nth data sampling clock of the data correction module is 1 / 2 of the coding interval; and the phase calibration module is used to respectively compare the relationship between the sampling result of the edge sampling module at the nth edge sampling clock and the sampling result of the data correction module at the n-1th data sampling clock and the sampling result of the data correction module at the nth data sampling clock, so as to adjust the phase of the data sampling clock of the data correction module.

[0012] In some embodiments, the phase calibration module includes a phase comparison unit and a phase adjustment unit; wherein the phase comparison unit is used to compare the sampling result of the edge sampling module at the nth edge sampling clock with the sampling result of the data correction module at the n-1th data sampling clock, and to compare the sampling result of the edge sampling module at the nth edge sampling clock with the sampling result of the data correction module at the nth data sampling clock, so as to determine whether the phase of the data sampling clock of the data correction module is advanced or delayed; and the phase adjustment unit is used to adjust the phase of the data sampling clock of the data correction module according to the advance or lag of the data sampling clock of the data correction module.

[0013] In some embodiments, the clock data recovery circuit further includes a loop filter and a voltage-controlled oscillator connected in sequence to the phase detector; wherein the loop filter is used to perform integration and comparison based on the data stream to obtain a DC voltage; and the voltage-controlled oscillator is used to output a clock signal to the phase detector under the control of the DC voltage.

[0014] In some embodiments, the clock data recovery circuit operates in a field blanking phase or a line blanking phase during data transmission.

[0015] In a second aspect, an embodiment of the present invention further provides a clock data recovery method, characterized by comprising:

[0016] Perform baud rate sampling on the data stream input by the front-end system to obtain the initial data encoding;

[0017] Determine whether the number of flip edges of the initial data code reaches a preset threshold, where the preset threshold is a value not less than 1;

[0018] If the number of flip edges of the initial data code does not reach the preset threshold, the initial data code is modified or replaced to output a corrected data code, and the number of flip edges of the corrected data code reaches the preset threshold.

[0019] In some embodiments, modifying the initial data encoding includes:

[0020] Modify any number of bits in consecutive bytes of the same value in the initial data code so that the number of flip edges of the modified initial data code reaches a preset threshold, and use the modified initial data code as the correction data code.

[0021] In some embodiments, replacing the initial data encoding includes:

[0022] The initial data code is replaced by a dummy data code to serve as the correction data code; wherein the number of flip edges of the dummy data code exceeds a preset threshold.

[0023] In a third aspect, an embodiment of the present invention further provides a display panel, comprising a driver chip and a timing controller, wherein the driver chip comprises the clock data recovery circuit as described above, and the clock data recovery circuit is used to lock the clock data between the driver chip and the timing controller.

[0024] The clock data recovery circuit and method, and display panel provided by the embodiments of the present invention have a phase detector in the clock data recovery circuit that performs baud rate sampling on the data stream sent by the front-end system through a data sampling module to obtain an initial data code; then, a data comparison module is used to determine whether the flip edge of the initial data code reaches a preset threshold; when the number of flip edges of the initial data code does not reach the preset threshold, the initial data code is modified or replaced by a data correction module so that the number of flip edges of the modified initial data code, i.e., the corrected data code, reaches the preset threshold, thereby ensuring that the number of flip edges of the data code input by the front-end system can reach the preset threshold, increasing the locking capability and anti-interference capability of the clock data recovery circuit, and avoiding the problem of the clock data recovery circuit losing lock and causing data transmission failure under low temperature or severe interference conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The technical solutions and other beneficial effects of the present invention will be made apparent by describing in detail the specific embodiments of the present invention in conjunction with the accompanying drawings.

[0026] Figure 1 A schematic structural diagram of a phase detector in a clock data recovery circuit provided by an embodiment of the present invention;

[0027] Figure 2 Another structural diagram of a phase detector in a clock data recovery circuit provided by an embodiment of the present invention;

[0028] Figure 3 A schematic structural diagram of a phase comparison module of a phase detector in a clock data recovery circuit provided by an embodiment of the present invention;

[0029] Figure 4 A phase diagram of a clock data recovery circuit in the prior art that does not respond;

[0030] Figure 5 A first phase diagram of a clock data recovery circuit provided by an embodiment of the present invention;

[0031] Figure 6 A second phase diagram of the clock data recovery circuit provided by an embodiment of the present invention;

[0032] Figure 7 A third phase diagram of the clock data recovery circuit provided by an embodiment of the present invention;

[0033] Figure 8 A schematic structural diagram of a clock data recovery circuit provided in an embodiment of the present invention;

[0034] Figure 9 A schematic flow chart of a clock data recovery method provided in an embodiment of the present invention;

[0035] Figure 10 A schematic structural diagram of a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0036] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0037] like Figure 1 As shown, an embodiment of the present invention provides a clock data recovery circuit, including a phase detector 10, wherein the phase detector 10 includes a data sampling module 101, a data comparison module 102 and a data correction module 103 connected in sequence;

[0038] The data sampling module 101 is used to perform baud rate sampling on the data stream input by the front-end system to obtain the initial data code;

[0039] The data comparison module 102 is used to determine whether the number of flip edges of the initial data code reaches a preset threshold, and the preset threshold is a value not less than 1;

[0040] The data correction module 103 is configured to modify or replace the initial data code to output a corrected data code when the number of flip edges of the initial data code does not reach the preset threshold, wherein the number of flip edges of the corrected data code reaches the preset threshold.

[0041] The initial data code and the correction data code in the embodiment of the present invention are both binary codes, that is, composed of 0 and 1.

[0042] Specifically, the preset threshold is a numerical value that is manually preset, and the preset threshold is a numerical value that is not less than 1. Corresponding preset thresholds are set for codes of different lengths. For example, for a 9b code, the preset threshold is set to 3. In this case, at least three flip edges are required in the data code. That is, if the initial data code is 111100001 and has only two flip edges, at least one flip edge must be added to ensure that the clock data recovery circuit does not lose lock. In this case, the initial data code is modified or replaced to output a correction data code with at least three flip edges, so that the clock data at the receiving and transmitting ends can remain locked.

[0043] It should be noted that if the number of flip edges of the initial correction code reaches a preset threshold, the data correction module 103 directly outputs the initial data code.

[0044] The phase detector 10 of the clock data recovery circuit provided in the embodiment of the present invention performs baud rate sampling on the data stream sent by the front-end system through the data sampling module 101 to obtain the initial data code; then, the data comparison module 102 is used to determine whether the flip edge of the initial data code reaches a preset threshold value. When the number of flip edges of the initial data code does not reach the preset threshold value, the initial data code is modified or replaced by the data correction module 103 so that the number of flip edges of the modified initial data code, i.e., the corrected data code, reaches the preset threshold value, thereby ensuring that the number of flip edges of the data code input by the front-end system can reach the preset threshold value, increasing the locking capability and anti-interference capability of the clock data recovery circuit, and avoiding the problem of the clock data recovery circuit losing lock and causing data transmission failure under low temperature or severe interference conditions.

[0045] The data correction module 103 stores a virtual data code, the number of flip edges of the virtual data code reaches the preset threshold, and the virtual data code is used to replace the initial data code as the correction data code. For example, if the preset threshold is 3, the virtual data code is stored as 101100001, and the number of flip edges reaches 3, which reaches the preset threshold. If the initial data code is 111100001, the virtual data code 101100001 replaces 111100001 as the correction data code, so that the number of flip edges of the final correction data code reaches 3; alternatively, the initial data code 111100001 can be modified to 101100001 as the correction code through the data correction module 103, which can also make the number of flip edges of the final correction data code reach 3, that is, the individual values ​​in the long 0 long 1 part are modified to the opposite values, thereby increasing the number of flip edges.

[0046] like Figure 4 As shown, in the prior art, a clock data recovery circuit compares the sampling results corresponding to the data sampling clock and the sampling results corresponding to the edge sampling clock to determine whether the phase of the data sampling clock is advanced or delayed, thereby adjusting the phase of the data sampling clock to lock the clock data of the clock data recovery circuit. However, if the initial data encoding does not have a flip edge, when comparing the sampling results Dn-1 and Dn corresponding to the data sampling clocks CKDn-1 and CKDn, and the sampling result EN corresponding to the edge sampling clock CKEn, it is impossible to determine the relationship between Dn-1 and EN, and between Dn and En. If interference occurs at this time, causing the phase of the data sampling clock to deviate, the clock data recovery circuit will be unable to detect whether the phase of the data sampling clock is advanced or delayed, resulting in an inability to adjust the phase of the data sampling clock, causing the clock data recovery circuit to lose clock data lock. Furthermore, if the number of flip edges is insufficient, interference may occur during the clock data training process, which may also cause the above situation, resulting in data transmission failure.

[0047] In view of this, an embodiment of the present invention selects whether to modify or replace the initial data code based on whether the number of flip edges of the initial data code reaches a preset threshold value to obtain a corrected data code whose flip edges reach the preset threshold value. That is, the phase detector 10 of the embodiment of the present invention then performs subsequent work on the corrected data code output by the data correction module 103.

[0048] Combine Figure 2 and Figure 4 As shown, the phase detector 10 of the clock data recovery circuit provided by the embodiment of the present invention further includes an edge sampling module 104 and a phase calibration module 105; wherein, as Figure 5 、 Figure 6 and Figure 7As shown, the time interval between the nth edge sampling clock CKEn of the edge sampling module 104 and the n-1th data sampling clock CKDn-1 and the nth data sampling clock CKDn of the data correction module 103 is 1 / 2 of the coding interval; the phase calibration module 105 is used to respectively compare the relationship between the sampling result En of the edge sampling module 104 at the nth edge sampling clock CKEn and the sampling result Dn-1 of the data correction module 103 at the n-1th data sampling clock CKDn-1 and the sampling result Dn of the data correction module 103 at the n-1th data sampling clock CKDn, so as to adjust the phase of the data sampling clock of the data correction module 103.

[0049] Among them, such as Figure 3 As shown, the phase calibration module 105 includes a phase comparison unit 1051 and a phase adjustment unit 1052; the phase comparison unit 1051 is used to compare the sampling result En of the edge sampling module 104 at the nth edge sampling clock CKEn with the sampling result Dn-1 of the data correction module 103 at the n-1th data sampling clock CKDn-1, and compare the sampling result En of the edge sampling module 104 at the nth edge sampling clock CKEn with the sampling result Dn of the data correction module 103 at the nth data sampling clock CKDn, so as to determine whether the phase of the data sampling clock of the data correction module 103 is advanced or delayed; the phase adjustment unit 1052 is used to adjust the phase of the data sampling clock of the data correction module 103 according to the advance or lag of the data sampling clock of the data correction module 103.

[0050] Specifically, compare Dn-1 and En, and the relationship between Dn and En. If Dn-1 and En are the same, but Dn and En are different, it means that the phase of the data sampling clock of the data correction module 103 is ahead, and the phase of the data sampling clock of the data correction module 103 needs to be slowed down to achieve the optimal sampling position, such as Figure 5 If Dn-1 and En are different, and Dn and En are the same, it means that the phase of the data sampling clock of the data correction module 103 is delayed, and the phase of the data sampling clock of the data correction module 103 needs to be faster to achieve the optimal sampling position, such as Figure 6 If Dn-1 and En are the same, and Dn and En are also the same, it means that the phase of the data sampling clock of the data correction module 103 is already in the optimal sampling position, such as Figure 7 shown.

[0051] Based on the above embodiments, Figure 8As shown, the clock data recovery circuit further includes a loop filter 20 and a voltage-controlled oscillator 30 connected in sequence to the phase detector 10; the loop filter 20 is used to perform integration and comparison according to the data stream to obtain a DC voltage; the voltage-controlled oscillator 30 is used to output a clock signal to the phase detector 10 under the control of the DC voltage.

[0052] It should be noted that the clock data recovery circuit operates during the vertical blanking phase (Vblank) or the horizontal blanking phase (Bblank) during data transmission. That is, the clock data recovery circuit performs a clock data training process during the vertical blanking phase or the horizontal blanking phase to lock the clock data between the receiving end and the transmitting end.

[0053] like Figure 9 As shown, an embodiment of the present invention further provides a clock data recovery method, characterized by comprising:

[0054] S1. Perform baud rate sampling on the data stream input by the front-end system to obtain the initial data code;

[0055] S2. Determine whether the number of flip edges of the initial data code reaches a preset threshold;

[0056] S3. If the number of flip edges of the initial data code does not reach the preset threshold, modify or replace the initial data code to output a corrected data code, wherein the number of flip edges of the corrected data code reaches the preset threshold.

[0057] The clock data recovery circuit method provided by the embodiment of the present invention performs baud rate sampling on the data stream sent by the front-end system to obtain the initial data code, and then determines whether the flip edge of the initial data code reaches a preset threshold. When the number of flip edges of the initial data code does not reach the preset threshold, the initial data code is modified or replaced so that the number of flip edges of the modified initial data code, i.e., the correction data code, reaches the preset threshold, thereby ensuring that the number of flip edges of the data code input by the front-end system can reach the preset threshold, increasing the tracking lock capability and anti-interference capability of the clock data recovery circuit, and avoiding the problem of the clock data recovery circuit losing lock and causing data transmission failure under low temperature or severe interference conditions.

[0058] In some embodiments, modifying the initial data encoding includes:

[0059] Modify any number of bits in consecutive bytes of the same value in the initial data code so that the number of flip edges of the modified initial data code reaches a preset threshold, and use the modified initial data code as the correction data code.

[0060] In some embodiments, replacing the initial data encoding includes:

[0061] The initial data code is replaced by a dummy data code to serve as the correction data code; wherein the number of flip edges of the dummy data code exceeds a preset threshold.

[0062] Based on the above embodiments, Figure 10 As shown, an embodiment of the present invention further provides a display panel, including a driver chip 1 and a timing controller 2. The driver chip 1 includes the clock data recovery circuit 3 described above. The clock data recovery circuit 3 is used to lock the clock data between the driver chip 1 and the timing controller 2. Since the clock data recovery circuit 3 has been described in detail in the above embodiments, it will not be repeated here.

[0063] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0064] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present invention; ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A clock data recovery circuit, characterized in that: It includes a phase detector, which includes a data sampling module, a data comparison module and a data correction module connected in sequence; The data sampling module is used to perform baud rate sampling on the data stream input by the front-end system to obtain the initial data code; The data comparison module is used to determine whether the number of flip edges of the initial data code reaches a preset threshold, and the preset threshold is a value not less than 1; The data correction module is used to modify or replace the initial data code to output a corrected data code when the number of flip edges of the initial data code does not reach the preset threshold, and the number of flip edges of the corrected data code reaches the preset threshold.

2. The clock data recovery circuit according to claim 1, wherein: The data correction module stores a virtual data code, the number of flip edges of the virtual data code reaches the preset threshold, and the virtual data code is used to replace the initial data code to serve as the correction data code.

3. The clock data recovery circuit according to claim 1, wherein: The phase detector further includes an edge sampling module and a phase calibration module; wherein the time interval between the nth edge sampling clock of the edge sampling module and the n-1th data sampling clock and the nth data sampling clock of the data correction module is 1 / 2 of the coding interval; The phase calibration module is used to respectively compare the sampling result of the edge sampling module at the nth edge sampling clock with the sampling result of the data correction module at the n-1th data sampling clock and the sampling result of the data correction module at the nth data sampling clock, so as to adjust the phase of the data sampling clock of the data correction module.

4. The clock data recovery circuit according to claim 3, wherein: The phase calibration module includes a phase comparison unit and a phase adjustment unit; The phase comparison unit is configured to compare the sampling result of the edge sampling module at the nth edge sampling clock with the sampling result of the data correction module at the n-1th data sampling clock, and to compare the sampling result of the edge sampling module at the nth edge sampling clock with the sampling result of the data correction module at the nth data sampling clock, so as to determine whether the phase of the data sampling clock of the data correction module is advanced or delayed; The phase adjustment unit is configured to adjust the phase of the data sampling clock of the data correction module according to whether the data sampling clock of the data correction module is advanced or delayed.

5. The clock data recovery circuit according to claim 1, wherein: It also includes a loop filter and a voltage-controlled oscillator connected in sequence to the phase detector; The loop filter is used to perform integration and comparison according to the data stream to obtain a DC voltage; The voltage-controlled oscillator is used to output a clock signal to the phase detector under the control of the DC voltage.

6. The clock data recovery circuit according to claim 1, wherein: The clock data recovery circuit operates in a field blanking phase or a line blanking phase during data transmission.

7. A clock data recovery method, characterized in that: include: Perform baud rate sampling on the data stream input by the front-end system to obtain the initial data encoding; Determine whether the number of flip edges of the initial data code reaches a preset threshold, where the preset threshold is a value not less than 1; If the number of flip edges of the initial data code does not reach the preset threshold, the initial data code is modified or replaced to output a corrected data code, and the number of flip edges of the corrected data code reaches the preset threshold.

8. The clock data recovery method according to claim 7, wherein: The modifying of the initial data encoding comprises: Modify any number of bits in consecutive bytes of the same value in the initial data code so that the number of flip edges of the modified initial data code reaches a preset threshold, and use the modified initial data code as the correction data code.

9. The clock data recovery method according to claim 7, wherein: The replacing of the initial data encoding comprises: The initial data code is replaced by a dummy data code to serve as the correction data code; wherein the number of flip edges of the dummy data code exceeds a preset threshold.

10. A display panel, characterized in that: The invention comprises a driving chip and a timing controller, wherein the driving chip comprises the clock data recovery circuit according to any one of claims 1 to 6, and the clock data recovery circuit is used to lock the clock data between the driving chip and the timing controller.

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