A recorder based on three-processor architecture

Abstract

The application discloses a kind of recorder based on three processor architecture, including ARM processor unit, DSP processor unit, FPGA processor unit, ARM processor unit coordinates DSP processor unit and FPGA processor unit to carry out processing to instruction and data;FPGA processing unit is electrically connected with external system, and FPGA processing unit forms the acquisition program of programming solidification according to the instruction and data distributed by ARM processor unit, and the signal data of external system is multiplexed parallel acquisition;DSP processor unit carries out real-time processing, storage, transmission to the signal data of FPGA processing unit according to the instruction and data distributed by ARM processor unit.The instruction and data processing of FPGA processor unit and DSP processor unit are coordinated by setting ARM processor unit as main control center, and work is completed by cooperation;The characteristics of three processors are realized, complementary advantages are achieved, independent and efficient, so that the optimal technical index of three processor recorder is overall played.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electrical signal data recording, and particularly relates to a recording wave generator based on a three-processor architecture. BACKGROUND

[0002] At present, the degree of automation in the field of high-speed rail and subway in China is very high, and industrial control systems are applied in various subsystems such as vehicles, lines and networks, such as power monitoring systems (SCADA), disaster prevention alarm systems (IFAS), equipment monitoring systems (IEMCS) and the like, which directly relate to the reliable and safe operation of the industry.

[0003] The recording wave generator can collect specific signals of the control system in an online manner, record the protection action event quantity and switch contact state information of the specific signals of the system in normal, abnormal or even fault conditions, so as to trace back the cause of the abnormality or fault, and if necessary, perform simulation calculation and analysis through a calculation tool, improve the control system hardware and software, and ensure the reliable and safe operation of the control system.

[0004] The recording wave generator is used in the early stage to automatically and accurately record the changes of various electrical quantities before and after the fault of the power system, and through the analysis and comparison of these electrical quantities, the recording wave generator plays an important role in analyzing and processing accidents, judging whether the protection is correctly operated, and improving the safety level of the power system. Later, due to the development of devices and technology, the recording wave generator is applied to various fields.

[0005] The recording wave generator mainly completes the collection and start-up discrimination of recording wave data, the recording of data, fault type analysis, fault positioning and fault reproduction and the like. In the development process of the performance and functions of the recording wave generator, the device performance and composition architecture of the core controller play a decisive or main role:

[0006] The first stage: the core controller is a single-chip microcomputer, which can be called a single-chip microcomputer type fault recording wave generator. However, due to the slow instruction execution speed and narrow bus bandwidth of the single-chip microcomputer, the system real-time requirement cannot be met, and the single-chip microcomputer does not have a DMA data transmission mode, which limits the transmission speed and has other shortcomings. With the development of the power network, the general single-chip microcomputer cannot meet the system requirements.

[0007] The second stage: the core controller is a DSP, which can be called a DSP fault recording wave generator. Although the DSP has powerful computing capability, the control capability is relatively insufficient, cannot transplant a powerful operating system, needs to formulate a TCP / IP protocol stack to support network communication, and has a large amount of engineering and is inconvenient for future maintenance and upgrading. This not only affects the processing speed of the DSP in the complete fault recording wave system, but also is difficult to meet the requirements of higher precision and real-time.

[0008] The third stage: the core controller is a DSP and an ARM processor. The dual-CPU scheme of ARM and DSP overcomes the weakness of ARM in digital signal processing and the weakness of DSP in system control, and forms a relatively simple and optimized software and hardware structure. Compared with the fault recorders of the previous two stages, the fault recorder has the advantages of high recording reliability, fast recording speed, better real-time performance, fast and convenient waveform acquisition, clear and accurate recording graph, small size, portability and the like.

[0009] With the complex and harsh application scene of the fault recorder and the improvement of the technical index requirements, such as high sampling rate, multi-channel parallel, real-time data processing, mass data fast dumping and the like, the current dual-processing architecture fault recorder cannot meet the high technical index requirements. SUMMARY

[0010] The main purpose of the present application is to solve the problem that the fault recorder in the prior art cannot meet the technical index requirements of high sampling rate, multi-channel parallel, real-time data processing, mass data fast dumping and the like, and provide a fault recorder based on a three-processor architecture.

[0011] To achieve the above purpose, the fault recorder based on a three-processor architecture comprises an ARM processor unit, a DSP processor unit and an FPGA processor unit.

[0012] The ARM processor unit receives instructions and data, and distributes the instructions and data to the DSP processor unit and the FPGA processor unit. The ARM processor unit coordinates the DSP processor unit and the FPGA processor unit to process the instructions and data. The ARM processor unit monitors the processing results of the DSP processor unit and the FPGA processor unit.

[0013] The FPGA processing unit is electrically connected with an external system. The FPGA processing unit forms a programmed and solidified acquisition program according to the instructions and data distributed by the ARM processor unit, and performs multi-channel parallel acquisition on the signal data of the external system.

[0014] The DSP processor unit performs real-time processing, storage and transmission on the signal data acquired by the FPGA processing unit according to the instructions and data distributed by the ARM processor unit.

[0015] Preferably, the FPGA processing unit comprises a multi-channel acquisition module and a multi-channel filtering module. The multi-channel acquisition module performs multi-channel parallel acquisition on the signal data of the external system. The multi-channel filtering module performs real-time filtering processing on the signal data acquired by the multi-channel acquisition module.

[0016] Preferably, the FPGA processing unit further comprises a control output module, which detects and determines whether the signal data of the multi-channel acquisition module is abnormal, and outputs a control signal to an actuator of an external system if it is determined to be abnormal.

[0017] Preferably, the ARM processor unit comprises a human-computer interaction module, a communication management module, and a system management module. The human-computer interaction module receives operation instructions and parameter data and sets parameters for the DSP processor unit and the FPGA processing unit. The human-computer interaction module receives query instructions and outputs state information. The communication management module receives communication instructions and transmits signal data and state information to a remote maintenance center. The system management module receives user information and password data to set permissions. The system management module determines whether there is a fault, the nature of the fault, and the scope based on real-time detection of key state data, and outputs corresponding control instructions based on the determination results.

[0018] Preferably, the DSP processor unit comprises a data processing module and a data dump module. The data processing module receives and stores signal data collected by the multi-channel acquisition module and signal data filtered by the multi-channel filtering module, and performs real-time algorithmic operation and processing on the signal data. The data dump module stores and transmits signal data processed by the data processing module.

[0019] Preferably, the DSP processor unit further comprises a waveform fitting module. The waveform fitting module receives operation instructions and parameter data from the human-computer interaction module, and performs real-time playback and display of stored signal data. The waveform fitting module performs curve fitting on special signals in the signal data.

[0020] Preferably, the ARM processor unit uses an efficiency-optimal algorithm to coordinate the processing of instructions and data by the FPGA processing unit and the DSP processor unit, while maintaining clock synchronization and real-time sharing of state data with the FPGA processing unit and the DSP processor unit.

[0021] Preferably, the control signal output by the control output module comprises a level signal and a pulse signal, and the actuator comprises a relay and a valve.

[0022] Preferably, the data processing module uses an FFT algorithm to process signal data and uses a relay protection algorithm to determine whether relay protection is needed based on the operation of signal data.

[0023] Preferably, the waveform fitting module uses a linear function, a quadratic function, a multiple function, an exponential function, and a multi-element function to perform curve fitting on special signals in the signal data.

[0024] The recorder based on the three-processor architecture has the following beneficial effects: the FPGA processor unit is arranged, the signal type, signal level, adopted frequency, process calibration, channel number, starting signal and other parameters determined by an external system are collected, a collection program and a filtering program are programmed and solidified, and multi-path parallel operation is performed, so that extreme data collection and strong anti-interference data filtering are realized; the DSP processor unit is arranged, algorithms are used to process the collected data, and storage and transmission are realized; the ARM processor unit is arranged as a master control center to coordinate the FPGA processor unit and the DSP processor unit to process instructions and data, and to cooperatively complete respective work; the characteristics of the three processors are realized, complement each other, are independent and efficient, and thus optimal technical indexes of the three-processor recorder are realized. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only are the embodiments of the present application, and for those skilled in the art, other drawings can be obtained based on the provided drawings without any creative effort:

[0026] Figure 1 Fig. 1 shows a system structure schematic diagram of a recorder based on a three-processor architecture provided by an embodiment of the present application;

[0027] Figure 2 Fig. 2 shows a module structure schematic diagram of a recorder based on a three-processor architecture provided by an embodiment of the present application;

[0028] 100, recorder; 10, FPGA processor unit; 11, multi-path collection module; 12, multi-path filtering module; 13, control output module; 20, DSP processor unit; 21, data processing module; 22, data dump module; 23, waveform fitting module; 30, ARM processor unit; 31, human-computer interaction module; 32, communication management module; 33, system management module; 200, external system; 300, remote maintenance center. DETAILED DESCRIPTION

[0029] In order to facilitate the understanding of the present application, the following will comprehensively describe the present application with reference to the related drawings. The drawings show typical embodiments of the present application. However, the present application can be realized in many different forms, and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0031] The general idea of the present application is: in view of the shortcomings that the existing recorder cannot meet the technical index requirements of high sampling rate, multi-channel parallel, real-time data processing, mass data fast dumping, etc., the present application sets FPGA processor unit, collects the parameters such as signal type, signal level, frequency, process calibration, channel number, starting signal determined by external system design, and programs and solidifies the acquisition program and filter program, and realizes the extreme data acquisition and strong anti-interference data filtering through multi-channel parallel operation; through setting DSP processor unit, the collected data is processed by using algorithm, and stored and transmitted; through setting ARM processor unit as the main control center, the FPGA processor unit and the DSP processor unit are coordinated for instruction and data processing, and the respective works are completed cooperatively; the respective characteristics of the three processors are realized, the advantages are complementary, and the three processors are independent and efficient, so that the optimal technical index of the three-processor recorder is realized.

[0032] In order to better understand the above technical solutions, the above technical solutions will be described in detail below in combination with the drawings and specific embodiments in the specification. It should be understood that the embodiments of the present application and the specific features in the embodiments are detailed descriptions of the technical solutions of the present application, and are not limitations of the technical solutions of the present application. In the case of no conflict, the technical features in the embodiments of the present application and the embodiments can be combined with each other.

[0033] Reference Figure 1 , Figure 1A system structure schematic diagram of a recorder 100 based on a three-processor architecture is shown in an embodiment of the present application; in this embodiment, a recorder 100 based on a three-processor architecture includes an ARM processor unit 30, a DSP processor unit 20, and an FPGA processor unit 10; the ARM processor unit 30 receives instructions and data, and distributes the instructions and data to the DSP processor unit 20 and the FPGA processor unit 10; the ARM processor unit 30 coordinates the processing of the instructions and data by the DSP processor unit 20 and the FPGA processor unit 10; the ARM processor unit 30 monitors the processing results of the instructions and data by the DSP processor unit 20 and the FPGA processor unit 10; the FPGA processing unit is electrically connected to an external system 200; the FPGA processing unit forms a programmed and solidified collection program according to the instructions and data distributed by the ARM processor unit 30, and performs multi-channel parallel collection on the signal data of the external system 200; the DSP processor unit 20 performs real-time processing, storage, and transmission on the signal data collected by the FPGA processing unit according to the instructions and data distributed by the ARM processor unit 30.

[0034] The collection probe of the recorder 100 is electrically connected to the external system 200 to achieve the electrical connection between the FPGA processor unit 10 and the electrical nodes of the external system 200; in the present application, the external system 200 is a power system; from the functional point of view, the FPGA chip uses a software and hardware structure to implement software instructions, while the general microprocessor is implemented through a hardware structure and software instructions. Compared with the traditional microprocessor, the FPGA chip uses a hardware structure to replace the implementation of software instructions in the software part; since the hardware structure is used to implement software functions compared with the software instructions, the FPGA chip has the advantages of fast speed, strong anti-interference, good reliability, and the ability to achieve multi-channel operation through the parallel work of multiple multipliers designed by programming, etc. The above advantages make the FPGA processor unit 10 meet the technical index requirements of faster collection speed, multi-channel collection, and more faithful collected signals for the power system. However, the software and hardware structure of the FPGA chip is not as flexible as the implementation of functions by software instructions, and its programming function is easy to solidify. However, in the power system, the electrical signal parameters are determined at the time of system design, that is, the electrical signal parameters of a power system basically do not change, which can cover up the disadvantage of the inflexible programming of the FPGA chip, and the advantages of the FPGA chip can meet the requirements of faster collection speed, multi-channel collection, and stronger anti-interference of collected signals for the electrical signals of the power system.

[0035] The three-processor architecture of the recorder 100, the ARM processor unit 30 as the main control unit, the FPGA processor unit 10 and the DSP processor unit 20 as the coprocessor unit, the system of the ARM processor unit 30 is an embedded operating system, which has the characteristics of high flexibility, easy expansion, multiple communication interfaces, etc., and can meet the needs of data communication, human-computer interaction, platform architecture management in various scenarios. In the case that the electrical parameters of the power system have been designed and determined, the FPGA processor unit 10 is set by the ARM processor unit 30 receiving the instructions and parameter data corresponding to the electrical parameters of the power system, so that the FPGA processor unit 10 acquires the programmed solidification, and realizes faster acquisition speed of the electrical signal of the power system. The electrical signal of the power system is an analog signal, and the FPGA processor unit 10 acquires the electrical signal and converts the acquired analog signal into a digital signal through the programmed solidification of the logic gate array.

[0036] The ARM processor unit 30 as the main control unit interacting with the outside world receives various instructions and data input from the outside, and distributes the instructions and data to the DSP processor unit 20 and the FPGA processor unit 10 and itself according to the type of the instructions for processing. For example, the acquisition programming instruction and the acquisition parameter data are distributed to the FPGA processor unit 10, the data processing instruction and the algorithm parameter data are distributed to the DSP processor unit 20, etc. After the DSP processor unit 20 and the FPGA processor unit 10 receive the instructions, the instructions are executed according to the parameter data, and in the whole processing process, the ARM processor unit 30 synchronizes the clock with the FPGA processing unit and the DSP processor unit 20, shares the state data in real time, and uses the most efficient algorithm to coordinate the processing of the FPGA processing unit and the DSP processor unit 20. At the same time, the ARM processor unit 30 monitors the results processed by the DSP processor unit 20 and the FPGA processor unit 10, such as whether the electrical signal data is abnormal, whether the instructions are not responsive, whether the parameter data is not stored, whether the data is not processed according to the specified algorithm, etc.

[0037] The DSP processor unit 20 mainly processes digital signals, which is different from the common CPU, and is a microprocessor with special structure for achieving fast mathematical operation. The fast instruction cycle, Harvard structure, pipeline operation, special hardware multiplier, special DSP instruction and the optimized design of integrated circuit highlight the characteristics of the DSP, that is, strong computing ability, high precision, fast bus speed and large throughput, especially the special hardware for realizing fixed-point and floating-point multiplication and addition, which is very fast. The DSP processor unit 20 receives the processing instructions and parameter data of the ARM processor unit 30, processes the data collected by the FPGA processing unit in real time, processes the real digital signal data of the FPGA processing unit into synthesized data signals constructed according to certain specific rules, and displays various parameter characteristics through the recorder 100. The digital signal data received and processed are also stored for later retrieval and analysis. Of course, the storage length is determined by the size of the hard disk. The larger the hard disk capacity, the more signal data can be stored, and the longer the digital signal data can be stored. Usually, when the storage capacity reaches the set value, the previously stored digital signal data will be automatically deleted. In order to ensure enough collected data for analysis, the collected data stored in the DSP processor unit 20 is usually periodically transferred to the remote maintenance center 300 for later tracing of abnormal or fault causes, and if necessary, the control system hardware and software are improved through simulation calculation and analysis to ensure reliable and safe operation of the control system. The remote maintenance center 300 plays an important role in analyzing and comparing electrical quantities, analyzing and processing accidents, judging whether the protection is correctly operated, and improving the safe operation level of the power system.

[0038] The recorder 100 in the application adopts a three-processor processor architecture, which can greatly improve the sampling rate, data calculation and processing, real-time transmission and playback, and timely response control of the recorder 100 by exerting the respective advantages of the three processors.

[0039] As shown in Figure 2 As shown in Figure 2 Fig. 1 is a module structure schematic diagram of a three-processor architecture recorder 100 according to an embodiment of the application. Specifically, the FPGA processing unit includes a multi-channel acquisition module 11 and a multi-channel filtering module 12. The multi-channel acquisition module 11 acquires the signal data of the external system 200 in multiple channels in parallel, and the multi-channel filtering module 12 performs real-time filtering processing on the signal data acquired by the multi-channel acquisition module 11.

[0040] The multi-channel acquisition module 11 is electrically connected with the external system 200, acquires the electrical signals of the external system 200, and is programmed and solidified according to the parameters determined by the system design, such as the type of electrical signals (such as analog signals and switching signals), the signal level (such as voltage level and current level), the frequency, the process calibration, the channel number, the start signal, and the like, to realize the extreme data acquisition. The multi-channel acquisition module 11 receives the instructions sent by the ARM processor unit 30, executes the acquisition program to acquire the data, and performs multi-channel and multi-channel parallel acquisition. The acquisition program converts the analog electrical signal data of the external system 200 into digital electrical signal data.

[0041] The multi-channel filtering module 12 receives the digital signal data acquired by the multi-channel acquisition module 11, needs to perform real-time filtering processing, and is programmed and solidified with the acquisition program of the multi-channel filtering module 12. The filtering program eliminates the interference of other signals in the signal channel and ensures the high fidelity of the acquired electrical signals. The multi-channel filtering module 12 receives the instructions sent by the ARM processor unit 30, executes the filtering program to perform multi-channel and multi-channel parallel digital filtering processing on the acquired digital signal data. After the processing is completed, the data is stored and transmitted.

[0042] In order to fully utilize the fast hardware implementation speed of software instructions, specifically, the FPGA processing unit further includes a control output module 13. The control output module 13 detects and determines whether the signal data of the multi-channel acquisition module 11 is abnormal, and outputs a control signal to the actuator of the external system 200 if it is determined to be abnormal.

[0043] The control output module 13 performs real-time detection on the acquired electrical signals. When the system fails, if the electrical signal is greater than the set reference voltage value or reference current value, the control output module 13 immediately sends a control signal to the actuator of the external system 200. The output time is extremely short, less than milliseconds. Preferably, the control signal is a level signal, and the actuator is a relay. When the relay receives a low-level output from the control output module 13, the actuator relay is disconnected, disconnecting the power supply between the power station and the load of the external system 200. The control signal can also be a pulse signal, and correspondingly, the actuator can be a valve. When the pulse signal is output, the valve is disconnected. The voltage parameters and current parameters and the like are set by inputting setting instructions and parameter data through the ARM processor unit 30, which is equivalent to storing the reference values of various electrical signal parameter types in the control output module 13.

[0044] Specifically, the ARM processor unit 30 comprises a human-computer interaction module 31, a communication management module 32, and a system management module 33. The human-computer interaction module 31 receives operation instructions and parameter data and sets parameters for the DSP processor unit 20 and the FPGA processor unit 10. The human-computer interaction module 31 receives query instructions and outputs state information. The communication management module 32 receives communication instructions and transmits signal data and state information to the remote maintenance center 300. The system management module 33 receives user information and password data and sets permissions. The system management module 33 determines whether there is a fault, the nature of the fault, and the scope based on real-time detection of key state data, and outputs corresponding control instructions based on the determination results.

[0045] The human-computer interaction module 31 is a processing module for the operator to interact with the wave recorder 100. It inputs instructions and data through peripheral devices, such as directly inputting instructions and data through a keyboard and determining commands and selecting objects for viewing through a mouse. For example, it sets parameters such as voltage and current of collected data of the FPGA processor unit 10 and executes collection programs, sets parameters such as filter parameters of the FPGA processor unit 10 and executes filter programs, queries the performance of the wave recorder 100 itself, such as the power state, working state, and network connection state of the wave recorder 100, whether there is an audible prompt, display screen display adjustment, and the like. It also includes changes to some dynamic parameters, result feedback, and the like, such as modifying some parameters of waveforms, changing frequencies, increasing waveform density, and the like. Typically, after the wave recorder 100 is powered on, the system starts and receives input devices such as a keyboard, buttons, code switches, touch screens, and the like to initialize parameter settings. It displays related parameters or states and abnormal sound prompts. In summary, the human-computer interaction module 31 is an interactive interface for the operator to control various functions of the wave recorder 100 and is also a window for various operation result feedback, greatly facilitating human-computer interaction.

[0046] The communication management module 32 is an interface for data interaction between the recorder 100 and the remote maintenance center 300. On the recorder 100, the communication interface usually includes RS232, RS485, CAN, and TCP / IP communication protocol interfaces. On one hand, the communication management module 32 analyzes the electrical signal data, reproduces the accident, prints, and remotely transmits the data to the remote maintenance center 300, so as to complete the management and recording of the electrical signal recording function of the whole system. On the other hand, the personnel of the remote maintenance center 300 can remotely view the state of the equipment through the communication interface. At the same time, the peer protection devices can also cooperate with each other through the mutual communication module to achieve the combined protection function. The initialization communication management module 32 executes the communication interface program, detects the communication function, detects whether the data transmission function of the recorder 100 to the remote maintenance center 300 is normal, whether the function of the recorder 100 viewed by the remote maintenance center 300 is normal, and whether the communication function between each recorder 100 in the whole system is normal. The communication management module 32 receives the signal data transmission instruction and state viewing instruction conveyed by the remote maintenance center 300, calls the stored signal data, queries the state of the recorder 100, and transmits the signal data and state information to the remote maintenance center 300.

[0047] The system management module 33 is a specific execution module of the ARM processor unit 30 for handling the platform system management of the recorder 100. It is mainly reflected in the installation of the DSP processor unit 20, the architecture design programming of the DSP processor unit 20, and the supervision and coordination of the DSP processor unit 20 and the DSP processor unit 20 for task execution. It is also reflected in the management of system security, including receiving user information, password data for permission setting, or user information registration, password modification, etc. It is also reflected in the emergency management of special situations, real-time detection of key state data, and determination of whether it is a fault, the nature of the fault, and the range. According to the determination result, the corresponding control instruction is output. For example, if the external system 200 is overvoltage and overcurrent due to special conditions, a trigger instruction is output, and a control signal is output to the external system 200 by the control output module 13.

[0048] Specifically, the DSP processor unit 20 includes a data processing module 21 and a data dump module 22. The data processing module 21 receives and stores the signal data collected by the multi-channel acquisition module 11 and the signal data filtered by the multi-channel filter module 12, and performs real-time algorithm operation processing on the signal data. The data dump module 22 stores and transmits the signal data processed by the data processing module 21.

[0049] The data processing unit utilizes the fast operation speed and the digital processing specialty of the DSP chip to perform real-time and efficient data processing on the collected signal data or the filtered signal data. The processing mode preferably includes processing the signal data by using the FFT algorithm, and using the relay protection algorithm to determine whether the relay needs to be disconnected for protection.

[0050] The data processing module 21 transmits the processed collected data to the data dump module 22 for storage by using an algorithm. The data dump module 22 receives a dump instruction from the ARM processing unit, and transmits the signal data in batches to the remote maintenance center 300. The communication management module 32 coordinates and manages the communication interface of the data dump module 22.

[0051] To realize the analysis of the electrical signal data by the operator, the DSP processor unit 20 further includes a waveform fitting module 23. The waveform fitting module 23 receives the operation instruction and the parameter data from the human-computer interaction module 31, and performs real-time playback display on the stored signal data. The waveform fitting module 23 performs curve fitting on the special signal in the signal data.

[0052] When analyzing the electrical signal data, the control instruction and the display parameter are input to the waveform fitting module 23 through the human-computer interaction module 31. The waveform fitting module 23 performs real-time playback display on the electrical signal according to time, and analyzes the waveform display. When a special signal is encountered, the control instruction and the waveform fitting parameter are input through the human-computer interaction module 31. The waveform fitting module 23 executes the waveform fitting display program to perform fitting calculation on the special signal. Preferably, the waveform fitting module 23 performs curve fitting on the special signal in the signal data by using a linear function, a quadratic function, a multiple function, an exponential function, and a multi-element function.

[0053] The recording wave device based on the three-processor architecture has the following beneficial effects: through the setting of the FPGA processor unit, the signal type, signal level, adopted frequency, process calibration, channel number, starting signal and other parameters determined by the external system design are collected, the program and the filtering program are programmed and solidified, and multiple parallel operation is realized, so that the extreme data collection and the strong anti-interference data filtering are realized; through the setting of the DSP processor unit, the collected data are processed by using the algorithm, and are stored and transmitted; through the setting of the ARM processor unit as the main control center, the FPGA processor unit and the DSP processor unit are coordinated to process the instructions and data, and the respective work is cooperatively completed; the respective characteristics of the three processors are realized, the advantages are complementary, the independence and efficiency are realized, and thus the optimal technical index of the three-processor recording wave device is realized as a whole.

[0054] In the description provided herein, a large number of specific details are explained. However, it can be understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.

[0055] Similarly, it is to be understood that the embodiments of the present application, which have been described in the foregoing specification, are illustrative of the application and not restrictive of the same. Many other embodiments of the application will be apparent to those of ordinary skill in the art from the foregoing description. The embodiments of the application as described are the best modes contemplated for carrying out the application. Their implementation can omit, substitute, or add various procedures or components in addition to those described and can not always remain within the set of procedures used in the foregoing recited or claimed embodiments. The scope of the application is indicated by the appended claims rather than by the foregoing description, and all changes and modifications that come within the meaning and range of equivalents of the claims are intended to be embraced therein. The disclosure is not limited to the details given in the foregoing description.

[0056] Those skilled in the art will appreciate that the modules in the apparatuses in the embodiments can be adaptively changed and arranged in one or more apparatuses different from the embodiments. The modules or units or components in the embodiments can be combined into one module or unit or component, and furthermore can be divided into multiple sub-modules or sub-units or sub-components. Except that at least some of such features and / or processes or units are mutually exclusive, all combinations of all features disclosed in the specification (including the accompanying claims, abstract and drawings), and all processes or units of any methods or apparatuses disclosed thus can be adopted. Unless explicitly stated otherwise, each feature disclosed in the specification (including the accompanying claims, abstract and drawings) can be replaced by an alternative feature providing the same, equivalent or similar purpose.

[0057] Furthermore, those skilled in the art will recognize that, while certain embodiments described herein include certain features that are not included in other embodiments, combinations of those features from different embodiments are meant to be within the scope of the application, and form different embodiments, for example, in the following claims. For example, in the following claims, any of the claimed embodiments can be used in any combination.

[0058] Various component embodiments of the application can be implemented in hardware, or as software modules running in one or more processors, or in combinations thereof. Skilled persons will appreciate that a microprocessor or digital signal processor (DSP) can be used in practice to implement some or all of the functionality of some or all of the components in accordance with embodiments of the application.

[0059] The application can also be implemented as a program for executing, in whole or in part, the methods described herein on a device or apparatus (e.g., a computer program and a computer program product). Such program implementing the application can be stored on a computer-readable medium, or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, or provided on a carrier, or in any other form. It should be noted that the above-mentioned embodiments illustrate rather than limit the application, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The application can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unitary claim, several of the devices mentioned in the groups of devices can be embodied by one and the same thing or element. The use of the words first, second and third, does not indicate any order. These words have been used to name the circumstances in which the embodiments have been described, but they are unfortunately not placed in this specific order for reasons of clarity having to do with the description and the comprehension of the disclosure, but also due to the technical and legal requirements of the patent claims.

Claims

1.A recorder based on a three-processor architecture, characterized in that, the recorder comprises an ARM processor unit, a DSP processor unit and an FPGA processor unit; the ARM processor unit receives instructions and data and distributes the instructions and data to the DSP processor unit and the FPGA processor unit, coordinates the DSP processor unit and the FPGA processor unit to process the instructions and data, and monitors the processing results of the DSP processor unit and the FPGA processor unit; the FPGA processor unit is electrically connected to an external system, forms a programmed and solidified acquisition program according to the instructions and data distributed by the ARM processor unit, and performs multi-channel parallel acquisition on signal data of the external system; the DSP processor unit performs real-time processing, storage and transmission on the signal data acquired by the FPGA processor unit according to the instructions and data distributed by the ARM processor unit; the ARM processor unit uses an efficiency optimization algorithm to coordinate the processing of the instructions and data by the FPGA processor unit and the DSP processor unit while keeping clock synchronization and real-time sharing of state data with the FPGA processor unit and the DSP processor unit. 2.The recorder based on a three-processor architecture according to claim 1, characterized in that, the FPGA processor unit comprises a multi-channel acquisition module and a multi-channel filtering module, the multi-channel acquisition module performs multi-channel parallel acquisition on signal data of an external system, and the multi-channel filtering module performs real-time filtering processing on the signal data acquired by the multi-channel acquisition module. 3.The recorder based on a three-processor architecture according to claim 2, characterized in that, the FPGA processor unit further comprises a control output module, which detects and determines whether the signal data of the multi-channel acquisition module is abnormal, and outputs a control signal to an actuator of the external system if it is determined to be abnormal. 4.The recorder based on a three-processor architecture according to claim 3, characterized in that, the ARM processor unit comprises a human-computer interaction module, a communication management module and a system management module, the human-computer interaction module receives operation instructions and parameter data and sets parameters for the DSP processor unit and the FPGA processor unit, the human-computer interaction module receives query instructions and outputs state information, the communication management module receives communication instructions and transmits signal data and state information to a remote maintenance center, the system management module receives user information and password data and sets permissions, the system management module determines whether there is a fault, the nature and scope of the fault according to key state data detected in real time, and outputs corresponding control instructions according to the determination results. 5.The recorder based on a three-processor architecture according to claim 4, characterized in that, The DSP processor unit comprises a data processing module and a data dump module, the data processing module receives and stores signal data collected by the multi-channel acquisition module and signal data filtered by the multi-channel filter module, and performs real-time algorithm operation processing on the signal data, and the data dump module stores and transmits the signal data processed by the data processing module. 6.The recorder based on the three-processor architecture according to claim 5, characterized in that, The DSP processor unit further comprises a waveform fitting module, the waveform fitting module receives operation instructions and parameter data of the human-computer interaction module, and performs real-time playback display on the stored signal data, and the waveform fitting module performs curve fitting on special signals in the signal data. 7.The recorder based on the three-processor architecture according to claim 3, characterized in that, The control signals output by the control output module comprise level signals and pulse signals, and the execution mechanism comprises relays and valves. 8.The recorder based on the three-processor architecture according to claim 5, characterized in that, The data processing module processes the signal data by using an FFT algorithm, and judges whether the relay protection is needed by using a relay protection algorithm to operate the signal data. 9.The recorder based on the three-processor architecture according to claim 6, characterized in that, The waveform fitting module adopts a linear function, a quadratic function, a multiple function, an exponential function, and a multi-element function to perform curve fitting on special signals in the signal data.

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