Display device

Abstract

A display device includes a display panel in which pixels are arranged, a first circuit board configured to provide a first driving signal to the display panel, and a second circuit board connecting the display panel and the first circuit board and having a first area in which a driving chip providing a second driving signal to the display panel is arranged and a second area surrounding the first area, the first area and the second area being defined in the second circuit board, wherein: the second circuit board includes first lines electrically connected to the driving chip and second lines electrically insulated from the driving chip; the second lines include a common line located in the first area; and in a plane, as the common line becomes farther from the first circuit board, a width of the common line decreases.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2021-0027955, filed on March 3, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Aspects of some embodiments of this disclosure relate to display devices. Background Technology

[0004] Typically, a display panel can be manufactured, and then a circuit board can be attached to the display panel. For example, in the "tape-on-board" (TAB) mounting method, the circuit board can be attached to the display panel using anisotropic conductive film (ACF).

[0005] Recently, with the reduction of bezel area (or non-display area), design proposals for display devices with high durability are being actively researched.

[0006] The information disclosed in this background section is only intended to enhance the understanding of the background art, and therefore, the information discussed in this background section may not constitute prior art. Summary of the Invention

[0007] Aspects of some embodiments of this disclosure relate to display devices, and for example, to display devices having relatively improved line arrangement efficiency.

[0008] Some aspects of embodiments of this disclosure include a display device in which power lines connected to a display panel are arranged relatively efficiently on a circuit board in terms of space.

[0009] According to some embodiments of the present invention, a display device includes: a display panel in which pixels are arranged; a first circuit board configured to provide a first driving signal to the display panel; and a second circuit board connecting the display panel and the first circuit board and having a first region and a second region surrounding the first region, wherein a driving chip providing the second driving signal to the display panel is arranged in the first region, the first region and the second region are defined in the second circuit board, wherein: the second circuit board includes a first line electrically connected to the driving chip and a second line electrically insulated from the driving chip; the second line includes a common line located in the first region; and in a plane, the width of the common line decreases as it becomes further away from the first circuit board.

[0010] According to some embodiments, the common line includes: a first portion adjacent to the first circuit board and extending in a first direction; a second portion having one end connected to the first portion and extending from the first portion in a second direction orthogonal to the first direction in a direction away from the first circuit board; and a third portion extending from the other end of the second portion opposite to the first end in the first direction and adjacent to the display panel, wherein a first width of the first portion may be greater than a second width of the second portion, and the second width may be greater than a third width of the third portion.

[0011] According to some embodiments, the second line may include at least one power line configured to provide power to the display panel.

[0012] According to some embodiments, the second line may further include multiple output lines extending from the common line to the second region, and the widths of the multiple output lines may all be the same.

[0013] According to some embodiments, the output lines may include a first output line of n connected to the first part, a second output line of m connected to the second part, and a third output line of l connected to the third part.

[0014] According to some embodiments, the number of the plurality of output lines connected to the common line may be proportional to the width of the common line.

[0015] According to some embodiments, the first width of the first portion may be proportional to the sum of the number of the first output lines, the number of the second output lines, and the number of the third output lines; the second width of the second portion may be proportional to the sum of the number of the second output lines and the number of the third output lines; and the third width of the third portion may be proportional to the number of the third output lines.

[0016] According to some embodiments, A = (n + m + l)x + a, B = (m + l)x + a, and C = lx + a, wherein the width of each of the plurality of output lines is x, the first width is A, the second width is B, and the third width is C, and the units of A, B, C and x are micrometers.

[0017] According to some embodiments, a can be 0.

[0018] According to some embodiments, a is a stability constant and may be approximately twice the width x of each of the said output lines.

[0019] According to some embodiments, the first line may include a pad portion located in the first region and connected to the driver chip and a line portion located in the second region.

[0020] According to some embodiments, the common line may be located in the first region to bypass the pad portion.

[0021] According to some embodiments, the second line may include a number of z output lines connected to the common line and extending into the second region, and the width of the common line may decrease by y, where y is in micrometers, whenever the common line passes each of the output lines in a direction away from the first circuit board.

[0022] According to some embodiments, the width of each output line can be x, and y can be the same as x, where the units of x and y are micrometers.

[0023] According to some embodiments, the width of each output line can be x, y can be a larger than x, and a can be approximately twice x, where x, y, and a are in micrometers.

[0024] According to some embodiments, the maximum value of the width of the common line can be xz, and the minimum value of the width of the common line can be x, where xz and x are in micrometers.

[0025] According to some embodiments of the present invention, a display device includes: a display panel; a first circuit board configured to provide a first drive signal to the display panel; and a second circuit board connecting the display panel and the first circuit board and having a first region and a second region surrounding the first region, wherein a driver chip providing the second drive signal to the display panel is positioned in the first region, and the first region and the second region are defined in the second circuit board, wherein: the second circuit board includes a first wire electrically connected to the driver chip and a second wire electrically insulated from the driver chip; the second wire includes a common line, the common line including a first common portion located in the first region and extending in a direction opposite to a first direction and a second common portion extending in the first direction; and each of the widths of the first common portion and the second common portion decreases as the first common portion and the second common portion become further apart from each other.

[0026] According to some embodiments, the second line includes multiple output lines connected to the common line and located in the second region, wherein the difference between the maximum and minimum width of the common line can be proportional to the number of output lines.

[0027] According to some embodiments, the plurality of output lines may include a plurality of first output lines connected to the first common portion and a plurality of second output lines connected to the second common portion, wherein the number of first output lines and the number of second output lines may be the same as each other.

[0028] According to some embodiments, whenever the first common portion passes the first output line in a direction away from the second common portion, the width of the first common portion can be reduced to the width of each of the first output lines, and whenever the second common portion passes the second output line in a direction away from the first common portion, the width of the second common portion can be reduced to the width of each of the second output lines. Attached Figure Description

[0029] The accompanying drawings are included to provide a further understanding of the inventive concept, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings:

[0030] Figure 1A These are perspective views of display devices according to some embodiments of the present invention;

[0031] Figure 1B This is an exploded perspective view of a display device according to some embodiments of the present invention;

[0032] Figure 2 This is a cross-sectional view of a display panel according to some embodiments of the present invention;

[0033] Figure 3 This is a plan view of a display panel according to some embodiments of the present invention;

[0034] Figure 4 This is an equivalent circuit diagram of a pixel according to some embodiments of the present invention;

[0035] Figure 5 This is an enlarged cross-sectional view of a display panel according to some embodiments of the present invention;

[0036] Figure 6A This is a plan view of a second circuit board according to some embodiments of the present invention;

[0037] Figure 6B This is a perspective view of a second circuit board according to some embodiments of the present invention;

[0038] Figure 7 This is a plan view of the chip mounting area of ​​a second circuit board according to some embodiments of the present invention;

[0039] Figure 8These are some embodiments of the concept of the present invention. Figure 7 A magnified view of a portion of the chip mounting area;

[0040] Figure 9A and Figure 9B These are some embodiments of the concept of the present invention. Figure 7 Enlarged view of a portion of the chip mounting area; and

[0041] Figure 10A and Figure 10B These are some embodiments of the concept of the present invention. Figure 7 A magnified view of a portion of the chip mounting area. Detailed Implementation

[0042] In this specification, it will be understood that when an element (or region, layer, part, etc.) is referred to as being "on" another element, "connected to" or "coupled to" another element, the element may be directly on, directly connected to or directly coupled to the other element, or there may be an intermediary element.

[0043] The same reference numerals always refer to the same elements. Additionally, in the drawings, the thickness, scale, and dimensions of elements are exaggerated for the purpose of effectively describing the technical content. As used herein, the term "and / or" includes any and all combinations that the associated construction can define.

[0044] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element without departing from the scope of the invention. Similarly, a second element may also be referred to as a first element. Unless otherwise stated, singular terms include plural forms.

[0045] For ease of explanation, terms such as "below," "under," "above," and "above" are used here to describe the relationship between one element and another (or multiple elements) as shown in the figures. These terms are relative concepts and are described based on the directions indicated in the figures.

[0046] It will be understood that when the terms “comprising” and / or “having” are used in this specification, it indicates the presence of the stated features, integers, steps, operations, elements, components and / or groups thereof, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0047] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that, unless expressly defined herein, terms (such as those defined in a common dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and will not be interpreted in an ideal or overly formal sense.

[0048] In the following description, embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0049] Figure 1A This is a perspective view of a display device according to some embodiments of the present invention. Figure 1B This is an exploded perspective view of a display device according to some embodiments of the present invention.

[0050] Reference Figure 1A and Figure 1B The display device DD can be activated based on an electrical signal. The display device DD can include various embodiments, applications, or usage examples. For example, the display device DD can be applied to the display devices of various electronic devices such as smartwatches, computers including tablet computers and laptop computers, and smart televisions.

[0051] The display device DD can display an image IM on a display surface IS parallel to each of the first direction DR1 and the second direction DR2, facing a third direction DR3. The display surface IS on which the image IM is displayed can correspond to the front surface of the display device DD. The image IM can include a moving (e.g., video) image or a still (e.g., static) image.

[0052] According to some embodiments, the front (or upper) and rear (or lower) surfaces of each component are defined based on the orientation of the displayed image IM. The front and rear surfaces are opposite each other on a third direction DR3, and the normal direction of each of the front and rear surfaces may be parallel to the third direction DR3.

[0053] The spacing between the front and rear surfaces in the third direction DR3 can correspond to the thickness of the display device DD in the third direction DR3. Meanwhile, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts and can be transformed into other directions.

[0054] The display device DD can sense external input applied from the outside. External input can include various types of input provided from the outside. According to some embodiments of the present invention, the display device DD can sense a user's touch US applied from the outside. The user's touch US can be any of various types of external input, such as a part of the user's body, light, heat, or pressure, or a combination thereof. According to some embodiments, the user's touch US is described, for example, as a touch input applied to the front surface (e.g., by the user's hand or other object such as a stylus), but this is merely an illustrative example, and as mentioned above, the first input via the user's touch US can be provided in various ways. Additionally, depending on the structure of the display device DD, the display device DD can sense a user's touch US applied to the side or rear surface of the display device DD, and embodiments of the present invention are not limited thereto.

[0055] In addition to the user's touch (US), the display device (DD) according to some embodiments of the present invention can also sense input from input devices (e.g., styluses, active pens, styluses, electronic pens, and electronic pen-like pens).

[0056] The front surface of the display device DD can be divided into a transmissive area TA and a bezel area BZA. The transmissive area TA can be the area where an image IM is displayed. The user visually recognizes or views the image IM displayed at or through the transmissive area TA. According to some embodiments, the transmissive area TA is shown as a quadrilateral shape with rounded vertices. However, this is shown as an example, and the transmissive area TA can have various shapes and is not limited to any one shape.

[0057] The border region BZA is adjacent to the transmissive region TA. The border region BZA may have a color (e.g., a set or predetermined color). The border region BZA may surround the transmissive region TA. That is, the border region BZA may be positioned outside (or outside the occupied area) of the transmissive region TA. Therefore, the shape of the transmissive region TA may be substantially defined by the border region BZA. However, this is shown by way of example, and the border region BZA may be positioned adjacent to one side of the transmissive region TA and may be omitted. The display device DD according to some embodiments of the present invention may include various shapes or arrangements and is not limited to any one shape.

[0058] like Figure 1B As shown, the display device DD may include a window WM and a display panel DP. The window WM may be positioned on the display panel DP. An input sensor may be positioned on the display panel DP. The input sensor may be formed on the display panel DP through a continuous process. The display panel DP outputs an image IM, and the input sensor acquires coordinate information from external input.

[0059] The window WM transmits the image from the display panel DP. That is, the window WM may have a transmission region TA and a border region BZA surrounding the transmission region TA. The transmission region TA and the border region BZA are defined within the window WM, and the image generated by the display panel DP passes through the transmission region TA (or the image generated by the display panel DP can be viewed through the transmission region TA).

[0060] The window WM can be made of a transparent material capable of displaying an image IM. For example, the window WM can be made of glass, sapphire, or plastic. The window WM is shown as a single layer, but is not limited to this, and according to some embodiments, the window WM may include multiple layers.

[0061] The display panel DP according to some embodiments of the present invention can be a light-emitting display panel, but is not specifically limited thereto. For example, the display panel DP can be an organic light-emitting display panel or a quantum dot light-emitting display panel. The light-emitting layer of an organic light-emitting display panel can contain organic light-emitting materials. The light-emitting layer of a quantum dot light-emitting display panel can contain quantum dots and quantum rods, etc. Hereinafter, the display panel DP is described as an organic light-emitting display panel.

[0062] Figure 1A and Figure 1B A display device DD with a flat structure is shown, but embodiments of the present invention are not limited thereto. The display device DD can be bent or folded along a folding axis and can have a sliding structure.

[0063] According to some embodiments, the anti-reflective layer may be further positioned between the window WM and the display panel DP. The anti-reflective layer reduces the reflectivity of external light incident from the upper side of the window WM. In some embodiments of the invention, the anti-reflective layer may include a retarder and a polarizer. The retarder may be a film-type retarder or a liquid crystal-coated retarder, and may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may also be a film-type polarizer or a liquid crystal-coated polarizer. The film-type retarder or film-type polarizer may include an elongated synthetic resin film, and the liquid crystal-coated retarder or liquid crystal-coated polarizer may include liquid crystals arranged in an array (e.g., a set or predetermined array). The retarder and polarizer may be implemented as a single polarizing film.

[0064] A display panel (DP) can display images and send / receive information about external inputs based on electrical signals. The display panel (DP) may have a display area (DA) and a non-display area (NDA) defined therein. The display area (DA) can be defined as the area displaying the image provided from the display panel (DP).

[0065] The non-display area NDA is adjacent to the display area DA. For example, the non-display area NDA may surround the display area DA. However, this is shown as an example, and the non-display area NDA may be defined in various shapes and is not limited to any one shape. In some embodiments of the present invention, the display area DA of the display panel DP may correspond to at least a portion of the transmissive area TA.

[0066] The display device DD may further include a main circuit board (MPCB), a flexible circuit film (FPCB), and a driver chip (DC). The main circuit board (MPCB) may be connected to the flexible circuit film (FPCB) for electrical connection to the display panel (DP). The main circuit board (MPCB) may include multiple driving elements. The multiple driving elements may include circuit units for driving the display panel (DP). The flexible circuit film (FPCB) is connected to the display panel (DP) to electrically connect the display panel (DP) and the main circuit board (MPCB). The driver chip (DC) may be mounted on the flexible circuit film (FPCB).

[0067] The driving chip DC may include driving elements for driving the pixels of the display panel DP, such as data driving circuitry. In some embodiments of the invention, the flexible circuit film FPCB is shown as a single film; however, the number of flexible circuit films FPCB is not limited to this, and multiple flexible circuit films FPCB may be provided and connected to the display panel DP. Hereinafter, the main circuit board MPCB is described as a first circuit board MPCB, and the flexible circuit film FPCB is described as a second circuit board FPCB.

[0068] Reference Figure 1B The display device DD also includes a housing EDC that houses the display panel DP. The housing EDC can be combined with a window WM to define the appearance of the display device DD. The housing EDC absorbs impacts from the outside and prevents or reduces the infiltration of foreign objects and moisture into the display panel DP, thus protecting the components housed within the housing EDC. Furthermore, as an example of the invention, the housing EDC can be provided in the form of multiple storage components combined with the housing EDC.

[0069] The display device DD according to some embodiments of the present invention may further include: an electronic module including various functional modules for operating the display panel DP; a power supply module for supplying power required for the overall operation of the display device DD; a display module; and / or a bracket for dividing the internal space of the display device DD by combining with the housing EDC.

[0070] Figure 2 This is a cross-sectional view of a display panel according to some embodiments of the present invention. Figure 3 This is a plan view of a display panel according to some embodiments of the present invention.

[0071] like Figure 2 As shown, the display panel DP includes a substrate layer BL, a circuit element layer DP-CL positioned on the substrate layer BL, a display element layer DP-OLED, and a thin-film encapsulation layer TFE. According to some embodiments, the display panel DP may also include functional layers such as an anti-reflective layer and a refractive index control layer.

[0072] The substrate layer BL may include a synthetic resin film. A synthetic resin layer is formed on a working substrate used in manufacturing the display panel DP. Subsequently, a conductive layer and an insulating layer are formed on the synthetic resin layer. When the working substrate is removed, the synthetic resin layer corresponds to the substrate layer BL. The synthetic resin layer may be a polyimide resin layer, and the material of the synthetic resin layer is not specifically limited to this. Alternatively, the substrate layer BL may include a glass substrate, a metal substrate, or an organic / inorganic composite material substrate, etc.

[0073] The circuit element layer DP-CL includes at least one insulating layer and circuit elements. Hereinafter, the insulating layer included in the circuit element layer DP-CL is referred to as the intermediate insulating layer. The intermediate insulating layer includes at least one intermediate inorganic film and at least one intermediate organic film. The circuit elements include signal lines and pixel driving circuits, etc. The circuit element layer DP-CL can be formed by processes such as coating and deposition to form the insulating layer, semiconductor layer, and conductive layer, and by processes such as photolithography to pattern the insulating layer, semiconductor layer, and conductive layer.

[0074] The DP-OLED display element layer includes light-emitting elements. The DP-OLED display element layer may include organic light-emitting diodes. The DP-OLED display element layer may also include organic films such as pixel-defining films.

[0075] A thin-film encapsulation layer (TFE) seals the display element layer of a DP-OLED. The TFE includes at least one insulating layer. In some embodiments of the present invention, the TFE may include at least one inorganic film (hereinafter referred to as the encapsulating inorganic film). In some embodiments of the present invention, the TFE may include at least one organic film (hereinafter referred to as the encapsulating organic film) and at least one encapsulating inorganic film.

[0076] An inorganic encapsulation film protects the DP-OLED display element layer from moisture / oxygen, while an organic encapsulation film protects the DP-OLED display element layer from foreign matter such as dust particles. The inorganic encapsulation film may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, but the embodiments of the present invention are not specifically limited thereto. The organic encapsulation layer may include an acrylic organic film, and is not specifically limited thereto.

[0077] Figure 3 The display panel, the first circuit board MPCB, and the second circuit board FPCB are shown.

[0078] like Figure 3 As shown, on a plane, the display panel DP includes a display area DA and a non-display area NDA. According to some embodiments, the non-display area NDA may be defined along the boundary of the display area DA.

[0079] The display panel (DP) may include a driver circuit (GDC), multiple signal lines (SGL) (hereinafter referred to as signal lines SGL), multiple signal pads (DP-PD) (hereinafter referred to as signal pads DP-PD), and multiple pixels (PX) (hereinafter referred to as pixels PX). Pixels PX are positioned within the display area (DA). Each pixel PX includes an organic light-emitting diode (OLED) and pixel driver circuitry connected to the OLED. The driver circuit (GDC), signal lines (SGL), signal pads (DP-PD), and pixel driver circuitry may be included... Figure 3 The circuit element layer DP-CL shown (see Figure 2 )middle.

[0080] The driving circuit GDC may include a scan driving circuit. The scan driving circuit generates multiple scan signals (hereinafter referred to as scan signals) and sequentially outputs the scan signals to multiple scan lines GL (hereinafter referred to as scan lines GL), which will be described later. The scan driving circuit may further output another control signal to the driving circuit of the pixel PX.

[0081] The scan driving circuit may include multiple thin-film transistors formed using the same process as the driving circuit of the pixel PX (e.g., low-temperature polycrystalline silicon (LTPS) process or low-temperature polycrystalline oxide (LTPO) process).

[0082] The signal line SGL includes multiple scan lines GL, multiple data lines DL, a power line PL, and a control signal line CSL. The multiple scan lines GL are connected to corresponding pixels PX, and the multiple data lines DL are also connected to corresponding pixels PX. The power line PL is connected to the pixels PX. The control signal line CSL provides control signals to the scan drive circuit.

[0083] The signal line SGL overlaps with the display area DA and the non-display area NDA. The signal line SGL may include a pad portion and a line portion. The line portion overlaps with the display area DA and the non-display area NDA. The pad portion is connected to the end of the line portion. The pad portion is located in the non-display area NDA and overlaps with the corresponding signal pad DP-PD among the signal pads DP-PD. The area in the non-display area NDA where the signal pad DP-PD is located can be defined as the pad area NDA-PD.

[0084] Basically, the line portion connected to pixel PX constitutes most of the signal line SGL. The line portion connects to transistors T1 and T2 of pixel PX (see...). Figure 5 The line portion may have a single-layer / multi-layer structure, and the line portion may be a single body, or may include two or more portions. The two or more portions are positioned on different layers and can be connected to each other through contact holes penetrating the insulating layer positioned between the two or more portions.

[0085] The display panel (DP) may also include dummy pads located in the pad area NDA-PD. Because the dummy pads are formed using the same process as the signal lines (SGL), they can be located in the same layer as the signal lines (SGL). The dummy pads can be floating electrodes.

[0086] Figure 3 The first circuit board MPCB and the second circuit board FPCB, which are electrically connected to the display panel DP, are shown.

[0087] The first circuit board MPCB and the second circuit board FPCB can be rigid or flexible circuit boards. The first circuit board MPCB can be connected to the display panel DP via the second circuit board FPCB. The second circuit board FPCB is electrically connected to the display panel DP via the signal pads DP-PD of the display panel DP.

[0088] The first circuit board (MPCB) may include various driving elements that provide a first drive signal for controlling the operation of the display panel (DP). For example, the first circuit board (MPCB) may include power components, etc. A driver chip (DC) for controlling the operation of the display panel (DP) may be located on a second circuit board (FPCB). Because various components, such as timing control circuits, are installed to control the display panel (DP), the driver chip (DC) can provide a second drive signal to the display panel (DP).

[0089] Figure 4 This is an equivalent circuit diagram of a pixel PX according to some embodiments of the present invention. Figure 5 This is an enlarged cross-sectional view of a display panel according to some embodiments of the present invention.

[0090] Figure 4 The diagram shows a scan line GL, a data line DL, a power line PL, and a pixel PX connected to them. The construction of the pixel PX is not limited to... Figure 4 And it can be modified for implementation.

[0091] An organic light-emitting diode (OLED) can be a front-surface LED or a rear-surface LED. A pixel PX includes a first transistor T1 (or a switching transistor), a second transistor T2 (or a driving transistor), and a capacitor Cst as a pixel driving circuit for driving the OLED. A first power voltage ELVDD is provided to the second transistor T2 via a power line PL, and a second power voltage ELVSS is provided to the OLED. The second power voltage ELVSS can be a voltage lower than the first power voltage ELVDD.

[0092] It can be achieved through a second circuit board FPCB (see Figure 3 The power lines from the first circuit board MPCB (see...) Figure 3 It provides a first power voltage ELVDD and a second power voltage ELVSS. A related description will be given later.

[0093] The first transistor T1 outputs a data signal applied to the data line DL in response to a scan signal applied to the scan line GL. The capacitor Cst is charged with a voltage corresponding to the data signal received from the first transistor T1. The second transistor T2 is connected to the organic light-emitting diode (OLED). The second transistor T2 controls the driving current flowing through the OLED in response to the amount of charge stored in the capacitor Cst.

[0094] The equivalent circuit is merely an example, and embodiments of the inventive concept are not limited thereto. The pixel PX may also include multiple transistors and may include a greater number of capacitors. That is, according to some embodiments, the pixel PX may include additional electrical components and / or differently arranged electrical components without departing from the spirit and scope of the embodiments according to this disclosure. The organic light-emitting diode (OLED) may be connected between the power line PL and the second transistor T2.

[0095] Figure 5 Is with Figure 4 The diagram shows a partial cross-sectional view of the display panel DP corresponding to the equivalent circuit shown.

[0096] The circuit element layer DP-CL, the display element layer DP-OLED, and the thin-film encapsulation layer TFE are sequentially positioned on the substrate layer BL. According to some embodiments, the circuit element layer DP-CL may include not only a buffer film BFL as an inorganic film, a first intermediate inorganic film IL1, and a second intermediate inorganic film IL2, but also an intermediate organic film IL3 as an organic film. The materials of the inorganic and organic films are not specifically limited thereto, and in some embodiments of the inventive concept, the buffer film BFL may be selectively arranged / omitted.

[0097] The semiconductor pattern OSP1 of the first transistor T1 (hereinafter referred to as the first semiconductor pattern OSP1) and the semiconductor pattern OSP2 of the second transistor T2 (hereinafter referred to as the second semiconductor pattern OSP2) are positioned on the buffer film BFL. The first semiconductor pattern OSP1 and the second semiconductor pattern OSP2 may be selected from any suitable semiconductor material including, for example, amorphous silicon, polycrystalline silicon and metal oxide semiconductor, or formed from any suitable semiconductor material including, for example, amorphous silicon, polycrystalline silicon and metal oxide semiconductor.

[0098] The first intermediate inorganic film IL1 is positioned on the first semiconductor pattern OSP1 and the second semiconductor pattern OSP2. The control electrode GE1 of the first transistor T1 (hereinafter referred to as the first control electrode GE1) and the control electrode GE2 of the second transistor T2 (hereinafter referred to as the second control electrode GE2) are positioned on the first intermediate inorganic film IL1. The first control electrode GE1 and the second control electrode GE2 can be positioned according to the scan line GL (see...). Figure 4 It is manufactured using the same photolithography process as the photolithography process.

[0099] A second intermediate inorganic film IL2 covering the first control electrode GE1 and the second control electrode GE2 is positioned on the first intermediate inorganic film IL1. The input electrode DE1 (hereinafter referred to as the first input electrode DE1) and output electrode SE1 (hereinafter referred to as the first output electrode SE1) of the first transistor T1, and the input electrode DE2 (hereinafter referred to as the second input electrode DE2) and output electrode SE2 (hereinafter referred to as the second output electrode SE2) of the second transistor T2 are positioned on the second intermediate inorganic film IL2.

[0100] The first input electrode DE1 and the first output electrode SE1 are connected to the first semiconductor pattern OSP1 through a first via CH1 and a second via CH2 penetrating the first intermediate inorganic film IL1 and the second intermediate inorganic film IL2, respectively. The second input electrode DE2 and the second output electrode SE2 are connected to the second semiconductor pattern OSP2 through a third via CH3 and a fourth via CH4 penetrating the first intermediate inorganic film IL1 and the second intermediate inorganic film IL2, respectively. Furthermore, according to some embodiments of the present invention, for implementation purposes, a portion of the first transistor T1 and the second transistor T2 can be converted into a bottom-gate structure (e.g., at least one of the first transistor T1 and the second transistor T2 can be converted into a bottom-gate structure).

[0101] An intermediate organic film IL3, covering the first input electrode DE1, the second input electrode DE2, the first output electrode SE1, and the second output electrode SE2, is positioned on the second intermediate inorganic film IL2. The intermediate organic film IL3 can provide a flat surface.

[0102] The display element layer DP-OLED is positioned on the intermediate organic film IL3. The display element layer DP-OLED may include a pixel-defining film PDL and an organic light-emitting diode (OLED). The pixel-defining film PDL may include organic materials. A first electrode AE ​​is positioned on the intermediate organic film IL3. The first electrode AE ​​is connected to a second output electrode SE2 through a fifth through-hole CH5 penetrating the intermediate organic film IL3. An opening OP is defined in the pixel-defining film PDL. The opening OP of the pixel-defining film PDL exposes at least a portion of the first electrode AE. In some embodiments of the present invention, the pixel-defining film PDL may be omitted.

[0103] As mentioned above Figure 3 As shown, pixel PX can be positioned within display area DA. Display area DA may include a light-emitting area PXA and a non-light-emitting area NPXA adjacent to the light-emitting area PXA. The non-light-emitting area NPXA may surround the light-emitting area PXA. According to some embodiments, the light-emitting area PXA is defined as a portion of the area corresponding to the first electrode AE ​​exposed by the opening OP.

[0104] According to some embodiments of the present invention, the light-emitting region PXA may overlap with at least one of the first transistor T1 and the second transistor T2. The opening OP may be wider, and the first electrode AE ​​and the light-emitting layer EML, which will be described later, may also be wider.

[0105] The hole control layer HCL can be commonly arranged in the light-emitting region PXA and the non-light-emitting region NPXA. According to some embodiments, a common layer such as the hole control layer HCL can be commonly formed in the pixel PX (see [link to embodiment]). Figure 4 )middle.

[0106] The emissive layer EML is positioned on the hole control layer HCL. The emissive layer EML can be positioned in the region corresponding to the opening OP. That is, the emissive layer EML can be formed individually in each pixel PX (see [link to EML]). Figure 4 The light-emitting layer (EML) can contain organic and / or inorganic materials. The EML can produce colored light (e.g., set or predetermined colored light).

[0107] According to some embodiments, as an example, a patterned emissive layer EML is shown; however, the emissive layer EML can be commonly arranged in pixels PX. In this case, the emissive layer EML can produce white light. Additionally, the emissive layer EML can have a multi-layer structure referred to as tandem.

[0108] The electronic control layer (ECL) is positioned on the light-emitting layer (EML). According to some embodiments, the ECL can be commonly formed on the pixel PX (see [link to embodiment]). Figure 4The second electrode CE is located on the electronic control layer ECL. The second electrode CE is commonly arranged in the pixel PX.

[0109] A thin-film encapsulation layer TFE is positioned on the second electrode CE. The thin-film encapsulation layer TFE is commonly positioned within a pixel PX. According to some embodiments, the thin-film encapsulation layer TFE directly covers the second electrode CE. According to some embodiments of the present invention, a cover layer covering the second electrode CE may be further positioned between the thin-film encapsulation layer TFE and the second electrode CE. In this case, the thin-film encapsulation layer TFE may directly cover the cover layer.

[0110] According to some embodiments of the present invention, an organic light-emitting diode (OLED) may further include a resonant structure for controlling the resonant distance of light generated from the emissive layer (EML). The resonant structure is positioned between a first electrode AE ​​and a second electrode CE, and the thickness of the resonant structure can be determined based on the wavelength of the light generated by the emissive layer (EML).

[0111] Figure 6A This is a plan view of a second circuit board according to some embodiments of the present invention. Figure 6B This is a perspective view of a second circuit board according to some embodiments of the present invention. Figure 7 This is a plan view of the chip mounting area of ​​a second circuit board according to some embodiments of the present invention. In the following, reference will be made to... Figures 6A to 7 Provide a description.

[0112] exist Figure 6A and Figure 6B In the middle, on the plane, the second circuit board FPCB is positioned between the first circuit board MPCB and the display panel DP to electrically connect the first circuit board MPCB and the display panel DP.

[0113] The second circuit board (FPCB) may have a first region (ICA) and a second region (ACA) defined within the second circuit board (FPCB). The first region (ICA) is a chip mounting area on which a driver chip (DC) is mounted, and the second region (ACA) is an active region surrounding the first region (ICA). Multiple lines and multiple pads may be positioned within the second region (ACA) of the second circuit board (FPCB). According to some embodiments, the second circuit board (FPCB) may include a first line 1L and a second line 2L, and the first line 1L and the second line 2L may be positioned within the second region (ACA). The driver chip (DC) may be mounted on the first region (ICA) (e.g., it may be arranged within the first region (ICA)).

[0114] The first line 1L may correspond to a driver chip power line, which is electrically connected to the driver chip DC to supply power to the driver chip DC. The first line 1L may include a line portion 1L-L and a pad portion 1L-P (see [link to documentation]). Figure 8 The line portion 1L-L is located in the second region ACA, and the pad portion 1L-P is located in the first region ICA. The first line 1L can be electrically connected to the driver chip DC through the pad portion 1L-P.

[0115] The second line 2L is electrically connected to the display panel DP and is not electrically connected to the driver chip DC (e.g., electrically insulated from the driver chip DC). The second line 2L may include multiple power lines (e.g., at least one power line) that supply power to the display panel DP. For example, the second line 2L may include a first power line 2L-1 and a second power line 2L-2. One of the first power line 2L-1 and the second power line 2L-2 can supply power to the pixels PX of the display panel DP (see...). Figure 4 Provides the first power voltage ELVDD (see...) Figure 4 Furthermore, the other of the first power line 2L-1 and the second power line 2L-2 can provide a second power voltage ELVSS to the pixels PX of the display panel DP (see...). Figure 4 ).

[0116] According to some embodiments, the second circuit board FPCB may include an input pad PI and an output pad PO. The input pad PI can electrically connect the first circuit board MPCB and the second circuit board FPCB. The output pad PO can electrically connect the second circuit board FPCB to the display panel DP.

[0117] According to some embodiments, the second circuit board FPCB can receive a first power voltage ELVDD from the first circuit board MPCB via input pad PI (see [link]). Figure 4 ) and second power voltage ELVSS (see Figure 4 And these voltages are supplied to the display panel DP via the output pad PO through the second line 2L.

[0118] Further reference Figure 7 The second power line 2L may include common lines 100 and 200 and multiple output lines SL. In an embodiment, the multiple output lines SL may have the same width. The multiple output lines SL may include first output lines SL1 to fourth output lines SL4. The first power line 2L-1 may include common line 100 and output lines SL1 to SL3. The second power line 2L-2 may include common line 200 and output lines SL4.

[0119] Common lines 100 and 200 can be located in the first zone ICA. Output line SL connects to common lines 100 and 200 and extends to the second zone ACA.

[0120] The first line 1L and the second line 2L can be connected to the display panel DP via the first area ICA, which serves as the chip mounting area. Common lines 100 and 200 of the second line 2L can be positioned within the first area ICA. The first line 1L is electrically connected to the driver chip DC within the first area ICA (see [link to relevant documentation]). Figure 6A Furthermore, the second line 2L can be connected to the display panel DP via the output line SL through the common lines 100 and 200 that bypass the first line 1L in the first region ICA. (Refer to...) Figures 8 to 10B Provide a more detailed description.

[0121] Figure 8 These are some embodiments of the concept of the present invention. Figure 7 A magnified view of a portion of the chip mounting area. Figure 8 yes Figure 7 A magnified view of region AA'.

[0122] Figure 8 The common line 100 and output lines SL1 to SL3 of the first power line 2L-1 in the second line 2L are shown.

[0123] Reference Figure 8 The first line 1L may include multiple pad portions 1L-P located in the first region ICA. The first line 1L may include multiple line portions 1L-L extending from the first region ICA to the second region ACA. Multiple line portions 1L-L may be provided, and the output lines SL1 to SL3 of the second line 2L may be positioned between the multiple line portions 1L-L.

[0124] The second line 2L may include a common line 100 and output lines SL1 to SL3 located in the first region ICA. The common line 100 is DC electrically insulated from the driver chip. The common line 100 is arranged to bypass multiple pad portions 1L-P.

[0125] Common line 100 may include a first portion 110, a second portion 120, and a third portion 130. The first portion 110 is connected to the first circuit board MPCB (see [link to MPCB]). Figure 6AThe first portion 110 is adjacent to the first portion 110 and extends in the first direction DR1. The second portion 120 extends perpendicularly from the first portion 110. That is, the second portion 120 extends from the end of the first portion 110 in the second direction DR2. In other words, the second portion 120 may have a first end connected to the first portion 110 and may extend from the first portion 110 in the second direction DR2, which is orthogonal to the first direction DR1, in a direction away from the first circuit board MPCB. The third portion 130 extends perpendicularly from the end of the second portion 120 that is not connected to the first portion 110. In other words, the third portion 130 may extend from the second end of the second portion 120 opposite to the first end in the first direction DR1. That is, the third portion 130 may be adjacent to the display panel DP (see...). Figure 6A ) are adjacent and extend in the first direction DR1.

[0126] To supply power from the first circuit board MPCB to the display panel DP, current flows from the first section 110 through the second section 120 to the third section 130. The current can be output to multiple output lines SL1 to SL3 connected to the common line 100 to flow to the display panel DP.

[0127] The width of the common line 100 gradually decreases (e.g., by segment or by portion) from the first portion 110 to the third portion 130. Here, the width may correspond to the length in a direction perpendicular to the longitudinal direction of the common line 100. That is, the first width WT1 of the first portion 110 may be greater than the second width WT2 of the second portion 120, and the second width WT2 of the second portion 120 may be greater than the third width WT3 of the third portion 130.

[0128] Common line 100 can be connected to multiple output lines SL1 to SL3, which extend to the second region ACA and connect to the display panel DP (see...). Figure 6A According to some embodiments, the first portion 110 can be connected to four first output lines SL1-1 to SL1-4. The second portion 120 can be connected to one second output line SL2-1. The third portion 130 can be connected to three third output lines SL3-1 to SL3-3. The width WT-X of the multiple output lines SL1 to SL3 can be the same as each other.

[0129] In the following text, it is assumed that the width WT-X of each of the output lines SL1 to SL3 is approximately 10 μm.

[0130] The width of the common line 100 can be proportional to the number of output lines SL1 to SL3 connected to it. For example, when the number of output lines SL1 to SL3 is 8, the width of the common line 100 can be approximately 80 μm, and when the number of output lines SL1 to SL3 is 16, the width of the common line 100 can be approximately 160 μm. When the number of output lines SL1 to SL3 is 4, the width of the common line 100 can be approximately 40 μm. That is, the width of the common line 100 and the number of output lines SL1 to SL3 can be provided in a ratio of 10 (μm): 1 (number).

[0131] The width of the common line 100 can be designed to be large enough for power stabilization. The ratio of the width of the common line 100 to the number of output lines SL1 to SL3 can be 10 + a (μm) : 1 (number). For example, when the number of multiple output lines SL1 to SL3 is 8, the width of the common line 100 can be approximately 100 μm. In this case, a is 20. That is, as the number of output lines SL1 to SL3 connected to the common line 100 increases, the width of the common line 100 can be increased.

[0132] According to some embodiments, as the common line 100 moves further away from the first circuit board MPCB (see...), Figure 6A And closer to the display panel DP (see) Figure 6A The width of the common line 100 is reduced.

[0133] According to some embodiments, the number of first output lines SL1 can be n, the number of second output lines SL2 can be m, and the number of third output lines SL3 can be l, where n is an integer greater than 0, m is an integer greater than 0, and l is an integer greater than 0.

[0134] In the following text, the width WT-X of each of the output lines SL1 to SL3 is referred to as x (i.e., is x). The first width WT1 of the first portion 110 of the common line 100 can be proportional to the sum of the number of first output lines SL1, the number of second output lines SL2, and the number of third output lines SL3. As n+m+l, which is the number of first output lines SL1 to third output lines SL3, increases, the first width WT1 increases to the value obtained by multiplying n+m+l by x.

[0135] exist Figure 8 In the above, when the number n of the first output lines SL1-1 to SL1-4 is 4, the number m of the second output lines SL2-1 is 1, and the number l of the third output lines SL3-1 to SL3-3 is 3, the first width WT1 can be approximately 80μm.

[0136] The second width WT2 of the second section 120 is less than the first width WT1. The second width WT2 can be proportional to the sum of the number of second output lines SL2 connected to the second section 120 and the number of third output lines SL3 connected to the third section 130. That is, as m+l, which is the number of second output lines SL2 and third output lines SL3, increases, the first width WT1 increases to the value obtained by multiplying m+l by x.

[0137] exist Figure 8 In this configuration, the number of second output lines SL2, m, is 1, and the number of third output lines SL3, l, is 3. The second width WT2 can be approximately 40 μm.

[0138] The third width WT3 of the third section 130 is smaller than the second width WT2. The third width WT3 can be proportional to the number of third output lines SL3 connected to the third section 130. That is, as l, which is the number of third output lines SL3, increases, the third width WT3 increases to the value obtained by multiplying l by x.

[0139] exist Figure 8 In this configuration, the number of third output lines SL3 is 3. The third width WT3 can be approximately 30 μm.

[0140] Each of the first width WT1, the second width WT2, and the third width WT3 can be designed to be large enough, i.e., increased by up to +a, where +a is in micrometers, for power stabilization. a can be a stability constant used for power stabilization. The stability constant a can correspond to (for example, it can be) twice the width WT-X of each of the output lines SL1 to SL3. That is, when the width WT-X of each output line SL1 to SL3 is approximately 10 μm, a can be 20.

[0141] In the embodiment, A = (n + m + l)x + a, B = (m + l)x + a, and C = lx + a, where the width of each output line in the plurality of output lines is x, A is the first width WT1, B is the second width WT2, C is the third width WT3, and the units of A, B, C, and x are micrometers. That is, in Figure 8 In this example, when n is 4, m is 1, and l is 3, the first width WT1 can be approximately 100 μm, the second width WT2 can be approximately 60 μm, and the third width WT3 can be approximately 50 μm. In this case, a is approximately 20. In the embodiment, the stability constant a can be 0.

[0142] Figure 9A and Figure 9B These are some embodiments of the concept of the present invention. Figure 7 A magnified view of a portion of the chip mounting area. Figure 9A yes Figure 7 A magnified view of region AA'. Figure 9B yes Figure 9A A magnified view of region XX'.

[0143] Reference Figure 9A As common line 100 moves further away from the first circuit board MPCB (see...) Figure 6A Furthermore, as it gets closer to the display panel DP, the width of the common line 100 can be gradually reduced.

[0144] Whenever the common line 100 passes through each of the multiple connected output lines SL1 to SL3, the width of the common line 100 can be reduced by the width WT-X of each of the output lines SL1 to SL3.

[0145] According to some embodiments, the width WT-X of each of the output lines SL1 to SL3 can be x, and the number of multiple output lines SL1 to SL3 can be z. The maximum width of the common line 100 can correspond to the value obtained by multiplying x by z. The width of the common line 100 has a maximum value when the common line 100 does not pass through the output lines SL1 to SL3 at all. That is, the width of the portion of the common line 100 closest to the first circuit board MPCB within the first region ICA can be the maximum.

[0146] The direction in which the common line 100 passes through the output lines SL1 to SL3 is called the travel direction, and the travel direction is defined as the direction of current flow. The current flow direction corresponds to the direction in which the distance from the first circuit board MPCB increases and the distance towards the display panel DP decreases.

[0147] Reference Figure 8 When the width WT-X of each of the output lines SL1 to SL3 is x and the number of the first output lines SL1 to the third output lines SL3 is (n+m+l), the maximum width of the common line 100 can correspond to the value obtained by multiplying (n+m+l) by x. For example, the first width WT1-1 of the common line 100 can correspond to approximately 80 μm, and when the stability constant a is added, the first width WT1-1 of the common line 100 can be approximately 80 μm to approximately 100 μm. That is, the maximum width can be approximately 80 μm to approximately 100 μm.

[0148] When the common line 100 passes the first output line SL1-1 from its first width WT1-1, the width of the common line 100 can be reduced by the width WT-X of the first output line SL1-1. Therefore, the second width WT1-2 can be approximately 70 μm to approximately 90 μm. After the common line 100 passes the second output line SL1-2, the third width WT1-3 can be approximately 60 μm to approximately 80 μm. After the common line 100 passes the third output line SL1-3, the fourth width WT1-4 can be approximately 50 μm to approximately 70 μm. After the common line 100 passes the fourth output line SL1-4, the fifth width WT1-5 can be approximately 40 μm to approximately 60 μm. After the common line 100 passes the first output line SL2-1, the sixth width WT2-1 can be approximately 30 μm to approximately 50 μm. After the common line 100 passes the first third output line SL3-1, the seventh width WT3-1 can be approximately 20μm to approximately 40μm. After the common line 100 passes the second third output line SL3-2, the eighth width WT3-2 can be approximately 10μm to approximately 30μm. After the common line 100 passes the third third output line SL3-3, the final width WT3-3 can be approximately 10μm to approximately 30μm. That is, the minimum width of the common line 100 can be approximately 10μm to approximately 30μm. Because there are no output lines after the final width WT3-3, the final width WT3-3 can be the same as the eighth width WT3-2.

[0149] According to some embodiments, the minimum width of the common line 100 can be the same as the width WT-X of each output line.

[0150] The widths of the common lines WT1-1 to WT3-3 are proportional to the total number of output lines subsequently positioned in the direction of travel. The widths of the common lines WT1-1 to WT3-3 can be obtained by multiplying the width of each output line WT-X by the total number of output lines subsequently positioned.

[0151] For example, since there are 7 output lines after the second width WT1-2, the second width WT1-2 can be approximately 70 μm, which is obtained by multiplying 7 by approximately 10 μm, which is the width WT-X of each output line.

[0152] Since there are no output lines after this, the final width WT3-3 can be the same as the eighth width WT3-2.

[0153] Reference Figure 9BThe reduced width WT-Y of the common line 100 can be the same as the width WT-X of each output line. The third width WT1-3 can be obtained by subtracting the reduced width WT-Y, which is equal to the width WT-X of the second first output line SL1-2, from the second width WT1-2.

[0154] exist Figure 9B In the middle, the second first output line SL1-2 can be located in the first line 1L located in the second region ACA (see Figure 7 The line portion 1L-L is between multiple output lines SL (see [link]). Figure 7 It can extend to the second region ACA and can be positioned between the line portion 1L-L of the first line 1L.

[0155] Figure 10A and Figure 10B These are some embodiments of the concept of the present invention. Figure 7 A magnified view of a portion of the chip mounting area. Figure 10A yes Figure 7 A magnified view of region BB'. Figure 10B yes Figure 10A A magnified view of region YY'.

[0156] Second line 2L (see Figure 7 This may include the first power line 2L-1 (see...) Figure 6A ) and the second power line 2L-2 (see Figure 6A First power line 2L-1 (see...) Figure 6A ) and the second power line 2L-2 (see Figure 6A They can be positioned adjacent to each other, with the pad portion 1L-P of the first line 1L located between the first electric field line 2L-1 (see...). Figure 6A ) and the second power line 2L-2 (see Figure 6A )between.

[0157] Reference Figure 10A First power line 2L-1 (see Figure 6A ) and the second power line 2L-2 (see Figure 6A The common line 200 of any of the power lines may include a first common portion 210 extending in the direction opposite to the first direction DR1 and a second common portion 220 extending in the first direction DR1. The second power line 2L-2 will be described below.

[0158] The first common portion 210 and the second common portion 220 of the second power line 2L-2 are arranged symmetrically to each other. As the first common portion 210 and the second common portion 220 become further apart from each other, the width of the first common portion 210 and the width of the second common portion 220 can be reduced respectively.

[0159] Second line 2L (see Figure 7 It may include multiple output lines SL4 that are connected to the common line 200 and extend to the second area ACA.

[0160] According to some embodiments, multiple output lines SL4 can be connected to the extended first common portion 210 and second common portion 220, respectively. Because the first common portion 210 and the second common portion 220 are symmetrical to each other, the number of multiple output lines SL4 located in the first common portion 210 and the number of multiple other output lines located in the second common portion 220 can be the same. The multiple output lines SL4 may include output lines SL4-1 to SL4-4.

[0161] exist Figure 10A The output lines SL4-1 to SL4-4 of the first common section 210 are described in the text.

[0162] The width of the first common portion 210 of the common line 200, from WT4-1 to WT4-4, can gradually decrease from the first output line SL4-1 to the fourth output line SL4-4.

[0163] According to some embodiments, the first width WT4-1 has a maximum value. The common line 200 includes a first common portion 210 and a second common portion 220, and the width of each of the first common portion 210 and the second common portion 220 can have a maximum value of approximately 40 μm. The second width WT4-2 can have a value obtained by subtracting the width of one of the multiple output lines SL4 from the first width WT4-1. That is, the second width WT4-2 can be approximately 30 μm. The third width WT4-3 is approximately 20 μm, and the fourth width WT4-4 is approximately 10 μm. The fourth width WT4-4 is the same as the width of each of the output lines SL4-1 to SL4-4.

[0164] The width of the common line 200 can be proportional to the number of output lines SL4. That is, as the number of output lines SL4 increases, the total width of the common line 200 can increase.

[0165] The difference between the maximum and minimum values ​​of the widths of the common lines WT4-1 to WT4-4 can be proportional to the number of output lines SL4-1 to SL4-4. Figure 10AIn the case of four output lines SL4, the maximum width of the first common portion 210 is approximately 40 μm, and the minimum width is approximately 10 μm, with a difference of approximately 30 μm. When three output lines SL4 are present, the maximum width is approximately 40 μm, and the minimum width is approximately 20 μm, with a difference of approximately 20 μm in this case. That is, the number of output lines SL4 can be proportional to the difference between the maximum and minimum widths of the common line 200.

[0166] The sum of the widths of the first common portion 210 and the second common portion 220 corresponds to approximately 80 μm. First electric field line 2L-1 (see...) Figure 7 The maximum width of the common line 100 can correspond to approximately 80 μm.

[0167] Reference Figure 10B There is a difference in width WT-Y between the first width WT4-1 and the second width WT4-2 of the first common portion 210. The reduced width WT-Y can be the same as the width WT-X of the first output line SL4-1.

[0168] The output line SL4-1 extending from the first common portion 210 of the first region ICA to the second region ACA can be located between the line portions 1L-L of multiple first lines.

[0169] Display devices according to some embodiments of the present invention can spatially and efficiently arrange power lines in the display panel on a driver chip. Display devices according to some embodiments of the present invention can reduce the width of the power lines and increase the space occupied by other lines.

[0170] As described above, embodiments have been disclosed in the accompanying drawings and specification. Although specific terminology has been used herein, it is for the purpose of describing the invention only and is not intended to limit the meaning or scope of the invention as described in the claims. Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments are thus possible. Consequently, the true technical scope of protection of the invention should be determined by the technical concept of the appended claims and their equivalents.

Claims

1. A display device, wherein, The display device includes: The display panel has pixels arranged in it. A first circuit board is configured to provide a first drive signal to the display panel; and A second circuit board, connecting the display panel and the first circuit board, has a first region and a second region surrounding the first region. A driver chip providing a second drive signal to the display panel is disposed in the first region, and the first region and the second region are defined within the second circuit board. in: The second circuit board includes a first wire electrically connected to the driver chip and a second wire electrically insulated from the driver chip; The second line includes a common line located in the first region; and On a plane, the width of the common line decreases as it moves further away from the first circuit board.

2. The display device according to claim 1, wherein, The common line includes: The first portion is adjacent to the first circuit board and extends in a first direction; The second portion has a first end connected to the first portion and extends from the first portion in a second direction orthogonal to the first direction in a direction away from the first circuit board; and The third part extends in the first direction from the second end of the second part opposite to the first end and is adjacent to the display panel. Wherein, the first width of the first part is greater than the second width of the second part, and the second width is greater than the third width of the third part.

3. The display device according to claim 1, wherein, The second line includes at least one power line configured to provide power to the display panel.

4. The display device according to claim 2, wherein, The second line also includes multiple output lines extending from the common line to the second region, and the multiple output lines have the same width.

5. The display device according to claim 4, wherein, The multiple output lines include: n first output lines connected to the first part, m second output lines connected to the second part, and l third output lines connected to the third part, where n is an integer greater than 0, m is an integer greater than 0, and l is an integer greater than 0.

6. The display device according to claim 5, wherein, The number of the plurality of output lines connected to the common line is proportional to the width of the common line.

7. The display device according to claim 5, wherein: The first width of the first portion is proportional to the sum of the number of the first output lines, the number of the second output lines, and the number of the third output lines; The second width of the second portion is proportional to the sum of the number of the second output lines and the number of the third output lines; and The third width of the third portion is proportional to the number of the third output lines.

8. The display device according to claim 5, wherein, A = (n + m + l)x + a, B = (m + l)x + a, and C = lx + a, where the width of each of the plurality of output lines is x, A is the first width, B is the second width, C is the third width, the units of A, B, C and x are micrometers, and a is a stability constant.

9. The display device according to claim 8, wherein, The stability constant is 0.

10. The display device according to claim 8, wherein, The stability constant is twice the width of each of the plurality of output lines.

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