Pixel circuit and display panel

Abstract

Embodiments of the present application disclose a pixel circuit and a display panel. The pixel circuit comprises a driving unit, a light-emitting unit, a first writing unit, a second writing unit, a time length adjusting unit and a signal selection unit. The driving unit is configured to drive the light-emitting unit to emit light according to a first power supply. The first writing unit is configured to write a first data voltage and a compensation voltage to a first node of the driving unit. The second writing unit is configured to write a second data voltage to a first node of the time length adjusting unit. The signal selection unit is configured to select a sweep signal output by a different signal selection circuit. The time length adjusting unit is configured to control a time length of a current flowing through the light-emitting unit according to the sweep signal output by the signal selection circuit selected by the signal selection unit, the second data voltage, the first power supply, the first data voltage and the compensation voltage. According to the embodiments of the present application, the light-emitting time length can be controlled.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a pixel circuit and a display panel. BACKGROUND

[0002] Micro LED display device has been paid more and more attention due to its low driving voltage, long service life and wide temperature resistance. Micro LED display is a current-driven light-emitting display unit, which is different from liquid crystal voltage-driven. Current-type control needs to control the current passing through the TFT to control the current passing through the Micro LED. Therefore, in the case of low gray scale, the voltage of data is relatively small, and the brightness difference caused by current difference is not obvious in the range of a minimum unit voltage, which leads to the loss of some gray scale and the inability to control the light-emitting duration. SUMMARY

[0003] The embodiments of the present application disclose a pixel circuit and a display panel, which can select different driving modes to improve the gray scale loss or display failure in the case of low gray scale, and control the light-emitting duration.

[0004] The first aspect of the embodiments of the present application discloses a pixel circuit, comprising a driving unit, a light-emitting unit, a first writing unit, a second writing unit, a duration adjusting unit and a signal selection unit.

[0005] The driving unit is configured to drive the light-emitting unit to emit light according to a first power supply.

[0006] The first writing unit is configured to write a first data voltage and a compensation voltage to a first node of the driving unit.

[0007] The second writing unit is configured to write a second data voltage to a first node of the duration adjusting unit.

[0008] The signal selection unit is configured to select a sweep signal output by different signal selection circuits.

[0009] The duration adjusting unit is configured to control the duration of the current flowing through the light-emitting unit according to the sweep signal output by the signal selection circuit selected by the signal selection unit, the second data voltage, the first power supply, the first data voltage and the compensation voltage.

[0010] As an optional implementation, in the first aspect of the embodiments of the present application, the signal selection unit comprises three signal selection circuits, each of which comprises a thin film transistor and a coupling capacitor, and the capacitance values of each of the coupling capacitors are different.

[0011] The first electrode of each of the thin film transistors is connected to the sweep signal, the gate electrode of each of the thin film transistors is connected to an opening signal, and the second electrode of each of the thin film transistors is connected to one end of a corresponding coupling capacitor and a second node of the time length adjustment unit.

[0012] The other end of each of the coupling capacitors is connected to a third power supply.

[0013] As an optional implementation, in the first aspect of the embodiment, the driving unit includes a first thin film transistor, a second thin film transistor, a third thin film transistor, and a first capacitor.

[0014] The first electrode of the first thin film transistor is connected to the first power supply, a third node of the time length adjustment unit, and one end of the first capacitor, and the second electrode of the first thin film transistor is connected to a first node of the first write unit and a first electrode of the second thin film transistor.

[0015] The second electrode of the second thin film transistor is connected to a first electrode of the third thin film transistor and a second node of the first write unit.

[0016] The second electrode of the third thin film transistor is connected to the light emitting unit.

[0017] The gate electrode of the first thin film transistor and the gate electrode of the third thin film transistor are connected to a first start signal, and the gate electrode of the second thin film transistor is connected to a fourth node of the first write unit, a third node of the time length adjustment unit, and the other end of the first capacitor.

[0018] As an optional implementation, in the first aspect of the embodiment, the first write unit includes a fourth thin film transistor and a fifth thin film transistor.

[0019] The first electrode of the fourth thin film transistor is connected to the first data voltage, and the second electrode of the fourth thin film transistor is connected to the second electrode of the first thin film transistor and the first electrode of the second thin film transistor.

[0020] The first electrode of the fifth thin film transistor is connected to the second electrode of the second thin film transistor and the first electrode of the third thin film transistor, and the second electrode of the fifth thin film transistor is connected to the gate electrode of the second thin film transistor, a fourth node of the time length adjustment unit, and the other end of the first capacitor.

[0021] The gate electrode of the fourth thin film transistor and the gate electrode of the fifth thin film transistor are connected to a second start signal.

[0022] As an optional implementation, in the first aspect of the embodiment, the second writing unit comprises a sixth thin film transistor;

[0023] The first electrode of the sixth thin film transistor is connected with the second data voltage, and the second electrode of the sixth thin film transistor is connected with the first node of the time length adjusting unit;

[0024] The gate electrode of the sixth thin film transistor is connected with the second start signal.

[0025] As an optional implementation, in the first aspect of the embodiment, the time length adjusting unit comprises a seventh thin film transistor, an eighth thin film transistor and a second capacitor;

[0026] The first electrode of the seventh thin film transistor is connected with the first power supply, the first electrode of the first thin film transistor and one end of the first capacitor respectively, and the second electrode of the seventh thin film transistor is connected with the first electrode of the eighth thin film transistor respectively;

[0027] The second electrode of the eighth thin film transistor is connected with the second electrode of the fifth thin film transistor, the gate electrode of the second thin film transistor and the other end of the first capacitor respectively;

[0028] The gate electrode of the seventh thin film transistor is connected with the second electrode of the sixth thin film transistor and one end of the second capacitor respectively, and the gate electrode of the eighth thin film transistor is connected with a control signal;

[0029] The other end of the second capacitor is connected with one end of each of the coupling capacitors in the signal selection unit.

[0030] As an optional implementation, in the first aspect of the embodiment, the circuit further comprises a reset unit;

[0031] The reset unit is configured to adjust the voltage of the first node of the driving unit and the first node of the time length adjusting unit to a reference voltage.

[0032] As an optional implementation, in the first aspect of the embodiment, the reset unit comprises a ninth thin film transistor, a tenth thin film transistor and an eleventh thin film transistor;

[0033] The first electrode of the ninth thin film transistor is connected with the input end of the light emitting unit and the second electrode of the third thin film transistor respectively, the second electrode of the ninth thin film transistor is connected with the reference voltage, the first electrode of the tenth thin film transistor and the first electrode of the eleventh thin film transistor respectively;

[0034] The second electrode of the tenth thin film transistor is connected with the second electrode of the eighth thin film transistor, the second electrode of the fifth thin film transistor, the gate electrode of the second thin film transistor and the other end of the first capacitor respectively;

[0035] The second electrode of the eleventh thin film transistor is connected with the gate electrode of the seventh thin film transistor, the second electrode of the sixth thin film transistor and one end of the second capacitor respectively.

[0036] The gate electrode of the ninth thin film transistor, the gate electrode of the tenth thin film transistor and the gate electrode of the eleventh thin film transistor are connected with the third start signal respectively.

[0037] As an optional implementation, in the first aspect of the embodiment, the capacitance value of the coupling capacitor in the signal selection circuit selected by the signal selection unit is in a positive correlation with the time length of the current flowing through the light-emitting unit controlled by the time length adjustment unit.

[0038] The second aspect of the embodiment provides a display panel, comprising a plurality of pixel circuits, wherein the pixel circuit is any one of the pixel circuits disclosed in the embodiment.

[0039] As an optional implementation, in the second aspect of the embodiment, the display panel comprises a display area and an edge area located at the periphery of the display area, and the driving unit, the light-emitting unit, the first writing unit, the second writing unit and the time length adjustment unit are located in the display area, and the signal selection unit is arranged in the edge area.

[0040] As an optional implementation, in the second aspect of the embodiment, the edge area comprises a wiring area and a blank area.

[0041] The signal selection unit is arranged in the blank area.

[0042] Compared with the related art, the embodiment has the following beneficial effects:

[0043] The pixel circuit of the present application comprises a driving unit, a light-emitting unit, a first writing unit, a second writing unit, a time length adjusting unit and a signal selection unit. The driving unit is configured to drive the light-emitting unit to emit light according to a first power supply; the first writing unit is configured to write a first data voltage and a compensation voltage to a first node of the driving unit; the second writing unit is configured to write a second data voltage to a first node of the time length adjusting unit; the signal selection unit is configured to select a sweep signal output by a different signal selection circuit; and the time length adjusting unit is configured to control the time length of current flowing through the light-emitting unit according to the sweep signal output by the signal selection circuit selected by the signal selection unit, the second data voltage, the first power supply, the first data voltage and the compensation voltage. Different driving modes can be selected to improve the loss of gray scale or poor display in the case of low gray scale, and the light-emitting time length can be controlled. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0045] Figure 1 is a structural schematic diagram of a pixel circuit disclosed by an embodiment of the present application;

[0046] Figure 2 is a driving timing diagram of a pixel circuit disclosed by an embodiment of the present application;

[0047] Figure 3 is a schematic diagram of voltage and current change over time of a pixel circuit disclosed by an embodiment of the present application;

[0048] Figure 4 is a structural schematic diagram of a display panel disclosed by an embodiment of the present application;

[0049] Wherein, the reference signs are: 10, driving unit; 20, light emitting unit; 30, first writing unit; 40, second writing unit; 50, time length adjusting unit; 60, signal selecting unit; 70, resetting unit; T1, first thin film transistor; T2, second thin film transistor; T3, third thin film transistor; T4, fourth thin film transistor; T5, fifth thin film transistor; T6, sixth thin film transistor; T7, seventh thin film transistor; T8, eighth thin film transistor; T9, ninth thin film transistor; T10, tenth thin film transistor; T11, eleventh thin film transistor; EM, first start signal; G(n), second start signal; G(n-1), third start signal; Control, control signal; Data1, first data voltage; Data2, second data voltage; C1, first capacitor; C2, second capacitor; Ca, coupling capacitor; Cb, coupling capacitor; Cc, coupling capacitor; S1, on signal; S2, on signal; S3, on signal; Sweep, sweep signal; VDD, first power supply; VSS, third power supply; Vref, reference voltage. DETAILED DESCRIPTION

[0050] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0051] It should be noted that the terms "comprising" and "having" and any variations thereof in the embodiments of the present application and the drawings are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed, or can optionally include other steps or units inherent to the process, method, product or device.

[0052] The embodiments of the present application disclose a pixel circuit and a display panel, which can select different driving modes to improve gray scale loss or display defects in a low gray scale case, and can control light emitting time length. The following are described in detail respectively.

[0053] Please refer to Figure 1 , Figure 1 is a structural schematic diagram of a pixel circuit disclosed by the embodiments of the present application. As shown in Figure 1As shown, the pixel circuit provided in the embodiment of the present application can be used in a display panel to emit display light. Specifically, the pixel circuit can include a driving unit 10, a light emitting unit 20, a first writing unit 30, a second writing unit 40, a time length adjusting unit 50, and a signal selection unit 60.

[0054] The driving unit 10 is configured to drive the light emitting unit 20 to emit light according to the first power supply.

[0055] The first writing unit 30 is configured to write a first data voltage and a compensation voltage to a first node of the driving unit 10.

[0056] The second writing unit 40 is configured to write a second data voltage to a first node of the time length adjusting unit 50.

[0057] The signal selection unit 60 is configured to select a sweep signal output by a different signal selection circuit.

[0058] The time length adjusting unit 50 is configured to control a time length of a current flowing through the light emitting unit 20 according to the sweep signal output by the signal selection circuit selected by the signal selection unit 60, the second data voltage, the first power supply, the first data voltage, and the compensation voltage.

[0059] In the embodiment of the present application, the light emitting unit 20 can be a current-driven light emitting device including a Micro LED (Micro Light Emitting Diode) in the prior art, which is taken as an example in the embodiment of the present application.

[0060] In the above embodiment, the first writing unit 30 writes the first data voltage and the compensation voltage to the Q node in the circuit, wherein the compensation voltage is an internal compensation voltage generated when the gate and the drain of the thin film transistor are connected; the second writing unit 40 writes the second data voltage to the g node in the circuit, so that the driving unit 10 is turned on and outputs the current to the light emitting unit 20 to make it emit light. Then, after the signal selection unit 60 selects the sweep signal output by the different signal selection circuit, the sweep signal is coupled with the second data voltage to make the time length adjusting unit 50 conductive, and after the time length adjusting unit 50 is conductive, the voltage at the Q node is coupled with the first power supply to make the driving unit 10 turn off, so that the light emitting unit 20 stops emitting light. In this process, the signal selection unit 60 selects the sweep signal output by the different signal selection circuit to control the speed of the time length adjusting unit 50 to turn on, thereby realizing the control of the light emitting time length of the light emitting unit 20.

[0061] Please refer to Figure 1In one embodiment, the signal selection unit 60 can include three signal selection circuits, each of which includes a thin film transistor and a coupling capacitor, and each of the coupling capacitors has a different capacitance value;

[0062] The first electrode of each thin film transistor is connected to a sweep signal, the gate electrode of each thin film transistor is connected to an opening signal, and the second electrode of each thin film transistor is connected to one end of a corresponding coupling capacitor and the second node of the time length adjustment unit 50.

[0063] The other end of each coupling capacitor is connected to a third power supply.

[0064] The driving unit 10 includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, and a first capacitor C1. The first electrode of the first thin film transistor T1 is connected to a first power supply, the third node of the time length adjustment unit 50, and one end of the first capacitor. The second electrode of the first thin film transistor T1 is connected to the first node of the first write unit 30 and the first electrode of the second thin film transistor T2. The second electrode of the second thin film transistor T2 is connected to the first electrode of the third thin film transistor T3 and the second node of the first write unit 30. The second electrode of the third thin film transistor T3 is connected to the light emitting unit 20. The gate electrode of the first thin film transistor T1 and the gate electrode of the third thin film transistor T3 are connected to a first start signal. The gate electrode of the second thin film transistor T2 is connected to the fourth node of the first write unit 30, the third node of the time length adjustment unit 50, and the other end of the first capacitor.

[0065] The first write unit 30 includes a fourth thin film transistor T4 and a fifth thin film transistor T5. The first electrode of the fourth thin film transistor T4 is connected to a first data voltage. The second electrode of the fourth thin film transistor T4 is connected to the second electrode of the first thin film transistor T1 and the first electrode of the second thin film transistor T2. The first electrode of the fifth thin film transistor T5 is connected to the second electrode of the second thin film transistor T2 and the first electrode of the third thin film transistor T3. The second electrode of the fifth thin film transistor T5 is connected to the gate electrode of the second thin film transistor T2, the fourth node of the time length adjustment unit 50, and the other end of the first capacitor. The gate electrode of the fourth thin film transistor T4 and the gate electrode of the fifth thin film transistor T5 are connected to a second start signal.

[0066] The second write unit 40 includes a sixth thin film transistor T6. The first electrode of the sixth thin film transistor T6 is connected to a second data voltage. The second electrode of the sixth thin film transistor T6 is connected to the first node of the time length adjustment unit 50. The gate electrode of the sixth thin film transistor T6 is connected to a second start signal.

[0067] The time length adjusting unit 50 comprises a seventh thin film transistor T7, an eighth thin film transistor T8 and a second capacitor; the first pole of the seventh thin film transistor T7 is connected with the first power supply, the first pole of the first thin film transistor T1 and one end of the first capacitor respectively, the second pole of the seventh thin film transistor T7 is connected with the first pole of the eighth thin film transistor T8 respectively; the second pole of the eighth thin film transistor T8 is connected with the second pole of the fifth thin film transistor T5, the gate of the second thin film transistor T2 and the other end of the first capacitor respectively; the gate of the seventh thin film transistor T7 is connected with the second pole of the sixth thin film transistor T6 and one end of the second capacitor respectively, the gate of the eighth thin film transistor T8 is connected with a control signal; the other end of the second capacitor is connected with one end of each coupling capacitor in the signal selection unit 60.

[0068] Please refer to Figure 1 In one embodiment, the pixel circuit further comprises a reset unit 70.

[0069] The reset unit 70 is configured to adjust the voltage of the first node of the driving unit 10 and the first node of the time length adjusting unit 50 to a reference voltage.

[0070] The reset unit 70 comprises a ninth thin film transistor T9, a tenth thin film transistor T10 and an eleventh thin film transistor T11; the first pole of the ninth thin film transistor T9 is connected with the input end of the light emitting unit 20 and the second pole of the third thin film transistor T3 respectively, the second pole of the ninth thin film transistor T9 is connected with the reference voltage, the first pole of the tenth thin film transistor T10 and the first pole of the eleventh thin film transistor T11 respectively; the second pole of the tenth thin film transistor T10 is connected with the second pole of the eighth thin film transistor T8, the second pole of the fifth thin film transistor T5, the gate of the second thin film transistor T2 and the other end of the first capacitor respectively; the second pole of the eleventh thin film transistor T11 is connected with the gate of the seventh thin film transistor T7, the second pole of the sixth thin film transistor T6 and one end of the second capacitor respectively; the gate of the ninth thin film transistor T9, the gate of the tenth thin film transistor T10 and the gate of the eleventh thin film transistor T11 are connected with a third start signal respectively.

[0071] In the embodiments of the present application, all the thin film transistors are P-type transistors, but in other embodiments, the above P-type transistors or P-type transistors are not limited. It should be noted that for a P-type accumulation mode transistor, when the applied V GS is a positive voltage, the device works in a depletion mode, the current carriers of the conductive channel are depleted, a high channel resistance is generated, and the device is in an off state; when the applied V GS is a negative voltage, the device works in an accumulation mode, a large number of current carriers are accumulated at the interface between the semiconductor layer and the insulating layer, a low-resistance conductive channel is formed, and the device is in an on state.

[0072] In the embodiments of the present application, please refer to Figure 2 , Figure 2 The timing diagram disclosed in an embodiment is based on the pixel circuit in Figure 1 and the timing in Figure 2 The process of controlling the light-emitting duration of the light-emitting unit 20 includes:

[0073] In the write and compensation phase t1, the second start signal G(n) is input with a low level, at this time, the fourth thin film transistor T4, the fifth thin film transistor T5 and the sixth thin film transistor T6 are turned on, at this time, since the first electrode and the second electrode of the fifth thin film transistor T5 are connected to the gate and the second electrode of the second thin film transistor T2 respectively, the second thin film transistor T2 is slightly turned on, so that the first data voltage is sequentially written into the Q node in the circuit through the fourth thin film transistor T4, the second thin film transistor T2 and the fifth thin film transistor T5, and since the first electrode and the second electrode of the fifth thin film transistor T5 are connected to the gate and the second electrode of the second thin film transistor T2 respectively, internal circuit compensation occurs, so that the voltage V th is stored into the Q node in the circuit together with the first data voltage. After the sixth thin film transistor T6 is turned on, the second data voltage is written into the g node in the circuit through the sixth thin film transistor T6.

[0074] Wherein, the current formula (1) is:

[0075] I ds =k×[(V GS -V th )V ds -1 / 2×V ds ^2] (1)

[0076] Wherein, I ds is the source-drain current of the second thin film transistor T2, V ds is the source-drain voltage of the second thin film transistor T2, k is the temperature coefficient of the offset voltage, V GS is the gate-source voltage of the second thin film transistor T2, V th is the compensation voltage. Since I ds =0, it can be obtained that V GS =V th . Therefore, V GS =Vg(Q point voltage)-Vs(first data voltage Data1)=Vth, it can be seen that the Q point voltage is Vs(first data voltage Data1)+V th .

[0077] In the light-emitting stage t2, the second start signal G(n) and the third start signal G(n-1) are inputted with high level, and the first start signal EM is inputted with low level, so the fourth thin film transistor T4, the fifth thin film transistor T5 and the sixth thin film transistor T6 are closed, and the first thin film transistor T1 and the third thin film transistor T3 are opened. Since in the writing and compensation stage t1, the node Q in the circuit is written with the first data voltage and the compensation voltage, the third thin film transistor T3 is opened in the light-emitting stage t2. The first power supply is inputted to the MicroLED through the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3, so that the MicroLED emits light.

[0078] Meanwhile, the Sweep voltage outputted by the signal selection unit 60 is linearly reduced from high level, and is pulled to low level in the process of the continuous light emission of the MicroLED, at this time, the Sweep voltage and the second data voltage written at the g point form a capacitive coupling through the second capacitor, and the capacitive coupling will couple the voltage at the g point to low level over time. Since the control signal is low level in the light-emitting stage t2, the eighth thin film transistor T8 is opened, and the time length adjusting unit 50 is connected with the driving unit 10. In the light-emitting stage t2, when the voltage at the g point is reduced to the threshold voltage of the seventh thin film transistor T7 by the capacitive coupling of the Sweep voltage from the second data voltage, the seventh thin film transistor T7 is opened, and the voltage at the Q point is pulled up to the voltage value of the first power supply from the sum of the voltage values of the first data voltage and the compensation voltage through the seventh thin film transistor T7. At this time, the second thin film transistor T2 is closed because the voltage at the Q point is pulled up, and the MicroLED stops emitting light because there is no current passing through the second thin film transistor T2.

[0079] Therefore, after the second data voltage is written at the g point and enters the light-emitting stage t2, the seventh thin film transistor T7 is opened by the capacitive coupling of the Sweep voltage and the second data voltage, so that the time length adjusting unit 50 is connected with the driving unit 10, and then the first power supply is coupled with the first data voltage and the compensation voltage to close the second thin film transistor T2. Therefore, the time when the time length adjusting unit 50 is connected with the driving unit 10 can be controlled by controlling the capacitive coupling speed of the Sweep voltage and the second data voltage, and then the light-emitting time length of the light-emitting unit 20 can be controlled.

[0080] In one embodiment, please refer to Figure 1 and Figure 2 The process of realizing the light-emitting time length control of the light-emitting unit 20 further includes:

[0081] In the reset stage t0, the third start signal G(n-1) is input to a low level, the ninth thin film transistor T9, the tenth thin film transistor T10 and the eleventh thin film transistor T11 are turned on, at this time, the reference voltage is transmitted through the ninth thin film transistor T9, the tenth thin film transistor T10 and the eleventh thin film transistor T11 respectively, and the voltage of the Q node, the voltage of the g node and the voltage of the MicroLED input end in the circuit are pulled to the value of the reference voltage. The key nodes in the circuit return to the same voltage reference point at the beginning of each frame and then start data writing, which can ensure that the voltage state of the important nodes is consistent before each data writing.

[0082] In one embodiment, please refer to Figure 3 , Figure 3 The voltage and current change over time diagram disclosed in an embodiment is shown. In the embodiment of the present application, the capacitance value of the capacitor Cc in the signal selection unit 60 is greater than the capacitance value of the capacitor Cb, and the capacitance value of the capacitor Cb is greater than the capacitance value of the capacitor Ca. Figure 3 The time-varying diagram of the voltage of the g point in the circuit and the sweep frequency signal are capacitively coupled to achieve the turn-on voltage of the seventh thin film transistor T7 when the coupling capacitors in the signal selection circuit selected by the signal selection unit 60 are the capacitor Ca, the capacitor Cb and the capacitor Cc is shown in FIG. 6. Figure 3 The time-varying diagram of the current flowing through the light-emitting unit 20 when the coupling capacitors in the signal selection circuit selected by the signal selection unit 60 are the capacitor Ca, the capacitor Cb and the capacitor Cc is also shown in FIG. 6. Figure 3 Therefore, in combination with FIG. 6 and the size relationship of the capacitance values of the capacitor Ca, the capacitor Cb and the capacitor Cc, it can be known that when the coupling capacitor in the signal selection circuit selected by the signal selection unit 60 is larger, the time for the voltage of the g point to be capacitively coupled to a low level to turn on the seventh thin film transistor T7 is also longer, and then the time for the current to flow through the light-emitting unit 20 is also longer, that is, the light-emitting time of the light-emitting unit 20 is also longer. Therefore, the capacitance value of the coupling capacitor in the signal selection circuit selected by the signal selection unit 60 is in a positive correlation relationship with the time length of the current flowing through the light-emitting unit 20 controlled by the time length adjusting unit 50.

[0083] In the embodiment of the present application, please refer to Figure 1In the signal selection unit 60, three signal selection circuits are included. The first signal selection circuit includes a thin film transistor and a coupling capacitor Ca, and the thin film transistor is controlled to be turned on or turned off by an opening signal S1. The second signal selection circuit includes a thin film transistor and a coupling capacitor Cb, and the thin film transistor is controlled to be turned on or turned off by an opening signal S2. The third signal selection circuit includes a thin film transistor and a coupling capacitor Cc, and the thin film transistor is controlled to be turned on or turned off by an opening signal S3. When the opening signal is at a low level, the corresponding thin film transistor is turned on. Therefore, according to the relationship between the coupling speed of the capacitor value and the g-point voltage and the light-emitting duration of the light-emitting unit 20, the coupling capacitor of the appropriate signal selection circuit can be better selected by each opening signal, so as to effectively control the light-emitting duration of the light-emitting unit 20.

[0084] In an embodiment, a display panel is provided, including a plurality of pixel circuits, and each pixel circuit is the pixel circuit described in any of the above embodiments.

[0085] In the embodiments of the present application, the display panel can be a micro light-emitting diode (Micro-LED) display panel or an organic light-emitting diode (OLED) display panel, and can be applied to any product with a display function, such as electronic paper, mobile phones, tablet computers, televisions, displays, notebook computers, digital photo frames, navigation devices, etc.

[0086] In an embodiment, please refer to Figure 4 , Figure 4 The structure diagram of the display panel disclosed in an embodiment is shown. The display panel 400 includes a display area 410 and an edge area located at the periphery of the display area, and the driving unit, the light-emitting unit, the first writing unit, the second writing unit, and the duration adjusting unit are all located in the display area 410, and the signal selection unit is arranged in the edge area.

[0087] In some embodiments, the reset unit is also located in the display area 410. The reset unit is located in the display area, which can better combine the reset phase with the writing and compensation phase and the light-emitting phase.

[0088] In an embodiment, please refer to Figure 4 again, the edge area includes a wiring area 420 and a blank area 430, and the signal selection unit is arranged in the blank area 430. Each signal selection unit on the blank area corresponds to a pixel circuit. By integrating the signal selection unit added to the conventional pixel circuit into the edge area or even the blank area of the display panel, the cost can be reduced, and the wiring condition of the conventional pixel circuit on the display panel is not affected.

[0089] It should be understood that every feature, structure, or characteristic described in relation to one embodiment is applicable to at least one other embodiment, unless the context clearly dictates otherwise. Thus, it is intended that such individual features, structures, or characteristics are not necessarily limited to a single embodiment. In addition, it should be understood that the features, structures, or characteristics described in the specification are not necessarily all inclusive unless the context indicates otherwise. Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0090] In various embodiments of the present application, it should be understood that the magnitude of the serial number of the above processes does not mean the inevitable sequence of execution, and the execution sequence of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0091] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e. they may be located in one place, or they may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0092] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0093] The pixel circuit and display panel disclosed in the embodiments of the present application are described in detail above, and the principles and implementation modes of the present application are described by applying specific examples. The above embodiment description is only used to help understand the method of the present application and its core idea. Meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed, and the above description should not be understood as a limitation on the present application.

Claims

1. A pixel circuit, characterized in that, It includes a driving unit, a light-emitting unit, a first writing unit, a second writing unit, a duration adjustment unit, and a signal selection unit; The driving unit is used to drive the light-emitting unit to emit light according to the first power supply; The first writing unit is used to write a first data voltage and a compensation voltage to the first node of the driving unit; The second writing unit is used to write a second data voltage to the first node of the duration adjustment unit; The signal selection unit is used to select different signal selection circuit output sweep signals; The duration adjustment unit is used to control the duration of current flowing through the light-emitting unit based on the sweep frequency signal output by the signal selection circuit selected by the signal selection unit, the second data voltage, the first power supply, the first data voltage, and the compensation voltage. The signal selection unit includes three signal selection circuits, each of which includes a thin-film transistor and a coupling capacitor, and the capacitance values ​​of each coupling capacitor are different. The first electrode of each of the thin film transistors is connected to the sweep frequency signal, the gate of each of the thin film transistors is connected to an enable signal, and the second electrode of each of the thin film transistors is connected to one end of the corresponding coupling capacitor and the second node of the duration adjustment unit. The other end of each of the coupling capacitors is connected to a third power source.

2. The circuit according to claim 1, characterized in that, The driving unit includes a first thin-film transistor, a second thin-film transistor, a third thin-film transistor, and a first capacitor; The first electrode of the first thin-film transistor is connected to the first power supply, the third node of the duration adjustment unit and one end of the first capacitor, respectively; the second electrode of the first thin-film transistor is connected to the first node of the first writing unit and the first electrode of the second thin-film transistor, respectively. The second electrode of the second thin-film transistor is connected to the first electrode of the third thin-film transistor and the second node of the first write unit, respectively; The second electrode of the third thin-film transistor is connected to the light-emitting unit; The gates of the first thin-film transistor and the third thin-film transistor are connected to the first start signal, and the gates of the second thin-film transistor are connected to the fourth node of the first writing unit, the third node of the duration adjustment unit, and the other end of the first capacitor, respectively.

3. The circuit according to claim 2, characterized in that, The first writing unit includes a fourth thin-film transistor and a fifth thin-film transistor; The first terminal of the fourth thin-film transistor is connected to the first data voltage, and the second terminal of the fourth thin-film transistor is connected to the second terminal of the first thin-film transistor and the first terminal of the second thin-film transistor, respectively. The first terminal of the fifth thin-film transistor is connected to the second terminal of the second thin-film transistor and the first terminal of the third thin-film transistor, respectively. The second terminal of the fifth thin-film transistor is connected to the gate of the second thin-film transistor, the fourth node of the duration adjustment unit, and the other end of the first capacitor, respectively. The gates of the fourth and fifth thin-film transistors are respectively connected to the second start signal.

4. The circuit according to claim 3, characterized in that, The second writing unit includes a sixth thin-film transistor; The first electrode of the sixth thin-film transistor is connected to the second data voltage, and the second electrode of the sixth thin-film transistor is connected to the first node of the duration adjustment unit; The gate of the sixth thin-film transistor is connected to the second start signal.

5. The circuit according to claim 4, characterized in that, The duration adjustment unit includes a seventh thin-film transistor, an eighth thin-film transistor, and a second capacitor; The first terminal of the seventh thin-film transistor is connected to the first power supply, the first terminal of the first thin-film transistor, and one end of the first capacitor, respectively; the second terminal of the seventh thin-film transistor is connected to the first terminal of the eighth thin-film transistor, respectively. The second terminal of the eighth thin-film transistor is connected to the second terminal of the fifth thin-film transistor, the gate of the second thin-film transistor, and the other end of the first capacitor, respectively. The gate of the seventh thin-film transistor is connected to the second electrode of the sixth thin-film transistor and one end of the second capacitor, respectively; the gate of the eighth thin-film transistor is connected to the control signal. The other end of the second capacitor is connected to one end of each of the coupling capacitors in the signal selection unit.

6. The circuit according to claim 5, characterized in that, The circuit also includes a reset unit; The reset unit is used to adjust the voltage of the first node of the drive unit and the first node of the duration adjustment unit to the reference voltage.

7. The circuit according to claim 6, characterized in that, The reset unit includes a ninth thin-film transistor, a tenth thin-film transistor, and an eleventh thin-film transistor; The first terminal of the ninth thin-film transistor is connected to the input terminal of the light-emitting unit and the second terminal of the third thin-film transistor, respectively. The second terminal of the ninth thin-film transistor is connected to the reference voltage, the first terminal of the tenth thin-film transistor, and the first terminal of the eleventh thin-film transistor, respectively. The second terminal of the tenth thin-film transistor is connected to the second terminal of the eighth thin-film transistor, the second terminal of the fifth thin-film transistor, the gate of the second thin-film transistor, and the other end of the first capacitor, respectively. The second terminal of the eleventh thin-film transistor is connected to the gate of the seventh thin-film transistor, the second terminal of the sixth thin-film transistor, and one end of the second capacitor, respectively. The gates of the ninth thin-film transistor, the tenth thin-film transistor, and the eleventh thin-film transistor are respectively connected to the third start signal.

8. The circuit according to any one of claims 1 to 7, characterized in that, The capacitance value of the coupling capacitor in the signal selection circuit selected by the signal selection unit is positively correlated with the duration of the control current flowing through the light-emitting unit by the duration adjustment unit.

9. A display panel, characterized in that, It includes multiple pixel circuits, wherein the pixel circuits are the pixel circuits described in any one of claims 1 to 8.

10. The display panel according to claim 9, characterized in that, The display panel includes a display area and an edge area located around the display area. The driving unit, the light-emitting unit, the first writing unit, the second writing unit, and the duration adjustment unit are all located in the display area, and the signal selection unit is located in the edge area.

11. The display panel according to claim 10, characterized in that, The edge region includes a trace area and a blank area; The signal selection unit is located in the blank area.

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