A method for fabricating a finfet device polysilicon cut

Abstract

The application provides a preparation method of a FinFET device polysilicon cutting, a semiconductor structure comprising a substrate, a plurality of Fin structures arranged along a transverse direction on the substrate, an oxide layer, a plurality of polysilicon strip structures arranged along a longitudinal direction on the oxide layer, and an interlayer dielectric layer filled between the polysilicon strip structures and covering the Fin structures; a hard mask layer is covered on the upper surface of the semiconductor structure; a first photo mask is used to define a plurality of first polysilicon cutting regions; the hard mask layer is etched to the upper surface of the polysilicon strip structure until the upper surface is exposed; a second photo mask is used to define a plurality of second polysilicon cutting regions; the hard mask layer is etched to the upper surface of the polysilicon strip structure until the upper surface is exposed; the hard mask layer is etched further downward to a height of 300 angstroms of the polysilicon strip structure, and then the etching is stopped to form a groove; and the polysilicon strip structure in the groove is etched to expose the substrate.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a FinFET device by cutting polysilicon. Background Technology

[0002] To address the challenge of not being able to simultaneously fabricate Poly Line and POC due to the miniaturization of 7nm process devices, this invention extends the polysilicon dicing process (POC Loop) to be fabricated after the interlayer dielectric layer process (ILD0 Loop), thus overcoming the process difficulties brought about by device miniaturization.

[0003] In SRAM, polysilicon cuts (POCs) can be placed in two ways: between the N-fin and the P-fin, and between two N-fins. Design rules stipulate that only when the distance between the POC and the fin is greater than 23nm can the subsequent DPR process completely remove the short-bar polysilicon. Therefore, when placing POCs, those between N-fins are placed in the middle of the fin, and those between N-fins and P-fins are placed 23nm away from the N-fin (3.5nm away from the P-fin). Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for fabricating polysilicon cutting for FinFET devices, which solves the problem that polysilicon lines and polysilicon cutting cannot be fabricated simultaneously due to the miniaturization of 7nm process devices in the prior art.

[0005] To achieve the above and other related objectives, the present invention provides a method for fabricating a FinFET device by dicing polysilicon, comprising at least:

[0006] Step 1: Provide a semiconductor structure, the semiconductor structure including a substrate, a plurality of Fin structures arranged laterally on the substrate, an oxide layer covering the substrate and the Fin structures, a plurality of polysilicon strip structures arranged longitudinally on the oxide layer, and an interlayer dielectric layer covering the Fin structures filling the spaces between the polysilicon strip structures.

[0007] Step 2: Cover the upper surface of the semiconductor structure with a hard mask layer;

[0008] Step 3: Define multiple first polysilicon cutting regions using photolithography with the first photomask;

[0009] Step 4: Etch the hard mask layer according to the defined plurality of first polysilicon cutting regions until the upper surface of the polysilicon strip structure is exposed;

[0010] Step 5: Define multiple second polysilicon cutting regions using second-light photolithography;

[0011] Step 6: Etch the hard mask layer according to the defined plurality of second polysilicon cutting regions until the upper surface of the polysilicon strip structure is exposed;

[0012] Step 7: Continue etching the semiconductor structure downwards according to the shape of the hard mask layer etched in Steps 4 and 6, until the height of the polysilicon strip structure removed is 300 angstroms, and stop etching to form a trench;

[0013] Step 8: Etch away the polysilicon strip structure in the trench until the substrate is exposed.

[0014] Preferably, the plurality of Fin structures in step one include N-type Fin structures and P-type Fin structures.

[0015] Preferably, the material of the hard mask layer in step two is SiN.

[0016] Preferably, the method for defining the first polysilicon dicing region in step three includes: sequentially spin-coating a SOC layer, a Si anti-reflection layer, and a photoresist onto the hard mask layer; and then exposing and developing the first polysilicon dicing region to reveal it.

[0017] Preferably, the method for defining the plurality of second polysilicon dicing regions in step six includes: sequentially spin-coating a SOC layer, a Si anti-reflection layer, and a photoresist onto the hard mask layer; followed by exposure and development to reveal the second polysilicon dicing regions.

[0018] Preferably, each of the first polysilicon dicing regions in step four is located at the midpoint between two adjacent N-type Fin structures.

[0019] Preferably, each of the second polysilicon dicing regions in step six is ​​located between two adjacent N-type Fin structures and P-type Fin structures.

[0020] Preferably, in step six, each of the second polysilicon dicing regions is 23 nm away from its nearest N-type Fin structure and 3.5 nm away from its nearest P-type Fin structure.

[0021] Preferably, the plurality of first polysilicon cutting regions in step four and the plurality of second polysilicon cutting regions in step six are placed alternately.

[0022] Preferably, this method is applicable to the process technology of the 7nm technology node.

[0023] As described above, the method for fabricating FinFET devices using polysilicon dicing according to the present invention has the following beneficial effects: The present invention is used for 7nm polysilicon dicing, employing two photomasks and a semi-detached process to complete the polysilicon dicing process. In the semi-detached process, the interlayer dielectric oxide layer plays a role in isolating and protecting the P-type Fin, avoiding damage to the top of the Fin due to polysilicon dicing etching. Attached Figure Description

[0024] Figure 1 The diagram shown is a cross-sectional view of the semiconductor structure of the present invention.

[0025] Figure 2 The diagram shown is a cross-sectional view of the etched hard mask layer of the present invention to expose the upper surface of the polysilicon strip structure;

[0026] Figure 3 The diagram shows a longitudinal cross-sectional view of the polysilicon strip structure with etched trenches in this invention, extending to the exposed substrate.

[0027] Figure 4 The diagram shown is a longitudinal cross-sectional view of the semiconductor structure of the present invention.

[0028] Figure 5 The diagram shows a longitudinal cross-section of the first polysilicon dicing region defined in this invention.

[0029] Figure 6 The diagram shows a longitudinal cross-sectional view of the trench formed by etching the semiconductor structure in this invention.

[0030] Figure 7 The diagram shows a cross-sectional view of the polysilicon strip structure with etched trenches in this invention, extending to the exposed substrate.

[0031] Figure 8 The diagram shows a three-dimensional structural schematic of the semiconductor structure in this invention.

[0032] Figure 9 The diagram shows a three-dimensional structure of the semiconductor structure in this invention, in which first and second polysilicon dicing regions are formed. Detailed Implementation

[0033] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0034] Please see Figures 1 to 9 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0035] This invention provides a method for fabricating a FinFET device by cutting polysilicon, comprising at least the following steps:

[0036] Step 1: Provide a semiconductor structure, the semiconductor structure including a substrate, a plurality of Fin structures arranged laterally on the substrate, an oxide layer covering the substrate and the Fin structures, a plurality of polysilicon strip structures arranged longitudinally on the oxide layer, and an interlayer dielectric layer covering the Fin structures filling the spaces between the polysilicon strip structures; as shown Figure 1 As shown, Figure 1 The diagram shown is a cross-sectional view of the semiconductor structure of the present invention. The semiconductor structure in step one includes a substrate, a plurality of Fin structures arranged laterally at intervals on the substrate, and an oxide layer covering the substrate and the Fin structures; as shown... Figure 4 As shown, Figure 4 The diagram shown is a longitudinal cross-sectional view of the semiconductor structure of the present invention. The semiconductor structure further includes a plurality of polysilicon strip structures (poly) arranged longitudinally on the oxide layer, and an interlayer dielectric layer 05 covering the Fin structure filling the spaces between the polysilicon strip structures (poly).

[0037] Furthermore, in step one of this embodiment, the plurality of Fin structures include N-type Fin structures and P-type Fin structures.

[0038] Step 2: Cover the upper surface of the semiconductor structure with a hard mask layer; such as... Figure 4 As shown, in step two, a hard mask layer 04 is covered on the upper surface of the semiconductor structure.

[0039] Furthermore, in this embodiment, the material of the hard mask layer 04 in step two is SiN.

[0040] Step 3: Define multiple first polysilicon cutting regions using photolithography with the first photomask;

[0041] Further, in step three of this embodiment, the method for defining the first polysilicon dicing region includes: sequentially spin-coating a SOC layer, a Si anti-reflection layer, and photoresist onto the hard mask layer; followed by exposure and development to reveal the first polysilicon dicing region. Figure 5 As shown, Figure 5 The diagram shown is a longitudinal cross-sectional view of the first polysilicon cutting region defined in this invention. Figure 5 The SOC layer (SOC), Si anti-reflective layer (Si-ARC), and photoresist (PR) are all identified by 0 and 1.

[0042] Step 4: Etch the hard mask layer according to the defined plurality of first polysilicon cutting regions until the upper surface of the polysilicon strip structure is exposed; as follows: Figure 2 As shown, Figure 2 The diagram shows a cross-sectional view of the etching of the hard mask layer to expose the upper surface of the polysilicon strip structure according to the present invention. Step four involves etching the hard mask layer (NM SIN) to expose the upper surface of the polysilicon strip structure (poly). Figure 2 The 02 mark represents the first polysilicon cutting region formed after etching the hard mask layer.

[0043] In a further step of this invention, each of the first polysilicon dicing regions in step four of this embodiment is located at the midpoint between two adjacent N-type Fin structures.

[0044] Step 5: Define multiple second polysilicon dicing regions using a second photomask; such as... Figure 8 and Figure 9 As shown, Figure 8 The diagram shows a three-dimensional structural schematic of the semiconductor structure of this invention. The semiconductor structure includes a substrate 06 and a plurality of Fin structures arranged laterally on the substrate. Figure 8 and Figure 9 (Not shown), an oxide layer covering the substrate 06 and the Fin structures, a plurality of polysilicon strip structures 07 arranged longitudinally on the oxide layer, and an interlayer dielectric layer 05 covering the Fin structures filling the spaces between the polysilicon strip structures 07. Figure 9 The diagram shows a three-dimensional structure of the semiconductor structure in this invention, in which first and second polysilicon dicing regions are formed. For example, 08 and 11 represent the first polysilicon dicing region, and 09 and 10 represent the second polysilicon dicing region.

[0045] Step 6: Etch the hard mask layer according to the defined plurality of second polysilicon cutting regions until the upper surface of the polysilicon strip structure is exposed;

[0046] Further, in step six of this embodiment, the method for defining the plurality of second polysilicon dicing regions includes: sequentially spin-coating a SOC layer, a Si anti-reflection layer, and a photoresist onto the hard mask layer; followed by exposure and development to reveal the second polysilicon dicing regions. Figures 1 to 7 The second polysilicon dicing region is not shown.

[0047] In a further embodiment of the present invention, each of the second polysilicon dicing regions in step six is ​​located between two adjacent N-type Fin structures and P-type Fin structures.

[0048] Furthermore, in step six of this embodiment, the distance between each of the second polysilicon dicing regions and its nearest N-type Fin structure is 23 nm; and the distance between it and its nearest P-type Fin structure is 3.5 nm.

[0049] Furthermore, in this embodiment, the plurality of first polysilicon dicing regions in step four and the plurality of second polysilicon dicing regions in step six are arranged alternately. For example... Figure 9 As shown, 08 and 11 are the first polysilicon cutting regions; 09 and 10 are the second polysilicon cutting regions.

[0050] Step 7: Continue etching the semiconductor structure downwards according to the shape of the hard mask layer etched in Steps 4 and 6, stopping the etching when the height of the polysilicon strip structure removed reaches 300 angstroms, forming a trench; Figure 6 As shown, Figure 6 The diagram shows a longitudinal cross-sectional view of the trench formed by etching the semiconductor structure in this invention.

[0051] Step 8: Etch away the polysilicon strip structure within the trench until the substrate is exposed. For example... Figure 3 and Figure 7 As shown, where Figure 3 The diagram shows a longitudinal cross-sectional view of the polysilicon strip structure with etched trenches in this invention, extending to the exposed substrate. Figure 7 The diagram shows a cross-sectional view of the polysilicon strip structure with etched trenches in this invention, extending to the exposed substrate. Figure 3 The 03 in the diagram represents the first polysilicon cutting region formed after etching the polysilicon strip structure.

[0052] Furthermore, the method of this embodiment is applicable to the process technology of the 7nm technology node.

[0053] In summary, this invention is used for 7nm polysilicon dicing, employing a two-mask, semi-detached process to complete the polysilicon dicing process. In the semi-detached process, the interlayer dielectric oxide layer acts as an isolation and protection layer for the P-type fins, preventing damage to the top of the fins due to polysilicon dicing etching. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0054] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a FinFET device by cutting polysilicon, characterized in that, At least including: Step 1: Provide a semiconductor structure, the semiconductor structure including a substrate, a plurality of Fin structures arranged laterally on the substrate, an oxide layer covering the substrate and the Fin structures, a plurality of polysilicon strip structures arranged longitudinally on the oxide layer, and an interlayer dielectric layer covering the Fin structures filling the spaces between the polysilicon strip structures; the plurality of Fin structures include N-type Fin structures and P-type Fin structures; Step 2: Cover the upper surface of the semiconductor structure with a hard mask layer; Step 3: Define multiple first polysilicon dicing regions using photolithography with a first photomask; each first polysilicon dicing region is located in the middle position between two adjacent N-type Fin structures; Step 4: Etch the hard mask layer according to the defined plurality of first polysilicon cutting regions until the upper surface of the polysilicon strip structure is exposed; Step 5: Define multiple second polysilicon dicing regions using a second photomask; each second polysilicon dicing region is located between two adjacent N-type Fin structures and P-type Fin structures; Step 6: Etch the hard mask layer according to the defined plurality of second polysilicon cutting regions until the upper surface of the polysilicon strip structure is exposed; Step 7: Continue etching the semiconductor structure downwards according to the shape of the hard mask layer etched in Steps 4 and 6 to form trenches; Step 8: Etch away the polysilicon strip structure in the trench until the substrate is exposed.

2. The method for fabricating FinFET devices by polysilicon dicing according to claim 1, characterized in that: In step seven, the semiconductor structure is etched downwards until the height of the polysilicon strip structure removed is 300 angstroms, at which point the etching stops, forming a trench.

3. The method for fabricating FinFET devices by polysilicon dicing according to claim 2, characterized in that: The material of the hard mask layer mentioned in step two is SiN.

4. The method for fabricating a FinFET device by polysilicon dicing according to claim 2, characterized in that: The method for defining the first polysilicon dicing region in step three includes: sequentially spin-coating a SOC layer, a Si anti-reflection layer, and a photoresist onto the hard mask layer; then exposing and developing the first polysilicon dicing region to reveal it.

5. The method for fabricating a FinFET device by polysilicon dicing according to claim 4, characterized in that: The method for defining the plurality of second polysilicon dicing regions in step six includes: sequentially spin-coating a SOC layer, a Si anti-reflection layer, and a photoresist onto the hard mask layer; and then exposing and developing the second polysilicon dicing regions.

6. The method for fabricating a FinFET device by polysilicon dicing according to claim 1, characterized in that: In step six, each of the second polysilicon dicing regions is 23 nm away from its nearest N-type Fin structure and 3.5 nm away from its nearest P-type Fin structure.

7. The method for fabricating a FinFET device by polysilicon dicing according to claim 1, characterized in that: The plurality of first polysilicon cutting regions and the plurality of second polysilicon cutting regions are placed alternately.

8. The method for fabricating a FinFET device by polysilicon dicing according to claim 1, characterized in that: This method is applicable to the 7nm technology node process.

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