An NVM memory cell

Abstract

The present invention is applicable to the storage technology field, and provides a NVM storage cell, which includes a P-type doped substrate, an NMOS transistor, two PN junction diodes, and an N-well capacitor. The NMOS transistor, the two PN junction diodes, and the N-well capacitor are all disposed on the P-type doped substrate. Wherein, the positions of the two PN junction diodes and the NMOS transistor form an active region, a first part of a polycrystalline gate is deposited in the active region, the first part of the polycrystalline gate is surrounded by the active region, and the P+-type implanted doping of the two PN junction diodes surrounds both sides of the first part of the polycrystalline gate. The NVM storage cell in the present invention solves the problems of leakage generated by the NMOS transistor itself after radiation and the leakage between two adjacent NMOS transistors.

Description

Technical Field

[0001] The present invention belongs to the field of storage technology, and particularly relates to a NVM storage cell. Background Art

[0002] NVM is a non-volatile memory. This floating-gate storage cell stores data by changing the threshold of the storage cell through the amount of charge stored in the floating gate, and the identification of data is achieved by comparing the conduction currents of storage cells with different thresholds. However, the floating-gate storage cell is vulnerable to space radiation and loses data, especially affected by the total dose effect, that is, the leakage current of the storage cell increases, resulting in data identification failure.

[0003] The main factor for the traditional storage cell affected by the total dose effect is caused by STI field oxide leakage, such as Figure 4 shown, the STI field oxide leakage mainly includes the leakage current of the parasitic channel of the NMOS transistor after irradiation and the leakage current of the conductive channel formed by the field oxide between two adjacent NMOS transistors. Summary of the Invention

[0004] An embodiment of the present invention provides a NVM storage cell, aiming to solve the problem of data loss in the traditional storage cell due to the influence of space radiation.

[0005] An embodiment of the present invention provides a NVM storage cell, including a P-type doped substrate, an NMOS transistor, two PN junction diodes, and an N-well capacitor. The NMOS transistor, the two PN junction diodes, and the N-well capacitor are all disposed on the P-type doped substrate. The two PN junction diodes are respectively electrically connected to the source terminal and the drain terminal of the NMOS transistor. A first parasitic channel and a second parasitic channel are respectively provided on the sides of the two PN junction diodes away from the NMOS transistor, and the N-well capacitor is disposed on the other side of the second parasitic channel.

[0006] Wherein, the positions of the two PN junction diodes and the NMOS transistor form an active region, a first part of the polycrystalline gate is deposited in the active region, the first part of the polycrystalline gate is surrounded by the active region, and the P+-type implanted doping of the two PN junction diodes surrounds both sides of the first part of the polycrystalline gate.

[0007] Furthermore, the first part of the polycrystalline gate is of an H-shaped structure.

[0008] Furthermore, the P+-type implanted doping of the two PN junction diodes also surrounds partial positions at both ends of the first part of the polycrystalline gate.

[0009] Furthermore, a second part of the polycrystalline gate connected to the first part of the polycrystalline gate is also deposited at the positions of the second parasitic channel and the N-well capacitor.

[0010] Further, the second part of the polycrystalline gate is of an L-shaped structure.

[0011] Further, the NMOS transistor is electrically connected to the N-well capacitor through the first part of the polycrystalline gate and the second part of the polycrystalline gate in sequence.

[0012] Further, both ends of the NMOS transistor and the N-well capacitor are respectively connected to a metal wire through contact holes provided thereon to be electrically connected to an external device.

[0013] Further, the two PN junction diodes further include N+-type implant doping.

[0014] Further, an N-well is formed at the position of the N-well capacitor.

[0015] The beneficial effects achieved by the present invention: By surrounding the first part of the polycrystalline gate with the active region, the parasitic channel constructed by the field oxide is eliminated. Also, by surrounding both sides of the first part of the polycrystalline gate with the P+-type implant doping of the two PN junction diodes, the electrons caused by radiation are absorbed, the leakage path is prevented, and the leakage path between two adjacent NMOS transistors is isolated, thereby solving the problem of self-leakage of the NMOS transistor after radiation and the leakage problem between two adjacent NMOS transistors. Description of the Drawings

[0016] Figure 1 is a schematic plan view of an NVM memory cell provided by an embodiment of the present invention;

[0017] Figure 2 is a schematic cross-sectional view in the transverse direction of an NVM memory cell provided by an embodiment of the present invention;

[0018] Figure 3 is an electrical schematic diagram of an NVM memory cell provided by an embodiment of the present invention;

[0019] Figure 4 is a schematic diagram of the situation where leakage current occurs in a traditional memory cell.

[0020] Wherein, 1, P-type doped substrate; 2, NMOS transistor; 3, PN junction diode; 4, first parasitic channel; 5, second parasitic channel; 6, third parasitic channel; 7, active region; 8, first part of the polycrystalline gate; 9, P+-type implant doping; 10, second part of the polycrystalline gate; 11, contact hole; 12, metal wire; 13, N+-type implant doping; 14, N-well capacitor; 15, N-well; 16, total polycrystalline gate. Detailed Embodiments

[0021] In order to make the objectives, technical solutions and advantages of the present invention more clear and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0023] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intermediate element. In the following embodiments, "connection", if there is an electrical signal or data transfer between the connected circuits, modules, units, etc., should be understood as "electrical connection", "communication connection", etc.

[0024] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" or "having" etc. specify the presence of the stated features, wholes, steps, operations, components, parts or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof. At the same time, the terms used in this specification include any and all combinations of the related listed items.

[0025] An embodiment of the present invention provides a NVM storage cell, in combination with Figures 1 to 3 As shown, it includes a P-type doped substrate 1, an NMOS transistor 2, two PN junction diodes 3, and an N-well capacitor 14. The NMOS transistor 2, the two PN junction diodes 3, and the N-well capacitor 14 are all disposed on the P-type doped substrate 1.

[0026] Wherein, the two PN junction diodes 3 are respectively electrically connected to the source terminal and the drain terminal of the NMOS transistor 2, that is, the two PN junction diodes 3 are respectively located on the source terminal side and the drain terminal side of the NMOS transistor 2; on the sides of the two PN junction diodes 3 away from the NMOS transistor 2, a first parasitic channel 4 and a second parasitic channel 5 are respectively provided; the N-well capacitor 14 is disposed on the other side of the second parasitic channel 5. In addition, a third parasitic channel 6 is provided on the other side of the N-well capacitor 14.

[0027] The two PN junction diodes 3 are formed by implanting P+ type implant doping 9 in the active region 7 that is opposite to the doping of the first parasitic communication and the second parasitic channel. Correspondingly, N+ type implant doping 13 is also included.

[0028] Specifically, the NVM memory cell in this embodiment is fully compatible with the standard CMOS process and has extremely low cost.

[0029] In this embodiment, the positions of the two PN junction diodes 3 and the NMOS transistor 2 form an active region 7. A first part of a polycrystalline gate 8 is deposited in the active region 7. The first part of the polycrystalline gate 8 is surrounded by the active region 7. The P+ type implant doping 9 of the two PN junction diodes 3 surrounds both sides of the first part of the polycrystalline gate 8.

[0030] The beneficial effects achieved by this embodiment: By surrounding the first part of the polycrystalline gate 8 with the active region 7, the parasitic channels constructed by the field oxide are eliminated. Also, by surrounding both sides of the first part of the polycrystalline gate 8 with the P+ type implant doping 9 of the two PN junction diodes 3, the electrons caused by radiation are absorbed, the leakage path is prevented, and the leakage path between two adjacent NMOS transistors 2 is isolated, thereby solving the problem of self-leakage of the NMOS transistor 2 after radiation and the leakage problem between two adjacent NMOS transistors 2. At the same time, the NVM memory cell in this embodiment has extremely strong total dose effect resistance ability, and the total dose effect resistance ability exceeds 100 krad(Si).

[0031] In this embodiment, the first part of the polycrystalline gate 8 is of an H-shaped structure. By adopting the H-shaped structure, the width of the NMOS transistor 2 can be defined to avoid the increase in the width of the NMOS transistor 2 caused by the active region 7 surrounding the first part of the polycrystalline gate 8, that is, by adding redundant polycrystalline gate structures at the source and drain ends of the NMOS transistor 2 to limit the width of the NMOS transistor 2. Therefore, the degree of freedom of the size of the active region 7 is released, so that in the NVM memory cell structure, the active region 7 can be expanded to exceed the width of the NMOS transistor 2.

[0032] In this embodiment, the P+ type implant doping 9 of the two PN junction diodes 3 also surrounds partial positions at both ends of the first part of the polycrystalline gate 8. This can further absorb the electrons caused by radiation, prevent the leakage path, and isolate the leakage path between two adjacent NMOS transistors 2.

[0033] In this embodiment, a second part of a polycrystalline gate 10 connected to the first part of the polycrystalline gate 8 is also deposited at the positions of the second parasitic channel 5 and the N-well capacitor 14. The second part of the polycrystalline gate 10 and the first part of the polycrystalline gate 8 together form the total polycrystalline gate 16 of the NVM memory cell.

[0034] Among them, the second part of the polycrystalline gate 10 is of an L-shaped structure; the NMOS transistor 2 is electrically connected to the N-well capacitor 14 through the first part of the polycrystalline gate 8 and the second part of the polycrystalline gate 10 in sequence.

[0035] In this embodiment, an N-well 15 is formed at the position of the N-well capacitor 14.

[0036] Among them, the size of the N-well capacitor 14 is determined by the overlapping portions of the first part of the polycrystalline gate 8 and the second part of the polycrystalline gate 10 with the N-well 15 and the active region 7.

[0037] In this embodiment, both ends of the NMOS transistor 2 and the N-well capacitor 14 are respectively connected to the metal wire 12 through the contact holes 11 provided thereon for electrical connection to external devices.

[0038] Among them, one contact hole 11 is provided at each end of the NMOS transistor 2, and then each contact hole 11 is connected to a metal wire 12; correspondingly, one contact hole 11 is provided on the N-well capacitor 14, and then this connection hole is connected to a metal wire 12.

[0039] In this embodiment, the first part of the polycrystalline gate 8 of the NMOS transistor 2 and the second part of the polycrystalline gate 10 of the N-well capacitor 14 are connected together to form a floating gate for storing charges. The control transistor, tunneling transistor, and selection transistor of the NVM memory cell are integrated in one NMOS transistor 2, and at the same time, a selection transistor is not required for write crosstalk protection. The source and drain ends of the NMOS transistor 2 are respectively electrically connected to a PN junction diode 3 to limit the leakage current caused by irradiation. The difference between the NMOS transistor 2 in the NVM memory cell and the traditional one is that the enlarged active region 7 surrounds the first part of the polycrystalline gate 8, and the first part of the polycrystalline gate 8 is used to determine the width of the storage transistor. P+-type implant doping 9 is added on both sides of the NMOS transistor 2 to form a PN junction diode 3 to isolate the side parasitic MOS transistor. The NVM memory cell is programmed using hot electron injection and erased using band-to-band tunneling hot hole injection. Using these two methods for write operations can reduce the high voltage requirement and reduce its size. In addition, since the total dose effect of space radiation is related to the voltage bias, the higher the voltage, the more serious the total dose effect. Therefore, reducing the write high voltage effectively improves the total dose effect resistance of the memory cell.

[0040] In this embodiment, the voltages of each port during the read and write operations of the NVM memory cell are shown in Table 1 below:

[0041] Table 1. Voltages of Each Port

[0042] WL SL BL 0 0 HV HV VDD HV VREAD 0 VREAD

[0043] Among them, VREAD is the read voltage, VDD is the power supply voltage, and HV is the write high voltage.

[0044] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0045] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. An NVM memory cell, characterized in that, It includes a P-type doped substrate, an NMOS transistor, two PN junction diodes, and an N-well capacitor. The NMOS transistor, the two PN junction diodes, and the N-well capacitor are all disposed on the P-type doped substrate. The two PN junction diodes are respectively electrically connected to the source terminal and the drain terminal of the NMOS transistor. A first parasitic channel and a second parasitic channel are respectively provided on one side of the two PN junction diodes away from the NMOS transistor. The N-well capacitor is disposed on the other side of the second parasitic channel; Among them, the positions of the two PN junction diodes and the NMOS transistor form an active region. A first part of the polycrystalline gate is deposited in the active region. The first part of the polycrystalline gate is surrounded by the active region. The P+-type implantation doping of the two PN junction diodes surrounds both sides of the first part of the polycrystalline gate; A third parasitic channel is provided on the other side of the N-well capacitor; the first part of the polycrystalline gate is of an H-shaped structure.

2. The NVM storage cell according to claim 1, wherein The P+-type implantation doping of the two PN junction diodes also surrounds partial positions at both ends of the first part of the polycrystalline gate.

3. The NVM storage cell according to claim 1, characterized in that, A second part of the polycrystalline gate connected to the first part of the polycrystalline gate is also deposited at the position of the second parasitic channel and the N-well capacitor.

4. The NVM storage cell according to claim 3, wherein The second part of the polycrystalline gate is of an L-shaped structure.

5. The NVM storage cell according to claim 3, wherein The NMOS transistor is electrically connected to the N-well capacitor through the first part of the polycrystalline gate and the second part of the polycrystalline gate in sequence.

6. The NVM storage cell according to claim 1, wherein Both ends of the NMOS transistor and the N-well capacitor are respectively connected to metal wires through contact holes provided thereon to be electrically connected to external devices.

7. The NVM memory cell according to claim 1, wherein The two PN junction diodes further include N+-type implantation doping.

8. The NVM storage cell according to claim 1, wherein An N-well is formed at the position of the N-well capacitor.

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