A three-phase discrete frequency-locked loop implementation method and a three-phase discrete frequency-locked loop

Abstract

The present invention discloses a three-phase discrete frequency-locked loop implementation method and a three-phase discrete frequency-locked loop, the implementation method comprising: setting a frequency-locked loop FLL in a discrete reduced-order generalized integrator d-ROGI, wherein the open-loop transfer function of the discrete reduced-order generalized integrator d-ROGI is constructed according to the algebraic relationship of a complex signal, and the frequency-locked loop FLL is constructed by taking the frequency as an adaptive parameter of the transfer function according to the change law of a first parameter used to characterize the frequency change, thereby forming a final d-ROGI-FLL frequency-locked loop. The present invention has the advantages of simple implementation method, being able to take into account both the amount of calculation and the discrete precision, and not needing to call trigonometric functions.

Description

Technical Field

[0001] The present invention relates to the technical field of frequency locked loops, and in particular to a three-phase discrete frequency locked loop implementation method and a three-phase discrete frequency locked loop. Background Art

[0002] The grid-connected inverter is an important interface for renewable energy power generation systems to access the power grid. Real-time detection and parameter estimation of the grid voltage are key links for the grid-connected inverter to maintain synchronization with the grid and realize functions and performance such as voltage transient control, frequency inertia support and island detection. With the widespread application of distributed generation and nonlinear loads in the power grid, the waveform quality of the grid voltage is difficult to guarantee, and voltage quality problems such as frequency offset, harmonic pollution and three-phase voltage imbalance often occur. In this case, fast and accurate detection of the grid voltage is one of the great challenges facing the grid-connected inverter technology.

[0003] The parameter estimation methods of grid voltage can be roughly divided into frequency domain and time domain methods. The typical representative of frequency domain methods is discrete Fourier transform method, which has very high detection accuracy at rated frequency. However, since the frequency method processes the data of a window as a stable signal, its real-time performance is poor, which is not conducive to the real-time control of the grid-connected system. In addition, in the case of grid frequency offset, this method requires additional interpolation or adjustment of sampling frequency, so it is difficult to implement.

[0004] The time domain processing method is more suitable for real-time control systems. The three-phase frequency-locked loop based on the synchronous rotating coordinate system and the three-phase frequency-locked loop based on the stationary coordinate system are a type of widely used voltage parameter estimation. From the perspective of computational complexity, the frequency-locked loop has better advantages than the frequency-locked loop due to the inherent stationary coordinate system modeling. However, at low sampling frequencies, the reduced-order generalized integrator that the frequency-locked loop relies on cannot guarantee good accuracy, and because the reduced-order generalized integrator needs to track AC signals instead of DC signals, the forward difference method commonly used for discretization of the frequency-locked loop integrator has very poor accuracy.

[0005] In order to improve the accuracy of the frequency-locked loop at low sampling frequencies, a third-order digital integrator method is proposed. This method has a clear correspondence in the continuous domain and does not introduce the problem of algebraic loops when discretizing the open-loop function. However, at low sampling frequencies, especially for high-frequency AC signals of aircraft power grid systems, this method still cannot ensure appropriate detection accuracy.

[0006] Some practitioners have proposed to realize high-precision frequency-locked loop based on discrete resonators, but the realization is complicated and involves observer theory. At the same time, there is a lack of accurate linearization model, so the optimal setting is difficult to ensure. In addition, the frequency-locked loop also needs to call trigonometric functions online, which consumes a lot of computing resources. Some practitioners have also proposed a three-phase frequency-locked loop based on linear Kalman filtering. This method has certain benefits when the frequency fluctuates over a wide range by implanting variable gain control, but the discrete realization in the frequency-locked loop is still complicated, and trigonometric functions cannot be avoided. Summary of the invention

[0007] The technical problem to be solved by the present invention is: in response to the technical problems existing in the prior art, the present invention provides a three-phase discrete frequency locked loop implementation method and a three-phase discrete frequency locked loop which have a simple implementation method, can take into account both the amount of calculation and the discrete accuracy, and do not require the use of trigonometric functions.

[0008] In order to solve the above technical problems, the technical solution proposed by the present invention is:

[0009] A three-phase discrete frequency-locked loop implementation method comprises: setting a frequency-locked loop FLL in a discrete reduced-order generalized integrator d-ROGI, wherein the open-loop transfer function of the discrete reduced-order generalized integrator d-ROGI is constructed according to the algebraic relationship of the complex signal, and the frequency-locked loop FLL uses the frequency as an adaptive parameter of the transfer function, according to the method for characterizing sin(ω rogi T s )The variation law of the first parameter q of the frequency variation is constructed to form the final d-ROGI-FLL frequency locked loop.

[0010] Furthermore, the discrete reduced-order generalized integrator d-ROGI in the d-ROGI-FLL frequency-locked loop includes a first adder, a first amplifier, a second adder, a delay device, and a first multiplier connected in sequence, wherein the output end of the first multiplier is connected to an input end of the first adder, and the first adder is respectively connected to the input quantity v and the estimated quantity of the output of the first multiplier The gain of the first amplifier is λ z , the multiplication coefficient of the first multiplier is is the estimated value of τ and τ=tan(ωT s ).

[0011] Furthermore, the first multiplier is implemented using a digital module.

[0012] Further, the frequency locked loop in the d-ROGI-FLL frequency locked loop includes a second multiplier, a second amplifier, a first calculation unit, a second calculation unit and a third multiplier connected in sequence, the input end of the second multiplier is respectively connected to the output end of the first adder and the output end of the first multiplier, the output end of the second multiplier is connected to the input end of the second amplifier, and the gain of the second amplifier is μ z The first calculation unit is used to calculate tan(ωT s )get τ and calculate the output estimate The second calculation unit is used to calculate To calculate the output c Estimated value of c To characterize cos(ω rogi T s ) a second parameter of frequency change, an input end of the third multiplier is respectively connected to an output end of the second calculation unit and an output end of the first multiplier, and an output end of the third multiplier is connected to an input end of the second adder.

[0013] Furthermore, the expression of the discrete reduced-order generalized integrator d-ROGI in the d-ROGI-FLL frequency-locked loop is:

[0014]

[0015] Among them, v(z) is the input quantity.

[0016] Furthermore, the method further includes the step of constructing a linearization model for the d-ROGI-FLL frequency locked loop, including:

[0017] Define the trajectory of the output signal:

[0018]

[0019] And the difference equation of the frequency-locked loop:

[0020]

[0021] A linearized frequency differential equation is constructed according to the trajectory of the output signal and the differential equation of the frequency locked loop:

[0022]

[0023] The frequency difference equation is converted into differential form and linearized as:

[0024]

[0025] Obtain the linearized relationship between phase and frequency;

[0026] Building Phase Dynamics:

[0027]

[0028] And the frequency dynamics:

[0029]

[0030] According to the phase dynamics and frequency dynamics, a second-order linear model with single input and output is constructed:

[0031]

[0032] The symbol ^ represents the estimated parameter, v represents the input quantity, λ is the control gain of d-ROGI, T s =f / f s is a sampling interval, V is the amplitude, ΔV is the amplitude change, φ is the instantaneous phase, Dφ is the phase change, is the first-order derivative of the estimated value of the angular frequency change, μ z is the gain of the frequency locked loop FLL, and ω is the angular frequency.

[0033] Furthermore, it also includes constructing a phase linearization model for the d-ROGI-FLL frequency locked loop:

[0034]

[0035] A three-phase discrete frequency-locked loop, comprising a discrete reduced-order generalized integrator d-ROGI and a frequency-locked loop FLL connected to each other, wherein the open-loop transfer function of the discrete reduced-order generalized integrator d-ROGI is constructed according to the algebraic relationship of the complex signal, and the frequency-locked loop FLL is constructed according to the algebraic relationship used to characterize sin(ω rogi T s )The variation law of the first parameter q of the frequency variation is constructed.

[0036] Furthermore, the discrete reduced-order generalized integrator d-ROGI in the d-ROGI-FLL frequency-locked loop includes a first adder, a first amplifier, a second adder, a delay device, and a first multiplier connected in sequence, wherein the output end of the first multiplier is connected to an input end of the first adder, and the first adder is respectively connected to the input quantity v and the estimated quantity of the output of the first multiplier The gain of the first amplifier is λ z , the multiplication coefficient of the first multiplier is is the estimated value of τ and τ=tan(ωT s ).

[0037] Further, the frequency locked loop in the d-ROGI-FLL frequency locked loop includes a second multiplier, a second amplifier, a first calculation unit, a second calculation unit and a third multiplier connected in sequence, the input end of the second multiplier is respectively connected to the output end of the first adder and the output end of the first multiplier, the output end of the second multiplier is connected to the input end of the second amplifier, and the gain of the second amplifier is μ z The first calculation unit is used to calculate tan(ωT s )get τ and calculate the output estimate The second calculation unit is used to calculate To calculate the output c Estimated value of c To characterize cos(ω rogi T s ) a second parameter of frequency change, an input end of the third multiplier is respectively connected to an output end of the second calculation unit and an output end of the first multiplier, and an output end of the third multiplier is connected to an input end of the second adder.

[0038] Compared with the prior art, the advantages of the present invention are as follows: the present invention realizes a three-phase discrete frequency locked loop by combining a discrete reduced-order generalized integrator with a frequency locked loop, constructs an open-loop transfer function of the discrete reduced-order generalized integrator according to the algebraic relationship of the complex signal to avoid the algebraic loop problem, and constructs the frequency locked loop according to the tracking error of the filter and the variation law of the unknown parameters, so that the frequency locked loop does not directly estimate the frequency, but estimates the unknown parameters reflecting the frequency change, and can realize a high-precision discrete frequency locked loop, which not only has a simple structure and high discrete accuracy, but also does not need to call trigonometric functions online. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 Schematic diagram of the structure of a three-phase discrete frequency-locked loop implemented in this embodiment.

[0040] Figure 2 This is a schematic diagram of the structural principle of ROGI.

[0041] Figure 3 Schematic diagram of the initial d-ROGI structure constructed in this example.

[0042] Figure 4 Schematic diagram of the structural principle of the d-ROGI constructed in this embodiment.

[0043] Figure 5 It is the Bode diagram obtained by d-ROGI in a specific application example.

[0044] Figure 6Schematic diagram of the digital implementation structure of d-ROGI-FLL in this embodiment. DETAILED DESCRIPTION

[0045] The present invention is further described below in conjunction with the accompanying drawings and specific preferred embodiments, but the protection scope of the present invention is not limited thereby.

[0046] The implementation method of the three-phase discrete frequency-locked loop in this embodiment includes: setting a frequency-locked loop FLL in a discrete reduced-order generalized integrator d-ROGI, wherein the open-loop transfer function of the discrete reduced-order generalized integrator d-ROGI is constructed according to the algebraic relationship of the complex signal, and the frequency-locked loop FLL uses the frequency as an adaptive parameter of the transfer function, according to the parameter used to characterize sin(ω rogi T s ) The variation law of the first parameter q of the frequency variation is constructed to form the final d-ROGI-FLL frequency-locked loop. The obtained d-ROGI-FLL frequency-locked loop is as follows Figure 1 shown.

[0047] This embodiment first analyzes the principle of ROGI (Reduced-order generalized integrator):

[0048] The two-phase orthogonal signal in the stationary coordinate system is defined as:

[0049]

[0050] Where: V is the amplitude, φ(t) is the instantaneous phase, ω(t) is the angular frequency, The initial phase.

[0051] Due to the uncertainty of the actual grid voltage, harmonics, noise, unbalanced components, etc. may exist in the input signal. This embodiment uses a complex coefficient resonator, that is, a reduced-order generalized integrator ROGI, such as Figure 2 As shown, the expression is:

[0052]

[0053] Where: the symbol ^ represents the estimated parameter, ω rogi is the center frequency of the corresponding ROGI, j is the complex variable operator, l>0 is the control gain of ROGI, and v(s) is the input quantity.

[0054] The closed-loop transfer function corresponding to ROGI is as follows:

[0055]

[0056] From equation (3), it can be seen that ROGI is essentially a first-order complex coefficient bandpass filter, which satisfies unity gain and zero phase lag at the center frequency.

[0057] Then analyze the principle of ROGI frequency-locked loop:

[0058] Since the actual grid frequency has certain fluctuations, especially in weak grid conditions, the frequency is allowed to deviate within the range of 47-52 Hz. In order to realize the above-mentioned ROGI adaptive frequency characteristics, this embodiment introduces a frequency-locked loop (FLL) to obtain real-time frequency information. The ROGI frequency locked loop FLL is formed, and the expression of the ROGI frequency locked loop FLL is as follows:

[0059]

[0060] Where: μ>0 is the gain of FLL.

[0061] The above ROGI frequency-locked loop FLL can be derived specifically according to the following process:

[0062] First, define the output signal trajectory to satisfy:

[0063]

[0064] According to the definition of error e, it can be deduced that:

[0065]

[0066] Then consider the slowly varying or steady-state frequency |ω(t+T s )-ω(t)|≤ε, where ε>0 is a small positive value, T s =f / f s is a sampling interval, the error locally satisfies:

[0067]

[0068] When If e<0, then the frequency-locked loop should be reduced in the next iteration in principle, then:

[0069]

[0070] Then the above frequency locked loop FLL is obtained.

[0071] Since most real-time control systems are implemented in digital signal processors (DSPs), the above continuous domain modeling ROGI-FLL cannot be directly implemented and needs to be discretized. The key to discretization is the integrator. The structure of d-ROGI is as follows: Figure 2 As shown in Figure 2, ROGI requires tracking of AC signals, so the traditional forward difference method 1 / s→z -1 / (1-z -1 ) cannot achieve steady-state error-free tracking. In order to improve the discretization accuracy, the third-order numerical integrator method is used: (z -1 The ideal AC signal integration capability cannot be achieved by using an observer or a Kalman filter (i.e., a Riccati observer) to obtain a high-precision discrete resonator. Not only is the derivation and implementation process complicated, but also the trigonometric functions sin() and cos() need to be called online.

[0072] This embodiment constructs a high-precision discrete reduced-order generalized integrator based on the continuous domain ROGI, so as to improve the discrete accuracy and reduce the implementation complexity, and there is no need to call the trigonometric functions sin() and cos() online. The detailed process of constructing the discrete reduced-order generalized integrator ROGI transfer function is:

[0073] First, for the discrete system, the complex signal in the stationary coordinate system is defined as:

[0074]

[0075] Among them, k is the current iteration point, and the physical meanings of other variables are consistent with those in the continuous domain.

[0076] Considering that continuous domain ROGI essentially needs to realize a first-order complex coefficient transfer function with infinite gain at the input signal frequency, the following discrete signal algebraic relationship exists:

[0077]

[0078] Analogously to the relationship satisfied in the continuous domain:

[0079]

[0080] And the ROGI in the continuous domain is:

[0081]

[0082] Then the frequency domain equivalent in the discrete domain can be obtained as follows:

[0083]

[0084] At this point, the following discrete ROGI transfer function can be obtained:

[0085]

[0086] Among them, λ1 is analogous to the gain λ in the continuous domain.

[0087] After the above steps, we can construct Figure 3 The initial d-ROGI structure shown in FIG. 1 includes an adder 1 (input side adder), an amplifier, an adder 2 (an adder connected to the output of the amplifier), a multiplier, and a delay device connected in sequence. The output of the delay device is also connected to the input of the adder 2. The adder 1 receives the input quantity v and the estimated quantity of the output of the adder 2. The gain of the amplifier is λ1, and the multipliers are connected to the estimated output of adder 2 as well as where ω rogi is the center frequency of the corresponding ROGI, j is a complex variable operator, T s =f / f s is a sampling interval.

[0088] The above initial d-ROGI structure cannot be directly implemented in an embedded processor because the current output is used as a feedback variable, i.e., an algebraic loop problem. In order to eliminate the above algebraic loop problem, this embodiment makes the feedback variable no longer the current output, but the output that lags behind by one beat, and obtains a more direct relationship as follows:

[0089]

[0090] Then the initial d-ROGI structure can be converted to:

[0091]

[0092] The d-ROGI structure used in this embodiment is constructed, such as Figure 4 As shown, the d-ROGI structure includes an adder 1 (input side adder), an amplifier, an adder 2 (an adder connected to the output of the amplifier), a delay device, and a multiplier connected in sequence. The output of the multiplier is also connected to the input of adder 1 and adder 2 respectively. Adder 1 is connected to the input quantity v and the estimated quantity of the output of adder 2 respectively. The gain of the amplifier is λ2, and the multiplier is connected to the output of the delay device and Output estimator Provided to adder 1 and adder 2.

[0093] In a specific application embodiment, the above discrete closed-loop transfer function has a sampling frequency of 2 kHz and a center frequency of ω rogi =100π and gain λ r = 0.02, the Bode plot is as follows Figure 5 As shown, it can be seen that even at very low sampling frequencies, the transfer function can still achieve a bandpass effect with unity gain and zero phase lag.

[0094] This embodiment further constructs a frequency locked loop:

[0095] Since the frequency of the input signal is unknown, FLL needs to be introduced to achieve the purpose of adaptive frequency. Note that the transfer function contains two parameters that reflect frequency changes:

[0096]

[0097] That is, the parameter c is the characteristic of cos(ω rogi T s ) frequency change parameter, q is the parameter that characterizes sin(ω rogi T s ) parameter of frequency change.

[0098] If the traditional FLL construction method is still used, it is inevitable to call trigonometric functions online to obtain the parameters c and q in real time.

[0099] To avoid calling trigonometric functions, this embodiment performs the following function equivalence:

[0100]

[0101] That is, the goal of frequency detection is not concerned, but the frequency is only used as an adaptive parameter of a transfer function to avoid calling trigonometric functions.

[0102] Furthermore, since the parameter q has the following relationship:

[0103]

[0104] Where:

[0105] That is, the change law of parameter q is consistent with the change of frequency ω. Therefore, according to the construction principle of traditional three-phase FLL, the following frequency-locked loop can be obtained:

[0106]

[0107] At this point, the parameter q can be accurately estimated. However, c needs to be further obtained. Since c and p satisfy the definite relationship:

[0108]

[0109] Therefore, the estimated parameter c can be obtained from the estimated parameter q. Considering that the square root operation is also very expensive in processors such as DSP, and the square root reciprocal operation is faster (through testing, its calculation cycle is 20% faster than the square root), this embodiment specifically adopts the discrete ROGI converted by the following formula:

[0110]

[0111] Among them, the parameter τ and the parameter q and their frequency ω all have consistent local variation rules. Then the frequency-locked loop structure of this embodiment is:

[0112]

[0113] like Figure 1 As shown, the discrete reduced-order generalized integrator d-ROGI in the d-ROGI-FLL frequency-locked loop specifically includes a first adder, a first amplifier, a second adder, a delay device, and a first multiplier connected in sequence, the output end of the first multiplier is connected to an input end of the first adder, and the first adder is respectively connected to the input quantity v and the estimated quantity of the output of the first multiplier The gain of the first amplifier is λ z , the multiplication coefficient of the first multiplier is is the estimated value of τ and τ=tan(ωT s The phase-locked loop in the d-ROGI-FLL frequency-locked loop specifically includes a second multiplier, a second amplifier, a first calculation unit, a second calculation unit, and a third multiplier connected in sequence. The input end of the second multiplier is respectively connected to the output end of the first adder and the output end of the first multiplier. The output end of the second multiplier is connected to the input end of the second amplifier. The gain of the second amplifier is μ z , the first calculation unit is used to calculate tan(ωT s )get τ and calculate the output estimate The second computing unit is used to calculate To calculate the estimated value of the output c c is used to characterize cos(ω rogi T s ) The second parameter of the frequency change, the input end of the third multiplier is respectively connected to the output end of the second calculation unit and the output end of the first multiplier, and the output end of the third multiplier is connected to an input end of the second adder. The transfer function of the discrete reduced-order generalized integrator d-ROGI is shown in the above formula (22).

[0114] Considering Figure 1 The complex variable module is not conducive to digital implementation. Figure 1 The structure in the figure is converted into an easy-to-understand real variable module structure. The detailed process is as follows:

[0115] The signal vector in the two-phase stationary coordinate system is defined as:

[0116]

[0117] In order to convert the complex signal of the discrete transfer function into a signal vector, the error signals are defined as:

[0118]

[0119] Then, the following time domain operation is obtained based on the discrete ROGI transfer function expression:

[0120]

[0121] If the above algebraic polynomial is regarded as a complex operator Γ, then through algebraic processing we can get the following concise form:

[0122]

[0123] In order to make the complex operator always equal to 0, the real part and the imaginary part must be 0. Then the following vector relationship is derived:

[0124]

[0125] This vector relationship is very concise and easy to implement numerically, where the common factors can be converted to:

[0126]

[0127] Since the frequency-locked loop is already a completely discrete structure, the linearization model of the traditional ROGI-FLL in the continuous domain cannot be used directly. This embodiment further constructs a more accurate second-order system than the traditional solution, and the digital implementation module of the constructed d-ROGI-FLL is as follows Figure 6 As shown, this embodiment also includes the step of constructing a linearization model for the d-ROGI-FLL frequency locked loop, including:

[0128] First, define the trajectory of the output signal to satisfy:

[0129]

[0130] Then the differential equation of the frequency-locked loop satisfies:

[0131]

[0132] Because frequency and phase are inherently coupled, the nonlinear function tan() in the above equation is removed during linearization. Since the following relationship exists:

[0133]

[0134] In order to achieve linearization, the small signal is set to satisfy:

[0135]

[0136] Then we get the following approximate relationship:

[0137]

[0138] as well as

[0139]

[0140] Therefore, the linearized frequency difference equation is:

[0141]

[0142] Considering that the frequency is a slow-varying or steady-state signal, the above equation can be converted into a differential form:

[0143]

[0144] Furthermore, the amplitude and phase small signals are defined to satisfy:

[0145]

[0146] Then the above differential equation can be further linearized as:

[0147]

[0148] At this point, we have obtained a linear relationship between phase and frequency. Further, we need to obtain another relationship to transform them into a single-input single-output model.

[0149] Since the dynamics of d-ROGI has not been considered, the parameter λ z It is still uncertain. This embodiment further analyzes the dynamics of d-ROGI. Since the d-ROGI in the discrete domain and the ROGI in the continuous domain are similar in terms of dynamics, the derivation in the continuous domain is more concise. Therefore, it is necessary to determine the equivalent ROGI in the continuous domain:

[0150] The equivalent relationship is obtained from the amplitude-frequency response, and considering their same attenuation ability for DC signals, the following is satisfied:

[0151]

[0152] Then we get the following gain relationship:

[0153]

[0154] The above relationship means that given a gain λ z , then there is a unique corresponding ROGI in the continuous domain, that is, the gain λ is established z Relationship with ROGI in the continuous domain. At this time, since the phase dynamics satisfies:

[0155]

[0156] Considering that the error satisfies The phase dynamics are thus:

[0157]

[0158] Differentiating the frequency dynamics again satisfies:

[0159]

[0160] Substituting the phase dynamics, the second-order linear model with single input and output can be obtained as:

[0161]

[0162] Using the inverse Laplace transform we get:

[0163]

[0164] In the same way, the linearized model of the phase can be derived as:

[0165]

[0166] Therefore, its parameters can be adjusted according to the second-order system, and the optimal damping ratio is adjusted as follows:

[0167]

[0168] This embodiment also provides a three-phase discrete phase-locked loop, such as Figure 1 As shown, the three-phase discrete phase-locked loop includes a discrete reduced-order generalized integrator d-ROGI and a phase-locked loop FLL connected to each other. The open-loop transfer function of the discrete reduced-order generalized integrator d-ROGI is constructed according to the algebraic relationship of the complex signal, and the phase-locked loop FLL is constructed according to the algebraic relationship used to characterize sin(ω rogi T s )The variation law of the first parameter q of the frequency variation is constructed.

[0169] like Figure 1As shown, the discrete reduced-order generalized integrator d-ROGI in the d-ROGI-FLL frequency-locked loop comprises a first adder, a first amplifier, a second adder, a delay device and a first multiplier connected in sequence, the output end of the first multiplier is connected to an input end of the first adder, and the first adder is respectively connected to the input quantity v and the estimated quantity of the output of the first multiplier The gain of the first amplifier is λ z , the multiplication coefficient of the first multiplier is is the estimated value of τ and τ=tan(ωT s ).

[0170] like Figure 1 As shown, the phase-locked loop in the d-ROGI-FLL frequency-locked loop includes a second multiplier, a second amplifier, a first calculation unit, a second calculation unit and a third multiplier connected in sequence, the input end of the second multiplier is respectively connected to the output end of the first adder and the output end of the first multiplier, the output end of the second multiplier is connected to the input end of the second amplifier, and the gain of the second amplifier is μ z , the first calculation unit is used to calculate tan(ωT s ) to obtain τ and calculate the output estimate The second computing unit is used to calculate To calculate the estimated value of the output c c is used to characterize cos(ω rogi T s ) a second parameter of frequency change, an input end of the third multiplier is respectively connected to the output end of the second calculation unit and the output end of the first multiplier, and an output end of the third multiplier is connected to an input end of the second adder.

[0171] The above-mentioned discrete frequency-locked loop for the three-phase system of the present invention is realized by combining a discrete reduced-order generalized integrator with a frequency-locked loop. The open-loop transfer function of the discrete reduced-order generalized integrator is constructed according to the algebraic relationship of the complex signal to avoid the algebraic loop problem. At the same time, the frequency-locked loop is constructed according to the tracking error of the filter and the variation law of the parameter (q), so that the frequency-locked loop does not directly estimate the frequency, but estimates the unknown parameters reflecting the frequency variation. A high-precision discrete frequency-locked loop can be realized, which is not only simple in structure and high in discrete precision, but also does not require online calling of trigonometric functions. The simulation results at low sampling frequencies verify that the discrete frequency-locked loop of the present invention has higher detection accuracy than the traditional third-order digital integrator discretization method. The discrete frequency-locked loop of the present invention can also improve the calculation amount of the three-phase discrete frequency-locked loop by one-third.

[0172] The above is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A three-phase discrete frequency-locked loop implementation method, characterized in that: include: A frequency locked loop FLL is set in a discrete reduced-order generalized integrator d-ROGI, wherein an open-loop transfer function of the discrete reduced-order generalized integrator d-ROGI is constructed according to an algebraic relationship of a complex signal, and the frequency locked loop FLL uses the frequency as an adaptive parameter of the transfer function, according to the method used to characterize sin(ω rogi T s ) The variation law of the first parameter q of the frequency variation is constructed to form the final d-ROGI-FLL frequency locked loop; The discrete reduced-order generalized integrator d-ROGI in the d-ROGI-FLL frequency-locked loop comprises a first adder, a first amplifier, a second adder, a delay device and a first multiplier connected in sequence, wherein the output end of the first multiplier is connected to an input end of the first adder, and the first adder is respectively connected to an input quantity v and an estimated quantity of the output of the first multiplier The gain of the first amplifier is λ z , the multiplication coefficient of the first multiplier is is the estimated value of τ and τ=tan(ωT s ); the d-ROGI-FLL frequency locked loop includes a second multiplier, a second amplifier, a first calculation unit, a second calculation unit and a third multiplier connected in sequence, the input end of the second multiplier is respectively connected to the output end of the first adder and the output end of the first multiplier, the output end of the second multiplier is connected to the input end of the second amplifier, and the gain of the second amplifier is μ z The first calculation unit is used to calculate tan(ωT s ) to obtain τ and calculate the output estimate The second calculation unit is used to calculate To calculate the estimated value of the output c c is used to characterize cos(ω rogi T s ) a second parameter of frequency change, an input end of the third multiplier is respectively connected to an output end of the second calculation unit and an output end of the first multiplier, and an output end of the third multiplier is connected to an input end of the second adder.

2. The method for implementing a three-phase discrete frequency locked loop according to claim 1, characterized in that: The first multiplier is implemented using a digitization module.

3. The method for implementing a three-phase discrete frequency locked loop according to claim 1, characterized in that: The expression of the discrete reduced-order generalized integrator d-ROGI in the d-ROGI-FLL frequency-locked loop is: Among them, v(z) is the input quantity.

4. The method for implementing a three-phase discrete frequency locked loop according to any one of claims 1 to 3, characterized in that: The method also includes the step of constructing a linearization model for the d-ROGI-FLL frequency-locked loop, including: Define the trajectory of the output signal: And the difference equation of the frequency-locked loop: A linearized frequency differential equation is constructed according to the trajectory of the output signal and the differential equation of the frequency locked loop: The frequency difference equation is converted into differential form and linearized as: Obtain the linearized relationship between phase and frequency; Building Phase Dynamics: And the frequency dynamics: According to the phase dynamics and frequency dynamics, a second-order linear model with single input and output is constructed: Where, the symbol ^ represents the estimated parameter, v represents the input, λ is the control gain of d-ROGI, T s =f / f s is a sampling interval, V is the amplitude, ΔV is the amplitude change, φ is the instantaneous phase, Δφ is the phase change, is the first-order derivative of the estimated value of the angular frequency change, μ z is the gain of the frequency locked loop FLL, and ω is the angular frequency.

5. The method for implementing a three-phase discrete frequency locked loop according to claim 4, characterized in that: It also includes building a phase linearization model for the d-ROGI-FLL frequency-locked loop:

6. A three-phase discrete frequency locked loop, characterized in that: The invention comprises a discrete reduced-order generalized integrator d-ROGI and a frequency-locked loop FLL connected to each other, wherein the open-loop transfer function of the discrete reduced-order generalized integrator d-ROGI is constructed according to the algebraic relationship of the complex signal, and the frequency-locked loop FLL is constructed according to the algebraic relationship used to characterize sin(ω rogi T s ) The discrete reduced-order generalized integrator d-ROGI comprises a first adder, a first amplifier, a second adder, a delay device and a first multiplier connected in sequence, the output end of the first multiplier is connected to an input end of the first adder, and the first adder is respectively connected to the input quantity v and the estimated quantity of the output of the first multiplier The gain of the first amplifier is λ z , the multiplication coefficient of the first multiplier is is the estimated value of τ and τ=tan(ωT s ); the frequency locked loop FLL comprises a second multiplier, a second amplifier, a first calculation unit, a second calculation unit and a third multiplier connected in sequence, the input end of the second multiplier is respectively connected to the output end of the first adder and the output end of the first multiplier, the output end of the second multiplier is connected to the input end of the second amplifier, and the gain of the second amplifier is μ z The first calculation unit is used to calculate tan(ωT s ) to obtain τ and calculate the output estimate The second calculation unit is used to calculate To calculate the estimated value of the output c c is used to characterize cos(ω rogi T s ) a second parameter of frequency change, an input end of the third multiplier is respectively connected to an output end of the second calculation unit and an output end of the first multiplier, and an output end of the third multiplier is connected to an input end of the second adder.

Images