A power amplifier applied to 5G frequency band

Abstract

The application discloses a power amplifier applied to a 5G frequency band, which comprises an adjustable gain driving stage circuit, an interstage matching circuit and an adjustable gain amplification stage circuit. The adjustable gain driving stage circuit amplifies a first radio frequency signal to obtain a second radio frequency signal, and provides the second radio frequency signal to the interstage matching circuit. The interstage matching circuit resonates at a working frequency point corresponding to a channel frequency of the second radio frequency signal, so as to improve the gain of the second radio frequency signal, and provides the second radio frequency signal to the adjustable gain amplification stage circuit. The adjustable gain amplification stage circuit amplifies the second radio frequency signal to obtain a third radio frequency signal, and provides the third radio frequency signal to an antenna. The application can perform power synthesis through two paths and two stages of power amplifiers, can improve the gain of the power amplifier, and can be beneficial to improving the stability of the radio frequency signal during power synthesis.

Description

Technical Field

[0001] This invention relates to the field of electronic communication technology, and in particular to a power amplifier for use in the 5G band. Background Technology

[0002] In real life, 5G Wi-Fi has gradually entered people's lives. 5G Wi-Fi uses Wi-Fi chips that operate in the 5G frequency band. The 5G frequency band is currently used less in China, which greatly reduces radio interference and results in better signal quality.

[0003] The biggest limiting factor for 5G Wi-Fi is its poor wall-penetrating ability due to its high frequency, with signal attenuation increasing with distance. Current solutions address this by increasing transmission power to extend propagation distance, making high-gain RF transmitters crucial. Power amplifiers are a vital component of RF transmitters and a key module for providing gain. In 5G bands, the increased frequency necessitates smaller parasitic capacitances and inductances to ensure resonance at the 5G frequency. However, smaller capacitances mean smaller transistors for amplification, and smaller inductors make it difficult to achieve a high Q value, both contributing to low gain in the first stage of the power amplifier. Therefore, providing a power amplifier that improves gain in the 5G band is of paramount importance. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a power amplifier for use in the 5G band, which adopts a multi-layer structure design, effectively improves the efficiency of the power amplifier in the 5G band, can improve the gain of the power amplifier, and can help improve the stability of the radio frequency signal during power combining.

[0005] To address the aforementioned technical problems, the first aspect of this invention discloses a power amplifier applied to the 5G frequency band, the power amplifier comprising:

[0006] Adjustable gain driver stage circuit, inter-stage matching circuit, and adjustable gain amplifier stage circuit;

[0007] The adjustable gain drive stage circuit has an input terminal for inputting a first radio frequency signal, an output terminal for electrically connecting to the input terminal of the inter-stage matching circuit, an output terminal for electrically connecting to the input terminal of the adjustable gain amplifier stage circuit, and an output terminal for electrically connecting to the antenna.

[0008] The adjustable gain drive stage circuit amplifies the first radio frequency signal to obtain a second radio frequency signal, and provides the second radio frequency signal to the inter-stage matching circuit. The inter-stage matching circuit resonates at the operating frequency point corresponding to the channel frequency of the second radio frequency signal to improve the gain of the second radio frequency signal, and provides the second radio frequency signal to the adjustable gain amplifier stage circuit. The adjustable gain amplifier stage circuit amplifies the second radio frequency signal to obtain a third radio frequency signal, and provides the third radio frequency signal to the antenna.

[0009] As an optional implementation, in the first aspect of the present invention, the power amplifier further includes at least one of an input matching circuit, an output matching circuit, and a bias circuit;

[0010] The input terminal of the input matching circuit is used to input the first radio frequency signal, and the output terminal of the input matching circuit is electrically connected to the input terminal of the adjustable gain drive stage circuit; the input matching circuit inputs the first radio frequency signal to the adjustable gain drive stage circuit without reflection.

[0011] The output terminal of the adjustable gain amplifier stage circuit is electrically connected to the input terminal of the output matching circuit, and the output terminal of the output matching circuit is used to electrically connect to the antenna; the output matching circuit provides the third radio frequency signal output by the adjustable gain amplifier stage circuit to the antenna.

[0012] The first output terminal of the bias circuit is electrically connected to the first bias circuit connection terminal of the adjustable gain drive stage circuit, and the second output terminal of the bias circuit is electrically connected to the second bias circuit connection terminal of the adjustable gain amplifier stage circuit; the third output terminal of the bias circuit is electrically connected to the third bias circuit connection terminal of the interstage matching circuit; the bias circuit provides corresponding bias voltages to the adjustable gain drive stage circuit, the adjustable gain amplifier stage circuit, and the interstage matching circuit.

[0013] As an optional implementation, in the first aspect of the present invention, the adjustable gain drive stage circuit includes two structurally identical adjustable gain drive stage sub-circuits, the inter-stage matching circuit includes two structurally identical inter-stage matching sub-circuits, and the adjustable gain amplification stage circuit includes two structurally identical adjustable gain amplification stage sub-circuits.

[0014] As an optional implementation, in a first aspect of the present invention, the adjustable gain drive stage sub-circuit includes a first capacitor, a second capacitor, a first resistor, a second resistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor.

[0015] Wherein, the first terminal of the first capacitor is electrically connected to the first output terminal of the input matching circuit, the second terminal of the first capacitor is electrically connected to the first terminal of the first resistor and the gate of the first NMOS transistor, the source of the first NMOS transistor is electrically connected to the source of the second NMOS transistor and is used for grounding, and the drain of the first NMOS transistor is electrically connected to the source of the third NMOS transistor.

[0016] The drain of the second NMOS transistor is electrically connected to the source of the fourth NMOS transistor. The gate of the second NMOS transistor is electrically connected to the first end of the second resistor and the first end of the second capacitor, respectively. The second end of the second capacitor is electrically connected to the second output end of the input matching circuit. The second end of the second resistor and the second end of the first resistor are electrically connected to the first sub-output end included in the first output end of the bias circuit.

[0017] The gates of the third NMOS transistor and the fourth NMOS transistor are electrically connected to the second sub-output terminal included in the first output terminal of the bias circuit, and the drains of the third NMOS transistor and the fourth NMOS transistor are electrically connected to the input terminal of the same interstage matching sub-circuit.

[0018] As an optional implementation, in the first aspect of the present invention, the adjustable gain drive stage sub-circuit further includes at least one first gain amplification adjustment sub-circuit, the first terminal of each first gain amplification adjustment sub-circuit being electrically connected to a corresponding third sub-output terminal included in the first output terminal of the bias circuit; the second terminal of each first gain amplification adjustment sub-circuit being electrically connected to the second terminal of the second resistor and the second terminal of the first resistor, respectively; the third terminal of each first gain amplification adjustment sub-circuit being grounded.

[0019] When the first terminal of a certain first gain amplification adjustment sub-circuit is in a conducting state with the second terminal of the first gain amplification adjustment sub-circuit, the first terminal of the first gain amplification adjustment sub-circuit and the third terminal of the first gain amplification adjustment sub-circuit are in a non-conducting state. The first gain amplification adjustment sub-circuit is used to adjust the gain amplification factor of the first radio frequency signal by the adjustable gain drive stage circuit.

[0020] As an optional implementation, in the first aspect of the present invention, the interstage matching sub-circuit includes a third resistor, a third capacitor, and a first balun, wherein the third resistor and the third capacitor are connected in parallel;

[0021] Wherein, the first end of the third resistor and the third capacitor connected in parallel is electrically connected to the drain of the third NMOS transistor and the first end of the main coil of the first balun; the second end of the third resistor and the third capacitor connected in parallel is electrically connected to the drain of the fourth NMOS transistor and the second end of the main coil of the first balun; the first end and the second end of the secondary coil of the first balun are electrically connected to the two input ends of the same adjustable gain amplifier stage sub-circuit.

[0022] The third terminal of the secondary coil of the first balun is electrically connected to the third output terminal of the bias circuit.

[0023] As an optional implementation, in the first aspect of the present invention, the adjustable gain amplifier stage sub-circuit includes a fourth capacitor, a fifth capacitor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor.

[0024] Wherein, the first terminal of the fourth capacitor is electrically connected to the first terminal of the secondary coil of the first balun and the gate of the fifth nmos transistor, the second terminal of the fourth capacitor (C4) is electrically connected to the drain of the sixth nmos transistor and the source of the eighth nmos transistor, the drain of the fifth nmos transistor is electrically connected to the first terminal of the fifth capacitor and the source of the seventh nmos transistor, and the source of the fifth nmos transistor is electrically connected to the source of the sixth nmos transistor and is used for grounding;

[0025] The gate of the sixth NMOS transistor is electrically connected to the second end of the secondary coil included in the first balun and the second end of the fifth capacitor, respectively.

[0026] The gates of the seventh NMOS transistor and the eighth NMOS transistor are respectively electrically connected to the first sub-output terminal included in the second output terminal of the bias circuit.

[0027] The drains of the seventh and eighth nmos transistors are electrically connected to the input terminals of the output matching circuit, respectively.

[0028] As an optional implementation, in the first aspect of the present invention, the adjustable gain amplifier stage sub-circuit further includes at least one second gain amplifier adjustment sub-circuit, wherein the first terminal of each second gain amplifier adjustment sub-circuit is electrically connected to a corresponding second sub-output terminal included in the second output terminal of the bias circuit; the second terminal of each second gain amplifier adjustment sub-circuit is electrically connected to the gate of the seventh nmos transistor and the gate of the eighth nmos transistor, respectively; and the third terminal of each second gain amplifier adjustment sub-circuit is used for grounding.

[0029] When the first terminal of a certain second gain amplification adjustment sub-circuit is in a conducting state with the second terminal of the second gain amplification adjustment sub-circuit, the first terminal of the second gain amplification adjustment sub-circuit and the third terminal of the second gain amplification adjustment sub-circuit are in a non-conducting state. The second gain amplification adjustment sub-circuit is used to adjust the gain amplification factor of the second radio frequency signal by the adjustable gain amplification stage circuit.

[0030] As an optional implementation, in the first aspect of the present invention, the bias circuit includes a first sub-bias circuit and a second sub-bias circuit.

[0031] The first sub-bias circuit includes a ninth NMOS transistor, a sixth capacitor, and a fourth resistor;

[0032] The drain of the ninth nmos transistor is electrically connected to the gate of the ninth nmos transistor and is used to input a first constant current. The gate of the ninth nmos transistor is electrically connected to the first terminal of the sixth capacitor and the first terminal of the fourth resistor. The source of the ninth nmos transistor and the second terminal of the sixth capacitor are grounded. The second terminal of the fourth resistor is electrically connected to the second terminal of the second resistor, the second terminal of the first resistor, the gate of the third nmos transistor, and the gate of the fourth nmos transistor.

[0033] As an optional implementation, in the first aspect of the present invention, the second sub-bias circuit includes: a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a fifth resistor, a seventh capacitor, and a current source.

[0034] In this circuit, the drain of the eleventh NMOS transistor and the gate of the twelfth NMOS transistor are used to input a second constant current. The source of the twelfth NMOS transistor is electrically connected to the first terminal of the current source, the first terminal of the seventh capacitor, the first terminal of the fifth resistor, and the gate of the tenth NMOS transistor. The drain of the twelfth NMOS transistor is used to connect to the power supply. The gate of the eleventh NMOS transistor is electrically connected to the gate of the seventh NMOS transistor and the gate of the eighth NMOS transistor. The source of the eleventh NMOS transistor is electrically connected to the drain of the tenth NMOS transistor. The second terminal of the current source, the source of the tenth NMOS transistor, and the second terminal of the seventh capacitor are used to ground. The second terminal of the fifth resistor is electrically connected to the third terminal of the secondary coil included in the balun in each interstage matching sub-circuit.

[0035] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0036] This invention discloses a power amplifier for the 5G band. The power amplifier includes an adjustable gain drive stage circuit, an inter-stage matching circuit, and an adjustable gain amplification stage circuit. The adjustable gain drive stage circuit amplifies a first radio frequency (RF) signal to obtain a second RF signal, and provides the second RF signal to the inter-stage matching circuit. The inter-stage matching circuit resonates at the operating frequency corresponding to the channel frequency of the second RF signal to increase the gain of the second RF signal, and provides the second RF signal to the adjustable gain amplification stage circuit. The adjustable gain amplification stage circuit amplifies the second RF signal to obtain a third RF signal, and provides the third RF signal to the antenna. Therefore, this invention can perform power combining using two-channel, two-stage power amplifiers, which can improve the gain of the power amplifier and enhance the stability of the RF signal during power combining. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of the circuit structure of a power amplifier applied to the 5G frequency band, as disclosed in an embodiment of the present invention;

[0039] Figure 2 This is a schematic diagram of the circuit structure of another power amplifier applied to the 5G band disclosed in an embodiment of the present invention;

[0040] Figure 3 This is a schematic diagram of the circuit structure of another power amplifier applied to the 5G band disclosed in an embodiment of the present invention;

[0041] Figure 4 This is a schematic diagram of the structure of an adjustable gain drive stage sub-circuit disclosed in an embodiment of the present invention;

[0042] Figure 5 This is a schematic diagram of the circuit structure of another power amplifier applied to the 5G band disclosed in an embodiment of the present invention;

[0043] Figure 6 This is a schematic diagram of the structure of an adjustable gain amplifier stage sub-circuit disclosed in an embodiment of the present invention;

[0044] Figure 7 This is a schematic diagram of the structure of a first sub-bias circuit disclosed in an embodiment of the present invention;

[0045] Figure 8This is a schematic diagram of the structure of a second sub-bias circuit disclosed in an embodiment of the present invention;

[0046] Figure 9 This is a schematic diagram of the circuit structure of another power amplifier applied to the 5G band, as disclosed in an embodiment of the present invention. Detailed Implementation

[0047] To better understand and implement this invention, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0048] It should be noted that, unless otherwise explicitly specified and limited, the term "electrical connection" in the specification, claims, and accompanying drawings of this invention should be interpreted broadly. For example, it can refer to a fixed electrical connection, a detachable electrical connection, or an integral electrical connection; it can be a mechanical electrical connection, an electrical-electrical connection, or a connection capable of communication; it can be a direct connection or an indirect connection through an intermediate medium; it can refer to the internal connection of two elements or the interaction between two elements. Furthermore, the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish different objects, not to describe a specific order. The terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0049] This invention discloses a power amplifier for the 5G band, which can perform power combining through two-stage power amplifiers, thereby improving the gain of the power amplifier and enhancing the stability of the radio frequency signal during power combining. These are described in detail below.

[0050] Example 1

[0051] Please see Figure 1 , Figure 1 This is a schematic diagram of the circuit structure of a power amplifier applied to the 5G frequency band, as disclosed in an embodiment of the present invention. Figure 1 As shown, the schematic diagram of the circuit structure of a power amplifier applied to the 5G band may include: an adjustable gain drive stage circuit 101, an inter-stage matching circuit 102, and an adjustable gain amplification stage circuit 103, wherein:

[0052] The input terminal of the adjustable gain drive stage circuit 101 is used to input the first radio frequency signal. The output terminal of the adjustable gain drive stage circuit 101 is electrically connected to the input terminal of the inter-stage matching circuit 102. The output terminal of the inter-stage matching circuit 102 is electrically connected to the input terminal of the adjustable gain amplifier stage circuit 103. The output terminal of the adjustable gain amplifier stage circuit 103 is used to electrically connect to the antenna.

[0053] The adjustable gain driver stage 101 amplifies the first radio frequency signal to obtain a second radio frequency signal, and provides the second radio frequency signal to the interstage matching circuit 102. The interstage matching circuit 102 resonates at the operating frequency point corresponding to the channel frequency of the second radio frequency signal to improve the gain of the second radio frequency signal, and provides the second radio frequency signal to the adjustable gain amplifier stage circuit 103. The adjustable gain amplifier stage circuit 103 amplifies the second radio frequency signal to obtain a third radio frequency signal, and provides the third radio frequency signal to the antenna.

[0054] In this embodiment of the invention, optionally, the adjustable gain drive stage circuit 101 can amplify the first radio frequency signal within a range of 0dB to 12dB. Further optionally, the adjustable gain drive stage circuit 101 can dynamically adjust the amplification of the first radio frequency signal.

[0055] In this embodiment of the invention, optionally, the channel frequency range of the second radio frequency signal can be from 4.92 GHz to 5.825 GHz. Further, the channel frequency range of the second radio frequency signal includes several channels, each with a different channel frequency. It should be noted that when the inter-stage matching circuit 102 resonates at the operating frequency corresponding to the channel frequency of the second radio frequency signal, the gain of the second radio frequency signal is highest and its performance is optimal.

[0056] In this embodiment of the invention, optionally, the adjustable gain amplifier stage circuit 103 can amplify the second radio frequency signal within a range of 0dB to 4.5dB. Further optionally, the amplification of the second radio frequency signal by the adjustable gain amplifier stage circuit 103 can be dynamically adjusted.

[0057] It is evident that implementation Figure 1 The described power amplifier for the 5G band uses an adjustable gain driver stage circuit, an inter-stage matching circuit, an adjustable gain amplifier stage circuit, and connections between these circuits to amplify the radio frequency (RF) signal twice through the adjustable gain driver stage circuit and the adjustable gain amplifier circuit. Furthermore, the amplification gain of the RF signal is dynamically adjusted, which helps to improve the gain, efficiency, and stability of the RF signal power amplification.

[0058] Example 2

[0059] Please see Figure 2 , Figure 2 This is a schematic diagram of another power amplifier circuit applied to the 5G band, as disclosed in an embodiment of the present invention. Figure 2 As shown, in Figure 1 Based on the circuit of the power amplifier applied to the 5G band shown, the power amplifier further includes at least one of the following: input matching circuit 104, output matching circuit 105, and bias circuit 106.

[0060] The input terminal of the input matching circuit 104 is used to input the first radio frequency signal, and the output terminal of the input matching circuit 104 is electrically connected to the input terminal of the adjustable gain drive stage circuit 101; the input matching circuit 104 inputs the first radio frequency signal to the adjustable gain drive stage circuit 101 without reflection.

[0061] The output terminal of the adjustable gain amplifier stage circuit 103 is electrically connected to the input terminal of the output matching circuit 105, and the output terminal of the output matching circuit 105 is used to electrically connect to the antenna; the output matching circuit 105 provides the third radio frequency signal output by the adjustable gain amplifier stage circuit to the antenna.

[0062] The first output terminal of the bias circuit 106 is electrically connected to the first bias circuit connection terminal of the adjustable gain drive stage circuit 101, and the second output terminal of the bias circuit 106 is electrically connected to the second bias circuit connection terminal of the adjustable gain amplifier stage circuit 103; the third output terminal of the bias circuit 106 is electrically connected to the third bias circuit connection terminal of the interstage matching circuit 102; the bias circuit 106 provides corresponding bias voltages to the adjustable gain drive stage circuit 101, the adjustable gain amplifier stage circuit 103, and the interstage matching circuit 102.

[0063] In this embodiment of the invention, the electrical connection relationship between the adjustable gain drive stage circuit 101, the inter-stage matching circuit 102, and the adjustable gain amplifier stage circuit 103 is described in Example 1. Figure 1 The descriptions will not be repeated in the embodiments of the present invention.

[0064] In this embodiment of the invention, optionally, the bias voltage provided by the bias circuit 106 to the adjustable gain drive stage circuit 101, the adjustable gain amplifier stage circuit 103, and the inter-stage matching circuit 102 can be the same or different for each circuit. This embodiment of the invention does not limit this.

[0065] In this embodiment of the invention, optionally, the third radio frequency signal can be combined in the output matching circuit 105, and the third radio frequency signal is provided to the antenna after the power is combined.

[0066] It is evident that implementation Figure 2The described power amplifier for the 5G band can input a first radio frequency signal to an adjustable gain drive stage circuit without reflection through an input matching circuit, provide a third radio frequency signal to an antenna through an output matching circuit, and provide corresponding bias voltages to the adjustable gain drive stage circuit, the adjustable gain amplification stage circuit, and the inter-stage matching circuit through a bias circuit. This can help improve the gain of the power amplifier in amplifying the radio frequency signal, improve the stability of the signal transmission in the circuit, and thus improve the stability of the radio frequency signal during power amplification.

[0067] In an optional embodiment, the adjustable gain drive stage circuit 101 includes two structurally identical adjustable gain drive stage sub-circuits, the inter-stage matching circuit 102 includes two structurally identical inter-stage matching sub-circuits, and the adjustable gain amplifier stage circuit 103 includes two structurally identical adjustable gain amplifier stage sub-circuits.

[0068] In this optional embodiment, such as Figure 3 As shown, Figure 3 This is a schematic diagram of the circuit structure of another power amplifier applied to the 5G frequency band. For example... Figure 3 As shown, the adjustable gain drive stage circuit 101 includes two structurally identical adjustable gain drive stage sub-circuits, namely DR1 and DR2; the adjustable gain amplifier stage circuit includes two structurally identical adjustable gain amplifier stage sub-circuits, namely PA1 and PA2.

[0069] As can be seen, the power amplifier for the 5G band described in this optional embodiment can input radio frequency signals into two identical adjustable gain drive stage sub-circuits, inter-stage matching sub-circuits, and adjustable gain amplification stage sub-circuits, which can help improve the gain of radio frequency signal power amplification, improve the efficiency of radio frequency signal power amplification, and improve the stability of radio frequency signal power amplification.

[0070] In another alternative embodiment, the adjustable gain drive stage sub-circuit includes a first capacitor C1, a second capacitor C2, a first resistor R1, a second resistor R2, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, and a fourth NMOS transistor NM4.

[0071] Wherein, the first terminal of the first capacitor C1 is electrically connected to the first output terminal of the input matching circuit 104, the second terminal of the first capacitor C1 is electrically connected to the first terminal of the first resistor R1 and the gate of the first NMOS transistor NM1, the source of the first NMOS transistor NM1 is electrically connected to the source of the second NMOS transistor NM2 and is used for grounding, and the drain of the first NMOS transistor NM1 is electrically connected to the source of the third NMOS transistor NM3.

[0072] The drain of the second NMOS transistor NM2 is electrically connected to the source of the fourth NMOS transistor NM4. The gate of the second NMOS transistor NM2 is electrically connected to the first terminal of the second resistor R2 and the first terminal of the second capacitor C2. The second terminal of the second capacitor C2 is electrically connected to the second output terminal of the input matching circuit 104. The second terminal of the second resistor R2 and the second terminal of the first resistor R1 are electrically connected to the first sub-output terminal included in the first output terminal of the bias circuit 106.

[0073] The gates of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are electrically connected to the second sub-output terminal included in the first output terminal of the bias circuit 106, and the drains of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are electrically connected to the input terminal of the same interstage matching sub-circuit 102.

[0074] In this optional embodiment, Figure 4 This is a schematic diagram of an adjustable gain drive stage sub-circuit. (Example) Figure 3 as well as Figure 4 As shown, DR1 or DR2 is determined by... Figure 4 It consists of all the remaining electronic components except for the first capacitor C1 and the second capacitor C2.

[0075] In this optional embodiment, the first capacitor C1 and the second capacitor C2 are DC blocking capacitors; the first resistor R1 and the second resistor R2 are AC blocking resistors; the first NMOS transistor NM1 and the second NMOS transistor NM2 are differential amplifier transistors; and the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are differential cascode transistors.

[0076] In this optional embodiment, the first radio frequency signal is input through the first DC blocking capacitor C1 and the second capacitor C2, respectively. The common mode of the first NMOS transistor NM1 and the second NMOS transistor NM2 of the differential amplifier is input through the first AC blocking resistor R1 and the second AC blocking resistor R2, respectively. After being amplified by the first NMOS transistor NM1 and the second NMOS transistor NM2 of the differential amplifier, the second radio frequency signal is obtained. The second radio frequency signal is output through the third NMOS transistor NM3 and the fourth NMOS transistor NM4 of the differential cascode, and the outputs of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 of the differential cascode are sent to the input terminal of the same interstage matching sub-circuit, so that the second radio frequency signal is output to the interstage matching circuit.

[0077] In this optional embodiment, the adjustable gain driver stage sub-circuit employs a differential cascode structure.

[0078] In this optional embodiment, the first resistor R1 and the second resistor R2 are used to prevent the input frequency of the first radio frequency signal to the first NMOS transistor NM1 and the second NMOS transistor NM2 from being too high, which would affect the amplification of the first radio frequency signal by the first NMOS transistor NM1 and the second NMOS transistor NM2.

[0079] As can be seen, the power amplifier for the 5G band described in this optional embodiment can input the first radio frequency signal through the DC blocking capacitors C1 and C2 respectively, which can help reduce the loss of the first radio frequency signal and improve the efficiency of the first radio frequency signal input. Furthermore, after the first radio frequency signal is amplified by the differential amplifier transistors NM1 and NM2, it is output to the input of the same interstage matching sub-circuit through the differential cascode transistors NM3 and NM4. This can help improve the gain of the radio frequency signal power amplification and improve the stability of the radio frequency signal power amplification.

[0080] In another optional embodiment, the adjustable gain drive stage sub-circuit further includes at least one first gain amplification adjustment sub-circuit, the first terminal of each first gain amplification adjustment sub-circuit being electrically connected to a corresponding third sub-output terminal included in the first output terminal of the bias circuit 106; the second terminal of each first gain amplification adjustment sub-circuit being electrically connected to the second terminal of the second resistor R2 and the second terminal of the first resistor R1, respectively; and the third terminal of each first gain amplification adjustment sub-circuit being grounded.

[0081] When the first terminal of a certain first gain amplification adjustment sub-circuit is in a conducting state with the second terminal of the first gain amplification adjustment sub-circuit, the first terminal of the first gain amplification adjustment sub-circuit and the third terminal of the first gain amplification adjustment sub-circuit are in a non-conducting state. The first gain amplification adjustment sub-circuit is used to realize the adjustment of the gain amplification factor of the first radio frequency signal by the adjustable gain drive stage circuit.

[0082] In this optional embodiment, such as Figure 4 As shown, the number of first gain amplification adjustment sub-circuits can be two. Optionally, the adjustable gain drive stage circuit can be a three-stage drive stage circuit arranged in a 1:1:2 ratio.

[0083] In this optional embodiment, when the first terminal of a first gain amplification adjustment sub-circuit and the third terminal of the first gain amplification adjustment sub-circuit are in a conducting state, the first terminal of the first gain amplification adjustment sub-circuit and the second terminal of the first gain amplification adjustment sub-circuit are in a non-conducting state, and the first gain amplification adjustment sub-circuit does not operate.

[0084] In this optional embodiment, each first gain amplification adjustment sub-circuit can optionally be a single-pole double-throw switch. The moving terminal of the single-pole double-throw switch is electrically connected to the corresponding third sub-output terminal included in the first output terminal of the bias circuit, and the other two terminals are stationary terminals. One of the stationary terminals is electrically connected to the second terminal of the second resistor R2 and the second terminal of the first resistor R1, respectively, and the other stationary terminal is used for grounding. It should be noted that when the moving terminal is in a conducting state with one of the stationary terminals, the moving terminal is in a non-conducting state with the other stationary terminal.

[0085] In this optional embodiment, for example, such as Figure 4 As shown, when one end of Vbias2_d is electrically connected to the second end of the second resistor R2 and the second end of the first resistor R1, and the other end of Vbias2_d is electrically connected to the corresponding third sub-output terminal included in the first output terminal of the bias circuit, the first gain amplification adjustment sub-circuit corresponding to Vbias2_d is used to adjust the gain amplification factor of the first radio frequency signal by the adjustable gain drive stage circuit.

[0086] As can be seen, the power amplifier applied to the 5G band described in this optional embodiment can, when the first terminal of a first gain amplification adjustment sub-circuit and the second terminal of the first gain amplification adjustment sub-circuit are in a conducting state, enable the adjustable gain drive stage circuit to adjust the gain amplification factor of the first radio frequency signal, which can help improve the gain of the radio frequency signal power amplification, improve the efficiency of the radio frequency signal power amplification, and improve the stability of the radio frequency signal power amplification.

[0087] In yet another optional embodiment, the interstage matching sub-circuit includes a third resistor R3, a third capacitor C3, and a first balun, with the third resistor R3 and the third capacitor C3 connected in parallel.

[0088] Specifically, the first end of the parallel connection of the third resistor R3 and the third capacitor C3 is electrically connected to the drain of the third NMOS transistor NM3 and the first end of the main coil of the first balun; the second end of the parallel connection of the third resistor R3 and the third capacitor C3 is electrically connected to the drain of the fourth NMOS transistor NM4 and the second end of the main coil of the first balun; the first and second ends of the secondary coil of the first balun are electrically connected to the two input terminals of the same adjustable gain amplifier stage sub-circuit.

[0089] The third terminal of the secondary coil of the first balun is electrically connected to the third output terminal of the bias circuit 106.

[0090] In this optional embodiment, the third capacitor C3 is an adjustable capacitor. Optionally, the third capacitor C3 resonates with the first balun, and the resonant point of the third capacitor C3 and the first balun corresponds to the second radio frequency signal, wherein the resonant point of the third capacitor C3 and the first balun is the operating frequency point corresponding to the channel frequency of the second radio frequency signal. It should be noted that the resonant point can be dynamically adjusted by the adjustable third capacitor C3, and the adjustable resonant point corresponding to the adjustable third capacitor C3 can cover the 5G frequency band. In this way, by having the third capacitor C3 and the first balun resonate at the operating frequency point corresponding to the channel frequency of the second radio frequency signal, the power amplification gain of the second radio frequency signal can be maximized.

[0091] In this optional embodiment, the third resistor R3 is an adjustable resistor. Optionally, the third resistor R3 can reduce the Q value of the interstage matching network. It should be noted that the Q value is the quality factor of the circuit, used to represent the response capability to high-frequency signals. A higher Q value indicates better selectivity but a narrower bandwidth. When improved selectivity is required, a higher Q value is needed; when a wider bandwidth is required, a lower Q value is needed. Thus, by using the adjustable third resistor R3, the power of the transmitted RF signal can be reduced when low-power RF signal transmission is required. Reducing the Q value of the interstage matching network can maintain the stability of the power amplifier while reducing the RF signal transmission power. Furthermore, reducing the Q value of the interstage matching network through the adjustable third resistor R3 can also widen the bandwidth, thereby improving bandwidth selectivity.

[0092] In this optional embodiment, optionally, Figure 5 This is a schematic diagram of the circuit structure of another power amplifier applied to the 5G band disclosed in an embodiment of the present invention, as shown below. Figure 5 As shown, the first end of the secondary coil of the first balun is electrically connected to the first input terminal of each adjustable gain amplifier stage sub-circuit, and the second end of the secondary coil of the first balun is electrically connected to the second input terminal of each adjustable gain amplifier stage sub-circuit. By short-circuiting the input terminals of the adjustable gain amplifier stage sub-circuits, the asymmetry between each adjustable gain amplifier stage sub-circuit can be reduced, and the symmetry and balance between each adjustable gain amplifier stage sub-circuit can be increased.

[0093] As can be seen, the power amplifier applied to the 5G band described in this optional embodiment can reduce the Q value of the interstage matching network through the adjustable resistor third resistor R3, and improve the gain of the second radio frequency signal by resonating with the first balun at the operating frequency corresponding to the channel frequency of the second radio frequency signal through the adjustable capacitor third capacitor C3. This can help improve the gain of the radio frequency signal power amplification and improve the efficiency of the radio frequency signal power amplification.

[0094] In yet another alternative embodiment, the adjustable gain amplifier stage sub-circuit includes a fourth capacitor C4, a fifth capacitor C5, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, and an eighth NMOS transistor NM8.

[0095] The first terminal of the fourth capacitor C4 is electrically connected to the first terminal of the secondary coil of the first balun and the gate of the fifth NMOS transistor NM5. The second terminal of the fourth capacitor C4 is electrically connected to the drain of the sixth NMOS transistor NM6 and the source of the eighth NMOS transistor NM8. The drain of the fifth NMOS transistor NM5 is electrically connected to the first terminal of the fifth capacitor C5 and the source of the seventh NMOS transistor NM7. The source of the fifth NMOS transistor NM5 is electrically connected to the source of the sixth NMOS transistor NM6 and is used for grounding.

[0096] The gate of the sixth NMOS transistor NM6 is electrically connected to the second terminal of the secondary coil included in the first balun and the second terminal of the fifth capacitor C5, respectively.

[0097] The gates of the seventh NMOS transistor NM7 and the eighth NMOS transistor NM8 are electrically connected to the first sub-output terminal included in the second output terminal of the bias circuit 106, respectively.

[0098] The drains of the seventh NMOS transistor NM7 and the eighth NMOS transistor NM8 are electrically connected to the input terminals of the output matching circuit 105, respectively.

[0099] In this optional embodiment, Figure 6 This is a schematic diagram of an adjustable gain amplifier stage sub-circuit. (Example) Figure 3 as well as Figure 6 As shown, Figure 6 The adjustable gain amplifier stage sub-circuit represented is Figure 3 PA1 or PA2 in the text.

[0100] In this optional embodiment, the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 are differential amplifier transistors; the seventh NMOS transistor NM7 and the eighth NMOS transistor NM8 are differential cascode transistors; and the fourth capacitor C4 and the fifth capacitor C5 are stability compensation capacitors.

[0101] In this optional embodiment, the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 of the differential amplifier amplify the input second RF signal to obtain a third RF signal, which is then output through the seventh NMOS transistor NM7 and the eighth NMOS transistor NM8 of the differential cascode transistor, so that the third RF signal is output to the output matching network.

[0102] In this optional embodiment, the adjustable gain amplifier stage sub-circuit employs a differential cascode structure.

[0103] As can be seen, the power amplifier for the 5G band described in this optional embodiment can amplify the second radio frequency signal by passing it through differential amplifier transistors NM5 and NM6 to obtain a third radio frequency signal. The third radio frequency signal is then output through differential cascode transistors NM7 and NM8 to the output matching network. This process can improve the gain, efficiency, and stability of the radio frequency signal power amplification.

[0104] In another optional embodiment, the adjustable gain amplifier stage sub-circuit further includes at least one second gain amplifier adjustment sub-circuit, the first terminal of each second gain amplifier adjustment sub-circuit being electrically connected to a corresponding second sub-output terminal included in the second output terminal of the bias circuit 106; the second terminal of each second gain amplifier adjustment sub-circuit being electrically connected to the gate of the seventh nmos transistor NM7 and the gate of the eighth nmos transistor NM8, respectively; and the third terminal of each second gain amplifier adjustment sub-circuit being grounded.

[0105] When the first terminal of a certain second gain amplification adjustment sub-circuit is in a conducting state with the second terminal of the second gain amplification adjustment sub-circuit, the first terminal of the second gain amplification adjustment sub-circuit and the third terminal of the second gain amplification adjustment sub-circuit are in a non-conducting state. The second gain amplification adjustment sub-circuit is used to adjust the gain amplification factor of the second radio frequency signal by the adjustable gain amplification stage circuit.

[0106] In this optional embodiment, such as Figure 6 As shown, the number of second gain amplifier adjustment sub-circuits can be one. Optionally, the power amplifier stage of the second gain amplifier adjustment sub-circuit can be two stages.

[0107] In this optional embodiment, optionally, when the first terminal and the third terminal of a certain second gain amplification adjustment sub-circuit are in a conducting state, the first terminal and the second terminal of the second gain amplification adjustment sub-circuit are in a non-conducting state, and the second gain amplification adjustment sub-circuit does not operate, and the adjustable gain amplification stage sub-circuit operates in mode 3; when the first terminal and the second terminal of a certain second gain amplification adjustment sub-circuit are in a conducting state, the first terminal and the third terminal of the second gain amplification adjustment sub-circuit are in a non-conducting state, and the second gain amplification adjustment sub-circuit is used to realize the adjustment of the gain amplification factor of the second radio frequency signal by the adjustable gain amplification stage circuit.

[0108] In this optional embodiment, for example, such as Figure 6 As shown, when one end of Vcas2_p is electrically connected to the gate of the seventh nmos transistor NM7 and the gate of the eighth nmos transistor NM8, and the other end of Vcas2_p is electrically connected to the corresponding second sub-output terminal included in the second output terminal of the bias circuit, the second gain amplification adjustment sub-circuit corresponding to Vcas2_p is used to adjust the gain amplification factor of the second RF signal by the adjustable gain amplification stage circuit.

[0109] As can be seen, the power amplifier applied to the 5G band described in this optional embodiment can, when the first terminal and the second terminal of a second gain amplification adjustment sub-circuit are in a conducting state, adjust the gain amplification factor of the second radio frequency signal by the adjustable gain amplification stage circuit. This can help improve the gain of the radio frequency signal power amplification, improve the efficiency of the radio frequency signal power amplification, and improve the stability of the radio frequency signal power amplification.

[0110] In yet another alternative embodiment, the bias circuit 106 includes a first sub-bias circuit and a second sub-bias circuit.

[0111] The first sub-bias circuit includes the ninth NMOS transistor NM9, the sixth capacitor C6, and the fourth resistor R4;

[0112] In this configuration, the drain of the ninth NMOS transistor NM9 is electrically connected to its gate and is used to input the first constant current. The gate of the ninth NMOS transistor NM9 is electrically connected to the first terminal of the sixth capacitor C6 and the first terminal of the fourth resistor R4. The source of the ninth NMOS transistor NM9 and the second terminal of the sixth capacitor C6 are grounded. The second terminal of the fourth resistor R4 is electrically connected to the second terminal of the second resistor R2, the second terminal of the first resistor R1, the gate of the third NMOS transistor NM3, and the gate of the fourth NMOS transistor NM4.

[0113] In this optional embodiment, such as Figure 7 As shown, Figure 7 This is a schematic diagram of the structure of a first sub-bias circuit disclosed in an embodiment of the present invention, wherein the first sub-bias circuit is a single-transistor mirror structure.

[0114] In this optional embodiment, the input of the first sub-bias circuit is a first constant current, and the output of the first sub-bias circuit is the bias voltage corresponding to the adjustable gain drive stage sub-circuit.

[0115] In this optional embodiment, the fourth resistor R4 is used to prevent the input first RF signal from being input to the gate of the ninth NMOS transistor NM9 and affecting its operation. The sixth capacitor C6 is a decapping capacitor. The decapping capacitor, the sixth capacitor C6, is used to maintain the same jitter frequency between the gate of the ninth NMOS transistor NM9 and ground, so that the ninth NMOS transistor NM9 operates normally at the corresponding operating point. The fourth resistor R4 and the decapping capacitor, the sixth capacitor C6, work together to ensure the normal operation of the first sub-bias circuit and the adjustable gain drive stage sub-circuit.

[0116] In this optional embodiment, the width-to-length ratio of the ninth nmos transistor NM9 to the first nmos transistor NM1 and the second nmos transistor NM2 of the differential amplifier are multiples of each other, so as to achieve consistency in the gain factor of the power amplification of each adjustable gain drive stage sub-circuit at different temperatures.

[0117] As can be seen, the power amplifier for the 5G band described in this optional embodiment can input a first constant current through the ninth nmos transistor NM9, and use the fourth resistor R4 and the sixth decap capacitor C6 to keep the gate of the ninth nmos transistor NM9 and ground at the same jitter frequency, so that the ninth nmos transistor NM9 can work normally at the corresponding operating point, can provide the corresponding bias voltage to the adjustable gain drive stage sub-circuit, and can help improve the stability of power amplification of radio frequency signals.

[0118] In yet another optional embodiment, the second sub-bias circuit includes: a tenth NMOS transistor NM10, an eleventh NMOS transistor NM11, a twelfth NMOS transistor NM12, a fifth resistor R5, a seventh capacitor C7, and a current source A1.

[0119] In this circuit, the drain of the eleventh NMOS transistor NM11 and the gate of the twelfth NMOS transistor NM12 are used to input the second constant current. The source of the twelfth NMOS transistor NM12 is electrically connected to the first terminal of the current source A1, the first terminal of the seventh capacitor C7, the first terminal of the fifth resistor R5, and the gate of the tenth NMOS transistor NM10. The drain of the twelfth NMOS transistor NM12 is used to connect to the power supply. The gate of the eleventh NMOS transistor NM11 is electrically connected to the gate of the seventh NMOS transistor NM7 and the gate of the eighth NMOS transistor NM8. The source of the eleventh NMOS transistor NM11 is electrically connected to the drain of the tenth NMOS transistor NM10. The second terminal of the current source A1, the source of the tenth NMOS transistor NM10, and the second terminal of the seventh capacitor C7 are used to ground. The second terminal of the fifth resistor R5 is electrically connected to the third terminal of the secondary coil included in the balun in each interstage matching sub-circuit.

[0120] In this optional embodiment, such as Figure 8 As shown, Figure 8 This is a schematic diagram of the structure of a second sub-bias circuit disclosed in an embodiment of the present invention. The second sub-bias circuit is a mirror structure and a loop structure. In this way, the loop structure can reduce the equivalent output impedance, which can help reduce the memory effect of the adjustable gain amplifier stage sub-circuit, and thus help improve the stability of power amplification of radio frequency signals.

[0121] In this optional embodiment, the input of the second sub-bias circuit is the second constant current, and the output of the second sub-bias circuit is the bias voltage corresponding to the adjustable gain amplifier stage sub-circuit.

[0122] In this optional embodiment, the seventh capacitor C7 is a decapping capacitor. The decapping capacitor C7 is used to maintain the same jitter frequency between the gate and ground of the tenth NMOS transistor NM10, ensuring that the tenth NMOS transistor NM10 operates normally at the corresponding operating point. The fifth resistor R5 is used to prevent the input second RF signal from being input to the gate of the tenth NMOS transistor NM10 and affecting its operation. The fifth resistor R5 and the decapping capacitor C6 work together to ensure the normal operation of the second sub-bias circuit and the adjustable gain amplifier stage sub-circuit.

[0123] In this optional embodiment, the width-to-length ratio of the tenth NMOS transistor NM10 to the differential cascode transistors, the seventh NMOS transistor NM7 and the eighth NMOS transistor NM8, is a multiple of each other, so as to achieve consistency in the gain factor of the power amplification of each adjustable gain drive stage sub-circuit at different temperatures.

[0124] As can be seen, the power amplifier for the 5G band described in this optional embodiment can input a second constant current through the eleventh NMOS transistor NM11 and the twelfth NMOS transistor NM12, and through the combined action of the fifth resistor R5 and the decap capacitor and the sixth capacitor C6, enable the second sub-bias circuit and the adjustable gain amplifier stage sub-circuit to work normally. It can provide the corresponding bias voltage to the adjustable gain amplifier stage sub-circuit and the inter-stage matching circuit, and can help improve the stability of power amplification of radio frequency signals.

[0125] In another alternative embodiment, the input matching circuit 104 includes: a sixth resistor R6, a seventh resistor R7, an eighth capacitor C8, a ninth capacitor C9, a first inductor L1, and a second inductor L2, wherein the sixth resistor R6 is connected in parallel with the eighth capacitor C8 and the first inductor L1, and the seventh resistor R7 is connected in parallel with the ninth capacitor C9 and the second inductor L2.

[0126] The first end of the parallel connection of the sixth resistor R6, the eighth capacitor C8, and the first inductor L1 is electrically connected to the first input terminal of the first radio frequency signal and the first end of the first capacitor C1, respectively. The second end of the parallel connection of the sixth resistor R6, the eighth capacitor C8, and the first inductor L1 is electrically connected to the first end of the parallel connection of the seventh resistor R7, the ninth capacitor C9, and the second inductor L2, respectively. The second end of the parallel connection of the seventh resistor R7, the ninth capacitor C9, and the second inductor L2 is electrically connected to the second input terminal of the first radio frequency signal and the second end of the second capacitor C2, respectively.

[0127] In this optional embodiment, such as Figure 3 As shown, Figure 3 This is a schematic diagram of a power amplifier circuit applied to the 5G band. The first radio frequency signal is input from the first terminal of the parallel connection of the sixth resistor R6, the eighth capacitor C8, and the first inductor L1, and the second terminal of the parallel connection of the sixth resistor R6, the eighth capacitor C8, and the first inductor L1. The eighth capacitor C8 and the first inductor L1, and the ninth capacitor C9 and the second inductor L2 resonate at the operating frequency point corresponding to the channel frequency of the first radio frequency signal, so that the first radio frequency signal can be input to the adjustable gain drive stage sub-circuit without reflection.

[0128] In this optional embodiment, the sixth resistor R6 and the seventh resistor R7 are adjustable resistors, and the eighth capacitor C8 and the ninth capacitor C9 are adjustable capacitors. The adjustable resistors R6 and R7 can reduce the Q value of the input matching network, and the adjustable capacitors C8 and C9 can dynamically adjust the resonant point. The adjustment range of the resonant point can cover the entire 5G frequency band. In this way, the first RF signal can be input to the adjustable gain drive stage sub-circuit without reflection through the adjustable resistors and capacitors, which can help improve the stability of power amplification of the RF signal.

[0129] As can be seen, the power amplifier for the 5G band described in this optional embodiment can input the first radio frequency signal to the adjustable gain drive stage circuit without reflection through the input matching circuit, which can help improve the stability of the signal transmission in the circuit, and thus help improve the stability of the radio frequency signal during power amplification.

[0130] In yet another alternative embodiment, the output matching circuit 105 includes a tenth capacitor C10 and a second balun;

[0131] The first terminal of the tenth capacitor C10 is electrically connected to the drain of the seventh NMOS transistor NM7 in different adjustable gain amplifier sub-circuits and the first terminal of the main coil of the second balun. The second terminal of the tenth capacitor C10 is electrically connected to the drain of the eighth NMOS transistor NM8 in different adjustable gain amplifier sub-circuits and the second terminal of the main coil of the second balun. The first terminal and the second terminal of the secondary coil of the second balun are used to electrically connect to the antenna.

[0132] In this optional embodiment, such as Figure 3 As shown, Figure 3 This is a schematic diagram of the circuit structure of a power amplifier applied to the 5G band. The third radio frequency signal is input to the output matching circuit. The tenth capacitor C10 and the second balun in the output matching circuit resonate at the operating frequency point corresponding to the channel frequency of the third radio frequency signal to maintain the stability of the third radio frequency signal and provide the third radio frequency signal to the antenna.

[0133] As can be seen, the power amplifier applied to the 5G band described in this optional embodiment can maintain the stability of the third radio frequency signal by resonating at the operating frequency point corresponding to the channel frequency of the third radio frequency signal through the tenth capacitor C10 and the second balun in the output matching circuit. This can help improve the stability of providing the third radio frequency signal to the antenna, and thus help improve the stability of power amplification of the radio frequency signal.

[0134] In yet another alternative embodiment, the output matching circuit 105 includes an eleventh capacitor C11, a twelfth capacitor C12, and a third balun.

[0135] Specifically, the first terminal of the eleventh capacitor C11 is electrically connected to the drain of the seventh NMOS transistor NM7 in one of the adjustable amplifier stage sub-circuits and the first terminal of the main coil of the third balun. The second terminal of the eleventh capacitor C11 is electrically connected to the drain of the eighth NMOS transistor NM8 in the adjustable amplifier stage sub-circuit and the second terminal of the main coil of the third balun. The third terminal of the main coil of the third balun is electrically connected to the first terminal of the twelfth capacitor C12 and the drain of the seventh NMOS transistor NM7 in the remaining adjustable amplifier stage sub-circuits (excluding the adjustable amplifier stage sub-circuit). The fourth terminal of the main coil of the third balun is electrically connected to the second terminal of the twelfth capacitor C12 and the drain of the eighth NMOS transistor NM8 in the remaining adjustable amplifier stage sub-circuit (excluding the adjustable amplifier stage sub-circuit). The first and second terminals of the secondary coil of the third balun are used to electrically connect to the antenna.

[0136] In this optional embodiment, such as Figure 9 As shown, Figure 9This is a schematic diagram of another power amplifier circuit applied to the 5G band. The third balun has four input ports and two output ports. The four input ports of the third balun are the four ports of the main coil, and the two output ports are the two ports of the secondary coil. Further, the first and second ends of the main coil of the third balun form one set of input ports, and the third and fourth ends of the main coil form another set of input ports. One set of input ports is electrically connected to the output of an adjustable amplifier stage sub-circuit, and the other set of input ports is electrically connected to the output of another adjustable amplifier stage sub-circuit.

[0137] In this optional embodiment, the power combining operation of the third radio frequency signal can be achieved through electromagnetic coupling in the third balun. This power combining of the third radio frequency signal through the third balun can improve the efficiency of power combining, improve the stability of providing the third radio frequency signal to the antenna, and thus improve the stability of power amplification of the radio frequency signal.

[0138] As can be seen, the power amplifier applied to the 5G band described in this optional embodiment can achieve power synthesis through electromagnetic coupling in the third balun, which can help improve the efficiency of power synthesis, improve the stability of providing the third radio frequency signal to the antenna, and thus help improve the stability of power amplification of the radio frequency signal.

[0139] The above provides a detailed description of a power amplifier for 5G bands in an electronic device disclosed in the embodiments of the present invention. Specific embodiments have been used to illustrate the principles and implementation of the present invention. However, the above preferred embodiments are not intended to limit the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, based on the ideas of the present invention, there will be changes in the specific implementation and application scope without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention is defined by the scope of the claims.

Claims

1. A power amplifier for use in the 5G frequency band, characterized in that, The power amplifier includes an adjustable gain drive stage circuit, an interstage matching circuit, and an adjustable gain amplification stage circuit. The adjustable gain drive stage circuit has an input terminal for inputting a first radio frequency signal, an output terminal for electrically connecting to the input terminal of the inter-stage matching circuit, an output terminal for electrically connecting to the input terminal of the adjustable gain amplifier stage circuit, and an output terminal for electrically connecting to the antenna. The adjustable gain drive stage circuit amplifies the first radio frequency signal to obtain a second radio frequency signal, and provides the second radio frequency signal to the inter-stage matching circuit. The inter-stage matching circuit resonates at the operating frequency point corresponding to the channel frequency of the second radio frequency signal to improve the gain of the second radio frequency signal, and provides the second radio frequency signal to the adjustable gain amplifier stage circuit. The adjustable gain amplifier stage circuit amplifies the second radio frequency signal to obtain a third radio frequency signal, and provides the third radio frequency signal to the antenna. The adjustable gain drive stage circuit includes two structurally identical adjustable gain drive stage sub-circuits. The adjustable gain drive stage sub-circuit includes a first capacitor (C1), a second capacitor (C2), a first resistor (R1), a second resistor (R2), a first NMOS transistor (NM1), a second NMOS transistor (NM2), a third NMOS transistor (NM3), and a fourth NMOS transistor (NM4). Wherein, the first terminal of the first capacitor (C1) is electrically connected to the first output terminal of the input matching circuit, the second terminal of the first capacitor (C1) is electrically connected to the first terminal of the first resistor (R1) and the gate of the first NMOS transistor (NM1), the source of the first NMOS transistor (NM1) is electrically connected to the source of the second NMOS transistor (NM2) and is used for grounding, and the drain of the first NMOS transistor (NM1) is electrically connected to the source of the third NMOS transistor (NM3). The drain of the second NMOS transistor (NM2) is electrically connected to the source of the fourth NMOS transistor (NM4). The gate of the second NMOS transistor (NM2) is electrically connected to the first terminal of the second resistor (R2) and the first terminal of the second capacitor (C2). The second terminal of the second capacitor (C2) is electrically connected to the second output terminal of the input matching circuit. The second terminal of the second resistor (R2) and the second terminal of the first resistor (R1) are electrically connected to the first sub-output terminal included in the first output terminal of the bias circuit. The gates of the third NMOS transistor (NM3) and the fourth NMOS transistor (NM4) are electrically connected to the second sub-output terminal included in the first output terminal of the bias circuit, and the drains of the third NMOS transistor (NM3) and the fourth NMOS transistor (NM4) are electrically connected to the input terminal of the same interstage matching sub-circuit.

2. The power amplifier for 5G bands according to claim 1, characterized in that, The power amplifier further includes at least one of an input matching circuit, an output matching circuit, and a bias circuit. The input terminal of the input matching circuit is used to input the first radio frequency signal, and the output terminal of the input matching circuit is electrically connected to the input terminal of the adjustable gain drive stage circuit; the input matching circuit inputs the first radio frequency signal to the adjustable gain drive stage circuit without reflection. The output terminal of the adjustable gain amplifier stage circuit is electrically connected to the input terminal of the output matching circuit, and the output terminal of the output matching circuit is used to electrically connect to the antenna; the output matching circuit provides the third radio frequency signal output by the adjustable gain amplifier stage circuit to the antenna. The first output terminal of the bias circuit is electrically connected to the first bias circuit connection terminal of the adjustable gain drive stage circuit, and the second output terminal of the bias circuit is electrically connected to the second bias circuit connection terminal of the adjustable gain amplifier stage circuit; the third output terminal of the bias circuit is electrically connected to the third bias circuit connection terminal of the interstage matching circuit; the bias circuit provides corresponding bias voltages to the adjustable gain drive stage circuit, the adjustable gain amplifier stage circuit, and the interstage matching circuit.

3. A power amplifier for use in the 5G band according to claim 2, characterized in that, The interstage matching circuit includes two structurally identical interstage matching sub-circuits, and the adjustable gain amplification stage circuit includes two structurally identical adjustable gain amplification stage sub-circuits.

4. A power amplifier for use in the 5G band according to claim 3, characterized in that, The adjustable gain drive stage sub-circuit further includes at least one first gain amplification adjustment sub-circuit. The first terminal of each first gain amplification adjustment sub-circuit is electrically connected to the corresponding third sub-output terminal included in the first output terminal of the bias circuit. The second terminal of each first gain amplification adjustment sub-circuit is electrically connected to the second terminal of the second resistor (R2) and the second terminal of the first resistor (R1), respectively. The third terminal of each first gain amplification adjustment sub-circuit is used for grounding. When the first terminal of a certain first gain amplification adjustment sub-circuit is in a conducting state with the second terminal of the first gain amplification adjustment sub-circuit, the first terminal of the first gain amplification adjustment sub-circuit and the third terminal of the first gain amplification adjustment sub-circuit are in a non-conducting state. The first gain amplification adjustment sub-circuit is used to adjust the gain amplification factor of the first radio frequency signal by the adjustable gain drive stage circuit.

5. A power amplifier for use in the 5G band according to claim 4, characterized in that, The interstage matching sub-circuit includes a third resistor (R3), a third capacitor (C3), and a first balun, wherein the third resistor (R3) and the third capacitor (C3) are connected in parallel; Wherein, the first end of the third resistor (R3) and the third capacitor (C3) connected in parallel is electrically connected to the drain of the third NMOS transistor (NM3) and the first end of the main coil of the first balun; the second end of the third resistor (R3) and the third capacitor (C3) connected in parallel is electrically connected to the drain of the fourth NMOS transistor (NM4) and the second end of the main coil of the first balun; the first end and the second end of the secondary coil of the first balun are electrically connected to the two input terminals of the same adjustable gain amplifier stage sub-circuit. The third terminal of the secondary coil of the first balun is electrically connected to the third output terminal of the bias circuit.

6. A power amplifier for use in the 5G band according to claim 5, characterized in that, The adjustable gain amplifier stage sub-circuit includes a fourth capacitor (C4), a fifth capacitor (C5), a fifth NMOS transistor (NM5), a sixth NMOS transistor (NM6), a seventh NMOS transistor (NM7), and an eighth NMOS transistor (NM8). Wherein, the first terminal of the fourth capacitor (C4) is electrically connected to the first terminal of the secondary coil of the first balun and the gate of the fifth NMOS transistor (NM5), the second terminal of the fourth capacitor (C4) is electrically connected to the drain of the sixth NMOS transistor (NM6) and the source of the eighth NMOS transistor (NM8), the drain of the fifth NMOS transistor (NM5) is electrically connected to the first terminal of the fifth capacitor (C5) and the source of the seventh NMOS transistor (NM7), and the source of the fifth NMOS transistor (NM5) is electrically connected to the source of the sixth NMOS transistor (NM6) and is used for grounding; The gate of the sixth NMOS transistor (NM6) is electrically connected to the second terminal of the secondary coil included in the first balun and the second terminal of the fifth capacitor (C5). The gates of the seventh NMOS transistor (NM7) and the eighth NMOS transistor (NM8) are respectively electrically connected to the first sub-output terminal included in the second output terminal of the bias circuit. The drains of the seventh NMOS transistor (NM7) and the eighth NMOS transistor (NM8) are electrically connected to the input terminal of the output matching circuit, respectively.

7. A power amplifier for use in the 5G band according to claim 6, characterized in that, The adjustable gain amplifier stage sub-circuit further includes at least one second gain amplifier adjustment sub-circuit. The first terminal of each second gain amplifier adjustment sub-circuit is electrically connected to the corresponding second sub-output terminal included in the second output terminal of the bias circuit. The second terminal of each second gain amplifier adjustment sub-circuit is electrically connected to the gate of the seventh NMOS transistor (NM7) and the gate of the eighth NMOS transistor (NM8), respectively. The third terminal of each second gain amplifier adjustment sub-circuit is used for grounding. When the first terminal of a certain second gain amplification adjustment sub-circuit is in a conducting state with the second terminal of the second gain amplification adjustment sub-circuit, the first terminal of the second gain amplification adjustment sub-circuit and the third terminal of the second gain amplification adjustment sub-circuit are in a non-conducting state. The second gain amplification adjustment sub-circuit is used to adjust the gain amplification factor of the second radio frequency signal by the adjustable gain amplification stage circuit.

8. A power amplifier for use in the 5G band according to claim 7, characterized in that, The bias circuit includes a first sub-bias circuit and a second sub-bias circuit; The first sub-bias circuit includes a ninth NMOS transistor (NM9), a sixth capacitor (C6), and a fourth resistor (R4). The drain of the ninth NMOS transistor (NM9) is electrically connected to its gate and used to input a first constant current. The gate of the ninth NMOS transistor (NM9) is electrically connected to the first terminal of the sixth capacitor (C6) and the first terminal of the fourth resistor (R4). The source of the ninth NMOS transistor (NM9) and the second terminal of the sixth capacitor (C6) are grounded. The second terminal of the fourth resistor (R4) is electrically connected to the second terminal of the second resistor (R2), the second terminal of the first resistor (R1), the gate of the third NMOS transistor (NM3), and the gate of the fourth NMOS transistor (NM4).

9. A power amplifier for use in the 5G band according to claim 8, characterized in that, The second sub-bias circuit includes: the tenth NMOS transistor (NM10), the eleventh NMOS transistor (NM11), the twelfth NMOS transistor (NM12), the fifth resistor (R5), the seventh capacitor (C7), and the current source (A1). The drain of the eleventh NMOS transistor (NM11) and the gate of the twelfth NMOS transistor (NM12) are used to input a second constant current. The source of the twelfth NMOS transistor (NM12) is electrically connected to the first terminal of the current source (A1), the first terminal of the seventh capacitor (C7), the first terminal of the fifth resistor (R5), and the gate of the tenth NMOS transistor (NM10). The drain of the twelfth NMOS transistor (NM12) is used to connect to the power supply. The eleventh NMOS transistor (NM11)... The gates of the eleventh nmos transistor (NM11) are electrically connected to the gates of the seventh nmos transistor (NM7) and the eighth nmos transistor (NM8), respectively. The source of the eleventh nmos transistor (NM11) is electrically connected to the drain of the tenth nmos transistor (NM10). The second terminal of the current source (A1), the source of the tenth nmos transistor (NM10), and the second terminal of the seventh capacitor (C7) are grounded. The second terminal of the fifth resistor (R5) is electrically connected to the third terminal of the secondary coil included in the balun in each of the interstage matching sub-circuits.

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