A delay-locked loop circuit, a clock generation chip, and an electronic device

Abstract

The application discloses a delay phase-locked loop circuit, a clock generation chip and electronic equipment, and aims at solving how to realize the anti-mislock function in the delay phase-locked loop with lower cost in the prior art. The delay phase-locked loop circuit provided by the embodiment of the application comprises a phase discrimination circuit, a charge pump, a loop filter, a voltage-controlled delay chain and a phase detection circuit. The filter capacitor in the charge pump can be charged before the first rising edge of the reference clock signal arrives, that is, before the circuit works, so that the delay of the voltage-controlled delay chain can be set to the minimum before the circuit works, and then the harmonic lock can be avoided. Since the application only uses one phase detection circuit to avoid the harmonic lock of the circuit, compared with the sampling of the input clock signal to other phase clock signals to avoid the harmonic lock, the cost can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of phase-locked loop, in particular to a delay-locked loop circuit, a clock generation chip and an electronic device. BACKGROUND

[0002] With the continuous improvement of the working frequency and signal processing accuracy of digital and digital-analog hybrid system chips, the performance requirements for the clock circuit therein are getting higher and higher, and the phase-locked loop technology is widely used to generate high-performance clock signals. As a kind of phase-locked loop, the delay-locked loop uses a voltage-controlled delay chain to replace the voltage-controlled oscillator in the traditional phase-locked loop, so as to obtain better phase noise characteristics, and due to the first-order system of the loop of the delay-locked loop, it has better stability and simpler circuit structure, so it is widely used to generate multi-phase high-precision clock signals.

[0003] An important problem faced by the delay-locked loop in the related art is how to ensure that the entire system can be correctly locked, that is, to ensure that the phase of the last stage of the output clock signal is exactly one period of the phase of the input reference clock signal, and at the same time, to ensure that the circuit can correctly and timely return to the locked state after being disturbed and deviating from the locked state.

[0004] One error lock detection method in the related art is to sample other phase clock signals with the input reference clock signal, and then obtain the phase relationship thereof through combination logic relationship, so as to generate an identification signal and input it into a phase discriminator circuit, and further output a phase discrimination signal up (charging switch signal) and down (discharging switch signal) through the phase discriminator circuit to control the charging and discharging of the charge pump, so as to adjust the control voltage of the voltage-controlled delay chain in real time to avoid false lock. This method has high reliability, but as the number of phase outputs of the voltage-controlled delay chain increases, the size of the detection circuit also increases, and the overhead and complexity of the circuit also increase, so it is not suitable for delay-locked loop circuits with more phase outputs.

[0005] In summary, how to realize the false lock prevention function in the delay-locked loop with lower overhead is a problem to be solved at present. SUMMARY

[0006] The present application provides a delay-locked loop circuit, a clock generation chip and an electronic device to solve the problem of how to realize the false lock prevention function in the delay-locked loop with lower overhead in the prior art.

[0007] In a first aspect, an embodiment of the present application provides a delay-locked loop circuit, comprising: a phase discriminator circuit, a charge pump, a loop filter, a voltage-controlled delay chain and a phase detection circuit;

[0008] The voltage-controlled delay chain is configured to delay the reference clock signal and output a plurality of delay signals.

[0009] The delay buffer circuit is configured to perform an inverting or buffering operation on each of the delay signals and output a plurality of phase clock signals.

[0010] The phase detection circuit is configured to output a phase detection signal according to the reference clock signal and the last-stage phase clock signal.

[0011] The charge pump is configured to charge and discharge a filter capacitor in the charge pump according to the phase detection signal and output a voltage control signal.

[0012] The loop filter is configured to filter the voltage control signal and control a delay time length of the voltage-controlled delay chain.

[0013] The phase detection circuit is configured to, before a first rising edge of the reference clock signal arrives, turn on a path between a power supply end and a loop filter capacitor in the loop filter according to a front-stage phase clock signal of a positive middle-stage, so as to charge the loop filter capacitor.

[0014] In a possible implementation, the phase detection circuit includes a control unit and a turn-on unit.

[0015] The control unit is configured to, before the first rising edge of the reference clock signal arrives, output a turn-on control signal for controlling the turn-on unit to turn on according to the front-stage phase clock signal.

[0016] In a possible implementation, the control unit includes an OR gate, a first D flip-flop and a first inverter.

[0017] A first input end of the OR gate is configured to input a first front-stage phase clock signal of a positive middle-stage, a second input end of the OR gate is configured to input a second front-stage phase clock signal of the positive middle-stage, and an output end of the OR gate is connected with a D end of the first D flip-flop, where the first front-stage phase clock signal and the second front-stage phase clock signal are different.

[0018] A CK end of the first D flip-flop is configured to input the reference clock signal, a Q end of the first D flip-flop is connected with an input end of the first inverter, and an output end of the first inverter is configured to output the turn-on control signal.

[0019] In a possible implementation, the control unit further includes a second D flip-flop, a third D flip-flop, an NOR gate, a second inverter and an AND gate.

[0020] The D end of the second D flip-flop is connected with the D end of the third D flip-flop, for inputting the second front-stage phase clock signal; the CK end of the second D flip-flop and the CK end of the third D flip-flop are connected, for inputting the reference clock signal; the Q end of the second D flip-flop is connected with the first input end of the NOR gate;

[0021] The Q end of the third D flip-flop is connected with the second input end of the NOR gate;

[0022] The output end of the NOR gate is connected with the second input end of the AND gate;

[0023] The output end of the first inverter is connected with the first input end of the AND gate;

[0024] The output end of the AND gate is used for outputting the conduction control signal.

[0025] In a possible implementation, the control unit comprises a fourth D flip-flop and a third inverter;

[0026] The D end of the fourth D flip-flop is used for inputting the third front-stage phase clock signal of the positive middle stage; the set end of the fourth D flip-flop is used for inputting the first enable signal; the CK end of the fourth D flip-flop is used for inputting the reference clock signal; and the Q end of the fourth D flip-flop is connected with the input end of the third inverter;

[0027] The output end of the third inverter is used for outputting the conduction control signal.

[0028] In a possible implementation, the conduction unit comprises a switch tube;

[0029] The control end of the switch tube is used for inputting the conduction control signal; the first end of the switch tube is connected with the power supply end; and the second end of the switch tube is connected with one end of the capacitor.

[0030] In a possible implementation, a first counter is further included;

[0031] The first counter is connected between the control unit and the conduction unit, for outputting the conduction control signal after reaching a count value.

[0032] In a possible implementation, a phase-detecting starting circuit is further included;

[0033] The phase-detecting starting circuit is used for controlling the phase-detecting circuit to start after the first rising edge of the last-stage phase clock signal comes under the control of the second enable signal and the reference clock signal.

[0034] In a possible implementation, the phase discrimination circuit comprises a fifth D flip-flop, a sixth D flip-flop, a first buffer, a second buffer, a third buffer, and a NAND gate.

[0035] The D input end of the fifth D flip-flop is connected with the power supply end, the CK end of the fifth D flip-flop is used for inputting a reference clock signal, the set end of the fifth D flip-flop is connected with the set end of the sixth D flip-flop and the output end of the third buffer, the Q output end of the fifth D flip-flop is connected with the input end of the first buffer, the output end of the first buffer is connected with the first input end of the NAND gate, and a first phase discrimination signal is outputted, the D input end of the sixth D flip-flop is connected with the power supply end, the CK end of the sixth D flip-flop is used for inputting a last-stage phase clock signal, the Q output end of the sixth D flip-flop is connected with the input end of the second buffer B2, the output end of the second buffer B2 is connected with the second input end of the NAND gate, and a second phase discrimination signal is outputted, and the output end of the NAND gate is connected with the input end of the third buffer.

[0036] The phase discrimination starting circuit comprises a second AND gate.

[0037] The first input end of the second AND gate is connected with the output end of the NAND gate, the second input end of the second AND gate is used for inputting a second enable signal, and the output end of the second AND gate is connected with the third buffer.

[0038] In a second aspect, an embodiment of the present application provides a clock generation chip, which comprises the delay-locked loop circuit according to any one of the first aspect.

[0039] In a third aspect, an embodiment of the present application provides an electronic device, which comprises the clock generation chip according to the second aspect.

[0040] The present application has the following advantages:

[0041] The delay-locked loop circuit, the clock generation chip and the electronic device provided by the embodiment of the present application, the delay-locked loop circuit comprises a phase discrimination circuit, a charge pump, a loop filter, a voltage-controlled delay chain and a phase detection circuit, the filter capacitor in the charge pump can be charged before the first rising edge of the reference clock signal arrives, that is, before the circuit works, so that the delay of the voltage-controlled delay chain can be set to be minimum before the circuit works, and then the harmonic locking can be avoided, since only one phase detection circuit is used in the embodiment of the present application, the harmonic locking of the circuit can be avoided, and therefore, compared with the method of sampling other phase clock signals to avoid the harmonic locking, the cost can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0043] Figure 1 A structure schematic diagram of a delay-locked loop circuit in the related art;

[0044] Figure 2 A circuit schematic diagram of a voltage-controlled delay chain in the delay-locked loop circuit in the related art;

[0045] Figure 3 A circuit schematic diagram of a delay buffer circuit in the delay-locked loop circuit in the related art;

[0046] Figure 4 A circuit schematic diagram of a phase detection circuit in the delay-locked loop circuit in the related art;

[0047] Figure 5 A timing schematic diagram of harmonic locking in the delay-locked loop circuit in the related art;

[0048] Figure 6 A timing schematic diagram of zero locking in the delay-locked loop circuit in the related art;

[0049] Figure 7 A structure schematic diagram of a delay-locked loop circuit provided by the embodiments of the present application;

[0050] Figure 8 A structure schematic diagram of a phase detection circuit in a delay-locked loop provided by the embodiments of the present application;

[0051] Figure 9 A circuit schematic diagram of a control unit provided by the embodiments of the present application;

[0052] Figure 10 A circuit schematic diagram of another control unit provided by the embodiments of the present application;

[0053] Figure 11 A circuit schematic diagram of another control unit provided by the embodiments of the present application;

[0054] Figure 12 A circuit schematic diagram of a phase detection circuit provided by the embodiments of the present application;

[0055] Figure 13 A circuit schematic diagram of another phase detection circuit provided by the embodiments of the present application;

[0056] Figure 14A circuit diagram of another phase detection circuit provided by an embodiment of the present invention;

[0057] Figure 15 A circuit diagram of another phase detection circuit provided by an embodiment of the present invention;

[0058] Figure 16 A circuit diagram of another phase detection circuit provided by an embodiment of the present invention;

[0059] Figure 17 A circuit diagram of another phase detection circuit provided by an embodiment of the present invention;

[0060] Figure 18 A timing diagram of a delay phase-locked loop circuit normally locked according to an embodiment of the present invention;

[0061] Figure 19 A timing diagram of a delay phase-locked loop circuit mislocking provided by an embodiment of the present invention;

[0062] Figure 20 A schematic structural diagram of another delay-locked loop circuit provided by an embodiment of the present invention;

[0063] Figure 21 A circuit diagram of a phase detection starting circuit provided by an embodiment of the present invention;

[0064] Figure 22 A schematic structural diagram of another delay-locked loop circuit provided by an embodiment of the present invention;

[0065] Figure 23 An operating timing diagram of a delay-locked loop circuit provided by an embodiment of the present invention;

[0066] Figure 24 Another working timing diagram of a delay-locked loop circuit provided by an embodiment of the present invention;

[0067] Figure 25 This is a working timing diagram of another delay locked loop circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0068] To make the objectives, technical solutions, and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings. It is apparent that the embodiments described are only some, not all, of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are intended to fall within the scope of protection of the present invention.

[0069] like Figure 1 As shown in the figure, it is a schematic diagram of the structure of the delay phase-locked loop circuit in the related art.Figure 1 As can be seen, the delay-locked loop circuit includes a phase detector (PD) 101, a charge pump (CP) 102, a loop filter (LPF) 103, a voltage-controlled delay line (VCDL) 104, and a delay buffer circuit 105, clkref is a reference clock signal, clk is a clock signal, and phase is a phase signal. <n-1>A last stage phase clock signal is generated for the voltage controlled delay line (VCDL) 104.

[0070] Figure 1 The delay-locked loop circuit operates as follows. The last stage phase clock signal clk <n-1>The phase detector is used to phase detect with the reference clock signal clkref to generate the phase detection signal up (charging switch signal) and down (discharging switch signal), which controls the voltage control signal Vctrl outputted by the charge pump (CP) 102 to control the charging and discharging of the filter capacitor in the loop filter (LPF) 103. By adjusting the size of the voltage control signal Vctrl, the size of the bias voltage Vcp and Vcn of the loop filter (LPF) 103 is controlled, so as to control the delay time of the voltage controlled delay line (VCDL) 104. When the last stage phase clock signal clk <n-1>After the delay of one period of the reference clock signal clkref and the constant holding, the whole delay-locked loop circuit enters a locked state.

[0071] As shown in Figure 2 FIG. 1, it is a circuit schematic diagram of a voltage-controlled delay line (VCDL) 104 in the delay-locked loop circuit, from which Figure 2 it can be seen that the voltage-controlled delay line (VCDL) 104 includes a plurality of serially connected inverting delay units, an input end of a first inverting delay unit is used for inputting the reference clock signal clkref, and an output end of each inverting delay unit is connected with a delay buffer circuit 105.

[0072] Among them, the inverting delay unit can be an inverter, and each inverter is controlled by bias voltages Vcp and Vcn.

[0073] As shown in Figure 3 FIG. 2, it is a circuit schematic diagram of the delay buffer circuit 105 in the delay-locked loop circuit, from which Figure 3 it can be seen that the delay buffer circuit 105 includes inverting units and buffers arranged at intervals, wherein an input end of each inverting unit in the delay buffer circuit 105 is connected with an output end of an inverting delay unit at an odd position in the voltage-controlled delay line (VCDL) 104, an input end of each buffer in the delay buffer circuit 105 is connected with an output end of an inverting delay unit at an even position in the voltage-controlled delay line (VCDL) 104, the inverting units in the delay buffer circuit 105 are used for outputting even-stage phase clock signals, such as a 0th-stage phase clock signal clk<0>, a 2nd-stage phase clock signal clk<2> and a 4th-stage phase clock signal clk<4>, and the buffers in the delay buffer circuit 105 are used for outputting odd-stage phase clock signals, such as a 1st-stage phase clock signal clk<1>, a 3rd-stage phase clock signal clk<3> and a 5th-stage phase clock signal clk<5>.

[0074] It should be noted that the inverting delay units at the odd positions in the voltage-controlled delay line (VCDL) 104 correspond to the inverting units in the delay buffer circuit 105 one by one, and the inverting delay units at the even positions in the voltage-controlled delay line (VCDL) 104 correspond to the buffers in the delay buffer circuit 105 one by one.

[0075] As shown in Figure 4 FIG. 3, it is a circuit schematic diagram of a phase detector (PD) 101 in the delay-locked loop circuit, from which Figure 4 As can be seen, the phase detection circuit (PD) 101 comprises a fifth D flip-flop DFF5, a sixth D flip-flop DFF6, a first buffer B1, a second buffer B2, a third buffer B3 and a NAND gate NA1, wherein the D input terminal of the fifth D flip-flop DFF5 is connected with the power supply terminal VDD, the clock terminal CK of the fifth D flip-flop DFF5 is used for inputting a reference clock signal clkref, the set terminal RN of the fifth D flip-flop DFF5 is connected with the set terminal RN of the sixth D flip-flop DFF6 and the output terminal of the third buffer B3, the Q output terminal of the fifth D flip-flop DFF5 is connected with the input terminal of the first buffer B1; the output terminal of the first buffer B1 and the first input terminal of the NAND gate NA1 are connected, and output a phase detection signal up; the D input terminal of the sixth D flip-flop DFF6 is connected with the power supply terminal VDD, the clock terminal CK of the sixth D flip-flop DFF6 is used for inputting a last stage phase clock signal clk <n-1>The Q output end of the sixth D flip-flop DFF6 is connected with the input end of the second buffer B2; the output end of the second buffer B2 is connected with the second input end of the NAND gate NA1, and outputs the judging signal down; the output end of the NAND gate NA1 is connected with the input end of the third buffer B3.

[0076] Figure 4 The working principle of the phase judging circuit is as follows: when the first rising edge of the reference clock signal clkref arrives first, the judging signal up is 1, and when the last phase clock signal clk <n-1>When the rising edge of the up signal arrives, the phase detection signal down is set to 1, at which time the reset end RN of the fifth D flip-flop DFF5 and the sixth D flip-flop DFF6 becomes 0, and the phase detection signals up and down are reset to 0 again.

[0077] It should be noted that the fifth D flip-flop DFF5 and the sixth D flip-flop DFF6 in the embodiment of the application are both D flip-flops with asynchronous reset.

[0078] For the delay-locked loop circuit in the related art, the following two errors can occur in the locking process thereof. As shown in FIG. 1, when the phase clock signal clk Figure 5 arrives at the phase detection circuit (PD) 101, the phase clock signal clk <n-1>the delay to the reference clock signal clkref is greater than 1.5 periods <n-1>the first rising edge of the phase clock signal clk will be aligned toward the rising edge of the reference clock signal clkref that is closest to it. In this case, the circuit locks after the first rising edge of the phase clock signal clk <n-1>This type of false locking, where the phase-locked loop locks to a signal that differs from the reference clock signal clkref by more than one cycle, is called harmonic locking.

[0079] If the range of the delay of the voltage controlled delay line (VCDL) 104 is smaller than the delay of the harmonic locking, the voltage control signal Vctrl eventually reaches a value that makes the voltage controlled delay line (VCDL) 104 delay the maximum, and the phase-locked loop circuit cannot lock. Similarly, when the phase clock signal clk <n-1>the delay to the reference clock signal clkref is less than 0.5 period of the phase clock signal clk <n-1>The first rising edge of the phase clock signal clk will be aligned to the first rising edge of the reference clock signal clkref as shown in Figure 6 In this case, the error lock result that reaches the lock time is called zero lock. At the same time, since the delay of the voltage controlled delay line (VCDL) 104 cannot be 0, the phase clock signal clk <n-1>The entire delay-locked loop circuit cannot be completely locked either.

[0080] The zero locking and harmonic locking mentioned above are both false locking conditions in the delay-locked loop circuit, and currently, a large cost is required to solve the false locking condition in the delay-locked loop circuit with multiple phase outputs.

[0081] Based on the above problems, an embodiment of the present application provides a delay-locked loop circuit, as shown in the figure, the circuit comprises a phase discrimination circuit (PD) 101, a charge pump (CP) 102, a loop filter (LPF) 103, a voltage-controlled delay line (VCDL) 104, a delay buffer circuit 105 and a phase detection circuit 106, wherein, Figure 7

[0082] The voltage-controlled delay line (VCDL) 104 is configured to delay the reference clock signal clkref and output a plurality of delay signals;

[0083] The delay buffer circuit 105 is configured to perform an inversion or buffering operation on each delay signal and output a plurality of phase clock signals;

[0084] The phase discrimination circuit 101 is configured to determine a phase difference between the reference clock signal clkref and the last-stage phase clock signal clk <n-1>Output phase detection signal;

[0085] The charge pump 102 is configured to charge and discharge the capacitor in the charge pump 102 according to the phase detection signal, and output a voltage control signal Vctrl;

[0086] A loop filter (LPF) 103 is used to filter the voltage control signal Vctrl and control the delay time of the voltage controlled delay chain (VCDL) 104;

[0087] The phase detection circuit 106 is used to connect the path between the power supply terminal and the loop filter capacitor in the loop filter 103 according to the previous stage phase clock signal of the intermediate stage before the first rising edge of the reference clock signal arrives, so as to charge the loop filter capacitor.

[0088] In the embodiment of the present invention, the phase detection circuit can charge the loop filter capacitor in the loop filter before the first rising edge of the reference clock signal arrives, that is, before the circuit operates. Therefore, the delay of the voltage-controlled delay chain can be minimized before the circuit operates, thereby avoiding harmonic lock. Since the embodiment of the present invention only uses one phase detection circuit to avoid harmonic lock of the circuit, compared with sampling the input clock signal and the other phase clock signals to avoid harmonic lock, it can reduce overhead.

[0089] Specifically, such as Figure 8 As shown, the phase detection circuit 106 in the embodiment of the present invention includes a control unit 801 and a conduction unit 802, wherein:

[0090] The control unit 801 is used to generate a clock signal according to the phase clock signal clk of the preceding stage of the intermediate stage before the first rising edge of the reference clock signal clkref arrives. <n 2-k>The output control unit 802 outputs a conduction control signal for turning on the output control unit 802, wherein k is an integer greater than or equal to 1 and less than n / 2, and (n / 2-k) is an odd number.

[0091] The conduction unit 802 is configured to, after receiving the conduction control signal, turn on a path between the power supply end VDD and the loop filter capacitor Cp to charge the loop filter capacitor Cp.

[0092] In an embodiment, as shown in Figure 9 The control unit 801 can include an OR gate OR1, a first D flip-flop DFF1, and a first inverter N1.

[0093] The first input end of the OR gate OR1 is configured to input a first pre-stage phase clock signal clk <n 2-p>The second input terminal of the OR gate OR1 is used to input the second pre-stage phase clock signal clk of the middle stage <n 2-j>an output terminal of the OR gate OR1 is connected with a D terminal of the first D flip-flop DFF1, wherein p and j are both integers greater than or equal to 1 and less than n / 2, p and j are not equal, and (n / 2-p) and (n / 2-j) are both odd numbers;

[0094] A CK terminal of the first D flip-flop DFF1 is used for inputting a reference clock signal clkref, a Q terminal of the first D flip-flop DFF1 is connected with an input terminal of the first inverter N1, and an output terminal of the first inverter N1 is used for outputting an on-off control signal VALID.

[0095] It should be noted that the first front-stage phase clock signal can be clk <n 2-2>, the second pre-stage behavior clock signal can be clk <n 2-4>.

[0096] In another embodiment, as shown in FIG. 8, the control unit 801 can further include a second D flip-flop DFF2, a third D flip-flop DFF3, an exclusive-OR gate XOR1, a second inverter N2, and an AND gate AND1. Figure 10

[0097] The D terminal of the second D flip-flop DFF2 is connected to the D terminal of the third D flip-flop DFF3, for inputting a second pre-stage phase clock signal clk <n 2-j>, the CK terminal of the second D flip-flop DFF2 is connected to the CK terminal of the third D flip-flop DFF3 for inputting the reference clock signal clkref, and the Q terminal of the second D flip-flop DFF2 is connected to the first input terminal of the NOR gate XOR1;

[0098] A Q terminal of the third D flip-flop DFF3 is connected to the second input terminal of the NOR gate XOR1;

[0099] An output terminal of the NOR gate XOR1 is connected to a second input terminal of the AND gate AND1;

[0100] An output terminal of the first inverter is connected to a first input terminal of an AND gate AND1;

[0101] The output terminal of the AND gate AND1 is used to output a conduction control signal VALID.

[0102] In another embodiment, Figure 11 As shown, the control unit 801 may include a fourth D flip-flop DFF4 and a third inverter N3;

[0103] The D terminal of the fourth D flip-flop DFF4 is used to input the third front-stage phase clock signal clk of the positive intermediate stage. <n 2-m>, the set end SN of the fourth D flip-flop is used for inputting the first enable signal en1, the CK end of the fourth D flip-flop DFF4 is used for inputting the reference clock signal clkref, and the Q end of the fourth D flip-flop DFF4 is connected with the input end of the third inverter N3, wherein m is an integer greater than or equal to 1 and less than n / 2, and (n / 2-m) is an odd number;

[0104] The output end of the third inverter N3 is used for outputting the turn-on control signal VALID.

[0105] In a specific implementation, m can be 2, that is, the third front-stage phase clock signal clk <n 2-2>.

[0106] The timing diagram of the first enable signal en1 in the embodiment of the application is shown in the figure. Figure 25 As shown, the first enable signal en1 jumps from low level to high level at the time of the first rising edge of the reference clock signal clkref, and then continuously outputs high level.

[0107] The fourth D flip-flop in the embodiment of the application is a D flip-flop with asynchronous setting. The D flip-flop with asynchronous setting can ensure that the on-off control signal VALID is set to 0 before the circuit starts to work, and the phase clock signal clk is directly set to the rising edge of the reference clock signal clkref. <n 2-2>The sampling also functions as phase detection.

[0108] It should be noted that the preceding phase clock signal for phase detection is not limited to clk <n 2-2>Only the phase of the phase clock signal is ensured to be ahead of the phase of the intermediate stage phase clock, and the number of the ahead phase should not be too much. Because too much ahead phase will lead to more difficult detection of harmonic locking condition, and even unable to detect. The phase clock signal of the front stage in the embodiment of the application is the phase clock signal output by the inverter in the delay buffer circuit 105.

[0109] As shown in Figure 12 、 Figure 13 and Figure 14 , the conducting unit 802 can include a switch tube G1.

[0110] The control end of the switch tube G1 is used for inputting a conducting control signal, the first end of the switch tube G1 is connected with the power supply end VDD, and the second end of the switch tube G1 is connected with one end of the loop filter capacitor Cp.

[0111] In the embodiment of the application, in order to avoid harmonic locking in the locking process, before the circuit starts to work, the circuit turns on the Pmos switch tube through the control signal VALID, so as to charge the loop filter capacitor Cp through VDD. After the voltage of the voltage control signal Vctrl is charged to the maximum value to make the delay of the voltage controlled delay chain minimum, the whole circuit is enabled. Thus, the circuit will increase from the minimum delay to the correct locking delay value in the locking process, thereby effectively avoiding harmonic locking.

[0112] For the voltage controlled delay chain whose delay is proportional to the voltage of the voltage control signal Vctrl, only the Pmos switch tube is replaced by an Nmos switch tube, and the conducting control signal VALID is inverted, and the core idea is to set the delay of the voltage controlled delay chain to be minimum before the circuit starts to work.

[0113] In the specific implementation, as shown in Figure 15 、 Figure 16 、 Figure 17 , the first counter CNT1 can also be connected between the control unit 801 and the conducting unit 802, and the first counter CNT1 is used for counting the reference clock signal clkref. After the first counter CNT1 reaches the count value, the conducting control signal VALID is output.

[0114] When the circuit works normally, the phase clock signal clk <n 2-2>The falling edge of a certain cycle is suddenly later than the rising edge of the reference clock signal clkref, so that the on control signal VALID directly outputs 0, and the voltage control signal Vctrl is pulled up, thereby destroying the normal locking state of the circuit. Figure 15 、 Figure 16 、 Figure 17 The first counter CNT1 in the phase detection circuit shown in the drawings can avoid this phenomenon, and the on control signal VALID is set to 0 after a certain period of counting, which indicates that the delay of the delay chain in this period is indeed too large, and the phase-locked loop circuit indeed has a false locking phenomenon, and the voltage control signal Vctrl is pulled up at this time, so that the phase-locked loop is re-locked.

[0115] The introduction of the counter in the embodiment of the application can ensure high reliability of detection, and the false locking prevention detection mechanism is not affected by the change of the clock frequency, so it can be applied to a wide frequency range of the phase-locked loop. At the same time, for a phase-locked loop circuit with a large number of phase outputs, the phase detection circuit of the application can also realize its normal function, greatly simplifying the design of the false locking prevention circuit when the number of phase outputs is large.

[0116] Figure 16 The phase detection circuit shown in the drawings has two functions. One is to set the on control signal VALID to 0 to turn on the PMOS switch tube before the circuit works. Taking the phase-locked loop circuit in the embodiment of the application as an example, a voltage-controlled delay chain based on an inverter with an enablement, when the circuit is not enabled, the output of each inverter in the voltage-controlled delay chain is set to 0, at this time, clk <n 2-2>and clk <n 2-4>At the same time, 1, since clk <n 2-2>and clk <n 2-4>The phase clock signal is outputted from the inverter, and the reference clock signal is outputted from the inverter Figure 9 At this time, X0 is inputted as 1, and X1 is set as 0 when the rising edge of the reference clock signal clkref comes; at the same time, the rising edge and the falling edge of the reference clock signal clkref are simultaneously applied to the phase clock signal clk <n 2-2>Sampling, the obtained X2 and X3 are both 1, and X4 outputs 0. In the embodiment of the present invention, the two-way logic circuit, namely Figure 9 In the circuit before the two input terminals of AND gate AND1, as long as one of the circuits works normally, X5 can be set to 0, thereby setting the conduction control signal VALID to 0, turning on the PMOS switch tube and charging the loop filter capacitor Cp.

[0117] The second is to be able to detect whether harmonic locking occurs in real time during and after the circuit is locked. Figure 18 As shown, when the circuit is locked normally, the phase clock signal clk <n 2-2>the first falling edge of X0 must precede the second rising edge of the reference clock signal clkref. When X0 is sampled with the rising edge of the reference clock signal clkref, X1 is set to 1, and the phase clock signal clk <n 2-2>Sampling is performed, the signals taken by X2 and X3 are not used, so that X4 is set to 1, and the output X5 is 1, so that when the control signal VALID is 1, it means that the circuit is normally locked. As shown in Figure 19 When the circuit is mislocked, the phase clock signal clk <n 2-2>The first falling edge of the first control signal X1 appears after the second rising edge of the reference clock signal clkref, at this time, X1 is set to 0, so that the output X5 is 1, the control signal VALID is set to 0, the PMOS switch is turned on to charge the loop filter capacitor Cp, the voltage control signal Vctrl is pulled up, and then the delay of the voltage-controlled delay chain is reduced, thereby effectively avoiding harmonic locking.

[0118] The delay-locked loop circuit provided by the embodiment of the present application can effectively avoid the harmonic locking problem that may occur in the locking process and after locking of the delay-locked loop. The structure of the phase detection circuit is independent of the specific structure of the main circuit of the delay-locked loop. For the voltage-controlled delay chain under different control modes, only slight modification of the circuit is needed to achieve the same function.

[0119] The phase detection circuit provided by the embodiment of the present application is realized by a digital logic circuit, and therefore has good process portability. For some voltage-controlled delay chains without enable control, a simpler phase detection circuit can be used to achieve the function of preventing false locking.

[0120] The delay-locked loop circuit provided by the embodiment of the present application, as shown in Figure 20 may further include a phase discrimination starting circuit 107.

[0121] The phase discrimination starting circuit 107 is used for starting the phase discrimination under the control of the second enable signal en2 and the reference clock signal clkref, and starting the phase discrimination of the last-stage phase clock signal clk <n-1>After the first rising edge of the reference clock signal clkref comes, the control phase detection circuit starts.

[0122] As shown in Figure 21 The phase detection start circuit 107 can include a second AND gate AND2, the first input end of the second AND gate AND2 is connected with the output end of the NAND gate NA1, the second input end of the second AND gate AND2 is used for inputting the second enable signal en2, and the output end of the second AND gate AND2 is connected with the third buffer B3.

[0123] As shown in Figure 23 The timing diagram of the second enable signal en2 provided by the embodiment of the present application is shown in the figure, the second enable signal en2 is converted from low level to high level at the time when the second rising edge of the reference clock signal clkref comes, and continuously outputs high level.

[0124] The embodiment of the present application adds the phase detection start circuit, when the second enable signal is enabled (en2 is 1), the START signal further generated by the first rising edge of the reference clock signal clkref enables the phase detector. Therefore, when the first rising edge of the reference clock signal clkref comes, the phase detector does not work, and when the last stage phase clock signal clk <n-1>After the rising edge of the reference clock signal clkref arrives, at this time the phase detector has been enabled by the second enable signal en2, so the phase detection signal down is set to 1, and when the second rising edge of the reference clock signal clkref arrives, the phase detection signal up is set to 1, and the first D flip-flop DFF1 and the second D flip-flop DFF2 are reset to 0 again, so the voltage control signal Vctrl is continuously discharged, so that the delay of the voltage controlled delay chain is continuously increased, until the last stage phase clock signal clk <n-1>The first rising edge of the first clock signal clk1 is aligned with the second rising edge of the reference clock signal clkref, so that the zero lock problem in the locking process is effectively avoided.

[0125] In a specific implementation, as shown in Figure 22 The delay-locked loop circuit further includes a second counter CNT2, a first input end of the second counter CNT2 is configured to input a second enable signal en2, a second input end of the second counter CNT2 is configured to input the reference clock signal clkref, and an output end of the second counter CNT2 is connected with a second input end of the second AND gate AND2.

[0126] Meanwhile, for a voltage-controlled delay chain with a large number of stages, when the circuit starts to work, due to the uncertain state of each delay unit, the phase clock signal clk <n-1>The phase relationship with the reference clock signal clkref may not be clear. Therefore, in order to ensure that the phase relationship between the two clock signals is correct when the phase detection starts, the present invention adds a counter CNT2, which counts the rising edges of the reference clock signal clkref. Figure 24 When the first rising edge of the reference clock signal clkref comes, the counter CNT2 starts counting. After counting a certain number of set cycles, the Start signal is set to 1 to enable the phase detection circuit, thus ensuring that the last phase clock signal clk <n-1>Completely follow the reference clock signal clkref variation.

[0127] The structure of the phase detection circuit proposed above is for the phase detection of the voltage-controlled delay chain whose delay decreases with the increase of the voltage control signal Vctrl. For the voltage-controlled delay chain structure whose delay increases with the increase of the voltage control signal Vctrl, only the up and down signals output by the phase detection circuit need to be exchanged to ensure the correct phase relationship of the phase detection. As for the counting period of the counter, the designer can flexibly select the length of the counting period according to the different voltage-controlled delay chain structures, or set the counting value as a programmable value. As long as the phase relationship of the phase detection clock is correct when the phase detection circuit starts the phase detection, the phase detection error caused by the incorrect initial phase relationship can be avoided.

[0128] The phase detection start circuit provided by the embodiments of the present application, in combination with the above phase detection circuit, can effectively avoid the two incorrect locking phenomena of zero locking and harmonic locking.

[0129] Those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application belong to the scope of the claims of the present application and the equivalent technologies thereof, the present application also intends to include these modifications and variations. < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> ​< / n> < / n> < / n> < / n> < / n> ​

Claims

1. A delay-locked loop circuit, characterized in that: include: Phase detection circuit, charge pump, loop filter, voltage-controlled delay chain, delay buffer circuit and phase detection circuit; The voltage-controlled delay chain is used to delay the reference clock signal and output multiple delayed signals; The delay buffer circuit is used to perform an inversion or buffering operation on each of the delayed signals to output multiple phase clock signals; The phase detection circuit is used to output a phase detection signal according to the reference clock signal and the last stage phase clock signal; The charge pump is used to charge and discharge the filter capacitor in the charge pump according to the phase detection signal, and output a voltage control signal; The loop filter is used to control the delay length of the voltage-controlled delay chain after filtering the voltage control signal; The phase detection circuit is configured to, before the first rising edge of the reference clock signal arrives, connect a path between the power supply terminal and the loop filter capacitor in the loop filter according to the preceding phase clock signal of the intermediate stage, so as to charge the loop filter capacitor; Wherein, the phase detection circuit includes a control unit and a conduction unit; The control unit is configured to output a conduction control signal for controlling the conduction unit to be turned on according to the previous-stage phase clock signal before the first rising edge of the reference clock signal arrives; The control unit includes an OR gate, a first D flip-flop, a first inverter, a second D flip-flop, a third D flip-flop, a NOR gate, a second inverter and an AND gate; The first input terminal of the OR gate is used to input the first previous stage phase clock signal of the positive intermediate stage, the second input terminal of the OR gate is used to input the second previous stage phase clock signal of the positive intermediate stage, and the output terminal of the OR gate is connected to the D terminal of the first D flip-flop, wherein the first previous stage phase clock signal and the second previous stage phase clock signal are different; The CK terminal of the first D flip-flop is used to input the reference clock signal, and the Q terminal of the first D flip-flop is connected to the input terminal of the first inverter; The D terminal of the second D flip-flop is connected to the D terminal of the third D flip-flop for inputting the second previous-stage phase clock signal, the CK terminal of the second D flip-flop is connected to the CK terminal of the third D flip-flop for inputting the reference clock signal, and the Q terminal of the second D flip-flop is connected to the first input terminal of the NOR gate; The Q terminal of the third D flip-flop is connected to the second input terminal of the NOR gate; The output terminal of the NOR gate is connected to the second input terminal of the AND gate; The output terminal of the first inverter is connected to the first input terminal of the AND gate; The output end of the AND gate is used to output the conduction control signal.

2. The circuit according to claim 1, wherein The control unit includes a fourth D flip-flop and a third inverter; A D terminal of a fourth D flip-flop is used to input the third previous stage phase clock signal of the positive intermediate stage, a set terminal of the fourth D flip-flop is used to input the first enable signal, a CK terminal of the fourth D flip-flop is used to input the reference clock signal, and a Q terminal of the fourth D flip-flop is connected to the input terminal of the third inverter; The output terminal of the third inverter is used to output the conduction control signal.

3. The circuit according to claim 1 or 2, characterized in that The conducting unit includes a switch tube; The control end of the switch tube is used to input the conduction control signal, the first end of the switch tube is connected to the power supply end, and the second end of the switch tube is connected to one end of the loop filter capacitor.

4. The circuit according to claim 1, wherein It also includes a phase detection starting circuit; The phase detection startup circuit is used to control the startup of the phase detection circuit after the first rising edge of the last-stage phase clock signal arrives under the control of the second enable signal and the reference clock signal.

5. The circuit according to claim 4, wherein The phase detection circuit includes a fifth D flip-flop, a sixth D flip-flop, a first buffer, a second buffer, a third buffer and a NAND gate; A D input terminal of a fifth D flip-flop is connected to the power supply terminal, a CK terminal of the fifth D flip-flop is used to input a reference clock signal, a set terminal of the fifth D flip-flop is connected to the set terminal of the sixth D flip-flop and the output terminal of the third buffer, and a Q output terminal of the fifth D flip-flop is connected to the input terminal of the first buffer; an output terminal of the first buffer is connected to the first input terminal of the NAND gate, and outputs a first phase detection signal; The D input terminal of the sixth D flip-flop is connected to the power supply terminal, the CK terminal of the sixth D flip-flop is used to input the last-stage phase clock signal, and the Q output terminal of the sixth D flip-flop is connected to the input terminal of the second buffer; the output terminal of the second buffer is connected to the second input terminal of the NAND gate and outputs a second phase detection signal; the output terminal of the NAND gate is connected to the input terminal of the third buffer; The phase detection startup circuit includes a second AND gate; The first input terminal of the second AND gate is connected to the output terminal of the NAND gate, the second input terminal of the second AND gate is used to input a second enable signal, and the output terminal of the second AND gate is connected to the third buffer.

6. A clock generation chip, characterized in that: The method comprises the delay locked loop circuit as claimed in any one of claims 1 to 5.

7. An electronic device, characterized in that: Comprising the clock generation chip as claimed in claim 6.

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