Method for producing a composite structure comprising a single-crystalline SiC thin layer on a SiC carrier substrate

Abstract

The invention relates to a method for manufacturing a composite structure comprising a thin layer made of single-crystal silicon carbide arranged on a carrier substrate made of silicon carbide, the method comprising: a) a step of providing a donor substrate made of single-crystal silicon carbide, b) a step of implanting light substance ions into the donor substrate to form a buried brittle plane, the buried brittle plane defining a thin layer between the buried brittle plane and the free surface of the donor substrate, c) a step of forming a crystalline carrier layer in succession, wherein n is greater than or equal to 2; the n crystalline carrier layers are stacked one after another on the donor substrate. The front side of the bottom is provided with a substrate and the carrier substrate is formed; the respective forming steps include: - performing direct liquid jet chemical vapor deposition at a temperature below 900°C to form a carrier layer, the carrier layer being formed of an at least partially amorphous SiC matrix and having a thickness of less than or equal to 200 microns; - performing a crystallization heat treatment on the carrier layer at a temperature less than or equal to 1000°C to form a crystalline carrier layer; d) a step of separating along the buried brittle plane, thereby forming a composite structure comprising a thin layer on the carrier substrate on the one hand and forming the rest of the donor substrate on the other hand.

Description

Background Art

[0002] Interest in silicon carbide (SiC) has increased significantly over the past few years as this semiconductor material can improve energy handling capabilities. SiC is increasingly being used to create innovative power devices to meet the needs of emerging areas of electronics, especially electric vehicles.

[0003] Compared to their traditional analogues made of silicon, power devices and integrated power systems based on single-crystal silicon carbide are able to manage higher power densities and do so with smaller active area sizes. In order to further limit the size of power devices on SiC, it is advantageous to manufacture the components vertically rather than laterally. To this end, vertical conduction between the electrode located on the front side of the SiC structure and the electrode located on the back side must be achieved by the structure.

[0004] However, single-crystal SiC substrates for the microelectronics industry are still expensive and difficult to supply in large sizes. Therefore, it is advantageous to utilize thin layer transfer solutions to produce composite structures, which usually include a single-crystal SiC thin layer on a cheaper carrier substrate. One well-known thin layer transfer solution is Smart Cut TM Process, which is based on the implantation of light ions and assembly by direct bonding. This process makes it possible, for example, to manufacture a composite structure comprising a thin layer made of c-SiC taken from a single-crystalline SiC (c-SiC) donor substrate, in direct contact with a carrier substrate made of polycrystalline SiC (p-SiC), allowing vertical conduction. However, it remains difficult to achieve high-quality direct bonding by molecular adhesion between two substrates made of c-SiC and p-SiC, because of the complexity of managing the surface state and roughness of the substrates.

[0005] Various methods derived from this process are also known in the prior art. For example, F. Mu et al. (ECS Transactions, 86 (5) 3-21, 2018) implemented direct bonding (SAB: "surface activated bonding") after activating the surface to be assembled by bombarding with argon: this treatment before bonding produces a very high density of side bonds, thereby promoting the formation of covalent bonds at the assembly interface, thereby generating high bonding energy. However, the disadvantage of this method is that an amorphous layer is produced on the surface of the single-crystalline SiC donor substrate, which has a negative impact on the vertical conduction between the thin layer made of c-SiC and the carrier substrate made of p-SiC.

[0006] Solutions to this problem have been proposed, notably in EP3168862, which involve implanting dopant species into the amorphous layer in order to restore its electrical properties. The main drawback of this approach is its complexity and, consequently, its cost.

[0007] Also known is US Pat. No. 8,436,363, which describes a process for producing a composite structure comprising a thin layer made of c-SiC arranged on a metal carrier substrate, the thermal expansion coefficient of which matches the thermal expansion coefficient of the thin layer. The production process comprises the following steps:

[0008] - forming a buried brittle plane in the c-SiC donor substrate, defining a thin layer between the buried brittle plane and the front side of the donor substrate;

[0009] - depositing a metal (e.g. tungsten or molybdenum) layer on the front side of the donor substrate to form a carrier substrate with sufficient thickness to act as a stiffener;

[0010] - Separation along the buried brittle plane, forming a composite structure comprising the metal carrier substrate and the thin layer made of c-SiC on the one hand and the remainder of the c-SiC donor substrate on the other hand.

[0011] However, this manufacturing process is incompatible when the material forming the carrier substrate is p-SiC which needs to be deposited at temperatures higher than 1200° C., the usual temperature for manufacturing p-SiC. In particular, at these high temperatures, the growth kinetics of the cavities present in the buried brittle planes are faster than those of the p-SiC layer and the thickness required for the strengthening effect is not reached before blistering begins to occur, which is associated with the deformation of the layer aligned with the cavities in the vertical direction.

[0012] Regardless of the layer transfer technique used, an additional problem arises, namely providing a composite structure comprising a thin c-SiC layer of extremely high quality, in particular without (or with a very low density of) extended defects which could easily affect the performance quality and reliability of power devices intended to be made on said thin layer.

[0013] Subject matter of the invention

[0014] The present invention relates to an alternative to the prior art and aims to completely or partially overcome the above-mentioned disadvantages. The present invention relates in particular to a method for manufacturing a composite structure comprising a high-quality thin layer made of c-SiC on a lower-quality carrier substrate made of SiC. Summary of the invention

[0015] The invention relates to a method for producing a composite structure comprising a thin layer made of single-crystalline silicon carbide arranged on a carrier substrate made of silicon carbide. The method comprises the following steps:

[0016] a) providing a donor substrate made of single-crystalline silicon carbide,

[0017] b) a step of implanting light species ions into a donor substrate to form a buried brittle plane defining a thin layer between the buried brittle plane and a free surface of the donor substrate,

[0018] c) forming n consecutive steps of a crystalline carrier layer, wherein n is greater than or equal to 2; n crystalline carrier layers are sequentially stacked on the front side of the donor substrate to form the carrier substrate; each forming step comprises:

[0019] - direct liquid jet chemical vapor deposition at a temperature below 900° C. to form a carrier layer formed of an at least partially amorphous SiC matrix and having a thickness less than or equal to 200 micrometers;

[0020] - subjecting the carrier layer to a crystallization heat treatment at a temperature of less than or equal to 1000° C. to form a crystallized carrier layer;

[0021] d) A step of separating along said buried fragile plane, thereby forming a composite structure comprising the thin layer on the carrier substrate on the one hand and the remainder of said donor substrate on the other hand.

[0022] According to other advantageous and non-limiting features of the invention taken alone or in any technically feasible combination:

[0023] The method comprises a step e) of mechanical and / or chemical treatment of the composite structure, the treatment being applied to the free face of the carrier substrate, the back face of the composite structure, and / or to the free face of the thin layer, the front face of the composite structure;

[0024] Step e) comprises simultaneously performing mechanical chemical polishing on the front and back sides of the composite structure;

[0025] Between step c) and step d), chemical etching, mechanical grinding and / or mechanochemical polishing are applied to the free face of the carrier substrate;

[0026] The thickness of each deposited support layer is less than or equal to 100 micrometers, or even less than 50 micrometers, or even less than 10 micrometers;

[0027] The deposition of step c) is carried out at a temperature ranging from 100° C. to 800° C. or even preferably from 200° C. to 600° C.;

[0028] The deposition in step c) is carried out at a pressure of 1 torr to 500 torr;

[0029] The precursor used in the deposition process of step c) is selected from polysilylethylene and disilabutane;

[0030] Step c) comprises n consecutive steps of forming a crystalline support layer, wherein n is 3 to several tens;

[0031] step a) comprises a step a') of providing an initial substrate made of single-crystalline silicon carbide, and a step a") of epitaxially growing a single-crystalline silicon carbide donor layer on the initial substrate to form a donor substrate, the donor layer having a lower crystal defect density than the initial substrate,

[0032] Step a') comprises forming a single crystal conversion layer on the initial substrate to convert basal plane dislocation defects of the initial substrate into edge dislocation defects;

[0033] The epitaxial growth step a″) is carried out at a temperature above 1200° C., preferably between 1500° C. and 1650° C.;

[0034] The separation step d) is carried out at a temperature greater than or equal to the crystallization heat treatment temperature of step c);

[0035] The method comprises the step of reprocessing the remainder of the donor substrate to reuse it as an initial substrate or as a donor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Other features and advantages of the present invention will become apparent from the following detailed description of the invention given with reference to the accompanying drawings, in which:

[0037] [ Figure 1 ] Figure 1 shows a composite structure made according to the manufacturing method of the present invention;

[0038] [ Figure 2a ]

[0039] [ Figure 2b ]

[0040] [Figure 2c(i)]

[0041] [Figure 2c(ii)]

[0042] [Figure 2c(iii)]

[0043] [Figure 2c(iv)]

[0044] [Figure 2c(v)]

[0045] [Figure 2c(vi)]

[0046] [ Figure 2d ]

[0047] [ Figure 2e ]

[0048] [ Figure 2f ] Figures 2a to 2fThe steps of the manufacturing method of the present invention are shown;

[0049] [ Figure 3a ]

[0050] [ Figure 3b ] Figure 3a and 3b The steps of the manufacturing method of the present invention are shown. DETAILED DESCRIPTION

[0051] In the description, the same reference numerals may be used for elements of the same type in the drawings. The figures are schematic and, for the sake of clarity, are not to scale. In particular, the thickness of the layers along the z-axis is not proportional to the lateral dimensions along the x- and y-axes; and the relative thickness of the layers relative to each other is not taken into account in the figures.

[0052] The invention relates to a method for producing a composite structure 1 comprising a thin layer 10 ( Figure 1 ). The carrier substrate 20 is advantageously polycrystalline ("p-SiC" will be used to refer to polycrystalline SiC).

[0053] The method first comprises a step a) of providing a donor substrate 111 made of single-crystalline silicon carbide. Throughout the rest of the description, "c-SiC" will be used to refer to single-crystalline silicon carbide.

[0054] The donor substrate 111 is preferably in the form of a wafer having a diameter of 100 mm, 150 mm or 200 mm, or even 300 mm or even 450 mm, and a thickness of typically 300 to 800 microns. It has a front side 11a and a back side 11b. The surface roughness of the front side 11a is advantageously chosen to be less than 1 nm Ra (average roughness), as measured by an atomic force microscope (AFM) within a scanning range of 20 microns x 20 microns.

[0055] According to an advantageous embodiment, step a) comprises a step a') of providing an initial substrate 11 made of single-crystalline silicon carbide. Then, the method comprises a step a'') of epitaxially growing a single-crystalline silicon carbide donor layer 110 on the initial substrate 11, thereby forming a donor substrate 111. Figure 2a The epitaxial growth step is performed so that the crystal defect density of the donor layer 110 is smaller than the crystal defect density of the initial substrate 11 .

[0056] For example, the initial substrate 11 made of c-SiC may be of 4H or 6H polytype, have an off-angle of less than 4.0°±0.5° relative to the <11-20> crystal axis, and have a threading dislocation (micropipe) density less than or equal to 5 / cm 2 , or even less than 1 / cm 2In the N (nitrogen) doped form, its resistivity is preferably 0.015 ohm·cm to 0.030 ohm·cm. Needless to say, the dopant may not be nitrogen, and the dopant may optionally be P-type. It may be selected to have a resistivity of typically less than or equal to 3000 / cm 2 The initial substrate 11 has a low basal plane dislocation (BPD) defect density. The BPD density is about 1500 / cm 2 The c-SiC substrates are reasonably available, which facilitates their supply.

[0057] Advantageously, the donor layer 110 (the c-SiC thin layer 10 from which the composite structure 1 will be formed at the end of the method of the invention) has excellent crystal quality to meet the specifications required for the vertical element intended to be made on said thin layer 10. This is because various extensional defects are present in the layers or substrates made of c-SiC. These extensional defects may affect the performance quality and reliability of the element. In particular, defects of the BPD type are fatal for bipolar elements because when the recombination energy of electron-hole pairs is available, Shockley stacking faults (or SSFs) extend from the dislocations. The extension of the SSF stacking faults in the active area of ​​the element leads to an increase in the through-state resistance of the element.

[0058] The c-SiC donor layer 110 is manufactured to have a relative humidity less than or equal to 1 / cm 2 BPD defect density.

[0059] To this end, the epitaxial growth step a″) is carried out at a temperature above 1200° C., preferably between 1500° C. and 1650° C. The precursors used are silane (SiH4), propane (C3H8) or ethylene (C2H4); the carrier gas can be hydrogen with or without argon.

[0060] The low content of BPD defects in the donor layer 110 is obtained by promoting the conversion of BPD defects present in the initial substrate 11 into edge dislocations (TEDs).

[0061] According to one specific embodiment, step a″) comprises forming a single-crystalline conversion layer 13, preferably made of c-SiC, in order to maximize the conversion of BPD defects of the initial substrate 11 into TED defects ( Figure 3a ). For this purpose, it is advantageous to select a low offcut angle close to 4° for the initial c-SiC substrate 11 to increase the in-situ etching performed before the epitaxial growth, thereby achieving a large growth rate (typically greater than 5 μm / h) and finally select the growth conditions of the single-crystalline conversion layer 13 so that the C / Si ratio in the precursor flow is close to 1.

[0062] Then, epitaxial growth of the donor layer 110 on the conversion layer 13 can be performed ( Figure 3bAccording to this specific embodiment, a BPD defect density less than or equal to 1 / cm 2 Or even less than 0.1 / cm 2 c-SiC donor layer 110. Moreover, at the end of the method of the invention, the probability of bipolar degradation (the probability of holes reaching the BPD / TED transition point) is negligible (<0.1%), and the single-crystalline conversion layer 13 is not intended to be transferred into the composite structure 1. Prior art techniques aimed at reducing bipolar degradation include introducing a composite layer (nitrogen doping more than 1) between the conversion layer and the active layer. E 18 atoms / cm 3 ). The layer may be 10 μm thick and greater than 5 E 18 / cm 3 At the expense of the concentration of the composite layer, the probability of the existence of holes is reduced to 0.1% relative to the base structure without the composite layer. In the present invention, since the single crystal conversion layer 13 is not transferred, the probability of holes reaching the nucleation point of bipolar degradation (BPD-TED conversion point or any BPD point) is at least less than 0.1%, and even close to 0%.

[0063] It should be noted that conventional cleaning or etching sequences aimed at eliminating all or part of the particulate metallic or organic contaminants or native oxide layer that may be present on the front side 11a of the initial substrate 11 may be performed before and / or after the epitaxial growth step a″).

[0064] Alternatively, the donor substrate 111 may be formed only from an initial substrate 11 having a low defect density, which is compatible with the specifications of the future thin layer 10; this layer is then removed from the donor substrate 111 as described below in a subsequent step of the method.

[0065] The manufacturing method of the present invention further comprises a step b): implanting light material ions into the donor substrate 111 (particularly when the donor layer 110 is present) to a predetermined depth representing the desired thickness of the thin layer 10. It should be noted that when the donor layer 110 is present, the depth will always remain less than the thickness of the donor layer 110. This implantation generates a buried brittle plane 12 in the donor substrate 111, which defines the thin layer 10 ( Figure 2b ).

[0066] The light material injected is preferably hydrogen, helium or both of them injected together. TM As is well known in the art, these light substances will form microcavities near a predetermined depth, distributed in a thin layer parallel to the free surface 11a of the donor substrate 111, ie parallel to the plane (x, y) in the figure. For simplicity, this thin layer is called a buried brittle plane 12.

[0067] The energy used to implant the light species is selected to reach a predetermined depth in the donor substrate 111 .

[0068] Typically, hydrogen ions will travel at energies between 10keV and 250keV and 5 E 16 / cm 2 to 1 E 17 / cm 2 A dose of 100 to 1500 nm is implanted to define a thin layer 10 with a thickness of about 100 to 1500 nm.

[0069] It should be noted that, before the ion implantation step, a protective layer may be deposited on the free surface of the donor substrate 111. For example, the protective layer may be composed of a material such as silicon oxide or silicon nitride.

[0070] The method of the invention then comprises n consecutive steps of forming a crystalline support layer 20 ″, where n is greater than or equal to 2. The number of consecutive formation steps may be greater than or equal to 3; it may generally be as high as several dozen.

[0071] N crystalline carrier layers 20" are arranged in sequence on the front side 11a of the donor substrate 111; they form the carrier substrate 20. In other words, the first crystalline carrier layer 20" is directly in contact with the front side 11a of the donor substrate 111, and then the second crystalline carrier layer 20" is in contact with the first crystalline carrier layer 20", and so on for the n crystalline carrier layers 20" (Figure 2c (i) to (vi)).

[0072] The various formation steps include direct liquid injection chemical vapor deposition (DLI-CVD) followed by a crystallization heat treatment of the deposited layer 20 ′.

[0073] The DLI-CVD deposition is carried out at a temperature below 900° C., preferably 100 to 800° C., 100 to 700° C. or even advantageously 200 to 600° C. The pressure in the deposition chamber is defined between 1 torr and 500 torr.

[0074] The DLI-CVD deposition technique provides a good yield between supplied material (precursors) and achieved deposition thickness without the use of chlorinated precursors, which limits cost and environmental constraints.

[0075] Preferably, DLI-CVD deposition involves a disilabutane precursor or a polysilylethylene precursor, either pure or diluted. Other precursors such as methyltrichlorosilane, ethylenetrichlorosilane, dichloromethylvinylsilane, tetraethylsilane, tetramethylsilane, diethylmethylsilane, bistrimethylsilylmethane or hexamethyldisilane may alternatively be used.

[0076] The DLI-CVD deposition technique is described in Guilhaume Boisselier's paper (2013, “ Pulsed liquid jet chemical vapor deposition of chrome, silicium and hafnium carbides (Pulsed liquid jet chemical vapor deposition of chromium, silicon and hafnium carbides) is used in applications where ceramic coatings are deposited onto parts to protect them during very high temperature processing, such as steel or alloy metal parts.

[0077] The Applicant has developed a DLI-CVD deposition for a completely different application, namely the formation of a carrier layer 20 ′ deposited on a c-SiC donor substrate 111 , in order to obtain, at the end of the manufacturing method, a composite structure 1 intended for use in the microelectronics field.

[0078] The deposited support layer 20' forms a SiC matrix comprising amorphous SiC, as well as reaction byproducts originating from the precursors used during deposition and formed from carbon chains. Furthermore, the SiC matrix may optionally include crystalline SiC grains.

[0079] Typically, the support layer 20' will have a thickness of less than or equal to 200 microns, less than or equal to 100 microns, less than or equal to 50 microns, less than or equal to 10 microns, or even less than or equal to a few microns. Note that the DLI-CVD technique can provide a deposition rate greater than or equal to 10 microns / hour, or even greater than 50 microns / hour, or even greater than 100 microns / hour.

[0080] The thickness of each of the deposited carrier layers 20' can be the same, but this is not essential. According to one option, the thickness of the n carrier layers 20' deposited successively increases; this can limit the detrimental effects of the differences in the thermal expansion coefficients of the layers present in the structure: the thinner carrier layer 20' deposited at the beginning is less constrained in the structure than a thick layer (especially during the crystallization heat treatment after deposition) and can change the thermal expansion coefficient to a moderate coefficient, which is more conducive to the subsequent deposition of thicker carrier layers 20'.

[0081] According to another option, the thickness of the n successively deposited support layers 20 ′ decreases continuously; this offers the advantage of gradually reducing the size of cracks generated during the crystallization heat treatment of the deposited layer 20 ′, which treatment will be described in detail later in the description.

[0082] Note that step c) is advantageously intended to define a non-insulating interface between the donor substrate 111 and the carrier substrate 20. In other words, step c) is performed so that the interface between the donor substrate 111 and the carrier substrate 20 in the final composite structure 1 is conductive: the goal is to have a specific resistance of the interface preferably less than 1 mohm·cm 2. Advantageously, in order to ensure the conductivity of the interface, the removal of the native oxide present on the free face 11a of the donor substrate 111 is carried out by HF (hydrofluoric acid) deoxidation via a wet or dry route. Alternatively, overdoping of at least the first deposited nanometers of the first carrier layer 20' can be carried out by introducing dopant substances during the DLI-CVD deposition process. It should be noted that, in general, dopant substances can be introduced (in various doses) during the n depositions of step c) according to the target doping level and conductivity of the carrier substrate 20.

[0083] It is also advantageous to subject the donor substrate 111 to a cleaning process before deoxidation and / or forming the first carrier layer 20 ′, in order to remove all or part of the particulate metal or organic contamination that may be present on its free face.

[0084] After the DLI-CVD deposition, step c) comprises subjecting the carrier layer 20' to a crystallization heat treatment at a temperature less than or equal to 1000°C to form a crystallized carrier layer 20". The temperature of the heat treatment may be, for example, 950°C or 900°C or 800°C. The annealing atmosphere may in particular comprise a gas such as argon, nitrogen, hydrogen, helium or a mixture of these gases.

[0085] This annealing has the effect of eliminating hydrogen from the carrier layer 20 ′ and causing the SiC matrix to crystallize in the form of polycrystalline SiC.

[0086] The crystallization heat treatment can be carried out using conventional furnaces for the simultaneous treatment of multiple structures (batch annealing). The typical duration of the treatment is therefore from a few minutes to a few hours.

[0087] Alternatively, the crystallization heat treatment can be performed in a rapid thermal processing (RTP) furnace. Typical annealing times are from a few seconds to a few minutes.

[0088] Finally, it is also conceivable to carry out a crystallization heat treatment in situ in the DLI deposition chamber, for a typical time of about a few minutes.

[0089] The relatively low thickness of the deposited carrier layer 20' allows for rapid crystallization, which prevents the thermal budget of the crystallization heat treatment from causing excessive growth of cavities in the buried brittle plane 12 of the donor substrate 111. For example, for a carrier layer 20' having a thickness of 10 microns, a crystallization heat treatment may be applied at 800°C for 10 minutes; such a thermal budget is not sufficient to exceed the critical density and size of the cavities present in the buried brittle plane 12 of the donor substrate 111 (blistering or spontaneous separation along the buried brittle plane 12).

[0090] It is important to note that crystallization of individual carrier layers 20' often results in cracks 2 in the crystallized carrier layer 20", affecting its mechanical and electrical qualities. This is why the method of the invention envisages successive steps for forming the crystallized carrier layer 20".

[0091] As can be seen in Fig. 2c(i), a first carrier layer 20' is deposited during a first DLI-CVD deposition on the donor substrate 111. The stack is then subjected to a first crystallization heat treatment, which converts the first carrier layer 20' into a first crystalline carrier layer 20" in the form of p-SiC and in which cracks 2 appear (Fig. 2c(ii)).

[0092] A second DLI-CVD deposition is then carried out on the free surface of the first crystalline carrier layer 20″ (Figure 2c (iii)), in particular in the crack 2: this results in the second surface carrier layer 20' and the crack 2' being filled with the same material as the second layer 20' (at least part of the amorphous SiC matrix). A second crystallization heat treatment is applied to the stack, which converts the second carrier layer 20' into a second crystalline carrier layer 20″ in the form of p-SiC and cracks 2 appear in the second crystalline layer 20″ (Figure 2c (iv)). The SiC matrix present in the crack 2″ of the first crystalline carrier layer 20″ is also crystallized in the form of p-SiC, which makes it possible to repair the initial surface crack 2 of the first layer 20″.

[0093] A third DLI-CVD deposition can then be carried out on the free surface of the second crystalline carrier layer 20″, in particular in the crack 2 that has appeared ( FIG. 2c (v)): this therefore fills the third carrier layer 20' and the crack 2' with the same material as the third layer 20'. The stack is subjected to a third crystallization heat treatment, which converts the third carrier layer 20' into a third crystalline carrier layer 20″ in the form of p-SiC and a crack 2 appears in the third crystalline layer 20″ ( FIG. 2c (vi)). The SiC matrix present in the crack 2' of the second crystalline carrier layer 20″ is also crystallized in the form of p-SiC, which makes it possible to repair the initial crack 2 in the second layer.

[0094] It should be noted that the n DLI-CVD depositions can be performed at different temperatures, just as is possible with the n crystallization annealing operations.

[0095] The method comprises at least two consecutive steps for forming a crystalline carrier layer 20″. By way of example, three of these steps are shown in FIGS. 2c(i) to (vi), but it is entirely conceivable that 2 to 10 or even dozens of consecutive deposition and crystallization steps are performed until a carrier substrate 20 formed by the superposition of crystalline carrier layers 20″ is obtained.

[0096] The deposition parameters and crystallization annealing parameters of step c) are determined so that the carrier substrate 20 has:

[0097] - good electrical conductivity, i.e. less than 0.03 ohm·cm, or even less than 0.01 ohm·cm,

[0098] - High thermal conductivity, i.e. greater than or equal to 150 W·m -1 ·K -1 , or even 200W·m -1 ·K -1 ,

[0099] - a coefficient of thermal expansion close to that of the thin layer 10, i.e. typically 3.8 at room temperature E -6 / K to 4.2 E -6 / K.

[0100] In order to obtain these characteristics, the carrier substrate 20 preferably has the following structural characteristics: polycrystalline structure, 3C SiC type grains, 111 orientation, with an average size of 1 to 50 μm in the main plane of the substrate, and N-type doping so that the final resistivity is less than or equal to 0.03 ohm·cm, or even less than or equal to 0.01 ohm·cm.

[0101] At the end of step c), the carrier substrate 20 has sufficient thickness for the subsequent separation step d) and advantageously has the desired thickness of the composite structure 1. The thickness of the carrier substrate 20 may thus be greater than or equal to 10 microns, 50 microns or even greater than or equal to 100 microns.

[0102] The stack 211 resulting from step c) comprises a carrier substrate 20 arranged on a donor substrate 111 .

[0103] The method of the invention then comprises a step d) of separation along the buried brittle plane 12, thereby forming the composite structure 1 on the one hand and the remaining part 111 ′ of the donor substrate on the other hand. Figure 2d ).

[0104] According to an advantageous embodiment, the separation step d) is carried out by applying a thermal treatment to the stack 211 at a separation temperature greater than or equal to the deposition and crystallization temperature of step c). In particular, the microcavities present in the buried brittle plane 12 follow the growth kinetics until the onset of a fracture wave that will propagate over the entire extent of the buried brittle plane 12 and cause the separation between the composite structure 1 and the rest of the initial substrate 111 '. In practice, the temperature can be between 950°C and 1200°C, preferably between 1000°C and 1200°C, depending on the implantation conditions of step b).

[0105] According to an alternative embodiment, the separation step d) is performed by applying a mechanical stress to the stack 211, optionally before the heat treatment to embrittle the buried brittle plane 12. For example, the stress can be applied by inserting a tool (e.g. a razor blade) close to the buried brittle plane 12. For example, the separation stress can be of the order of several GPa, preferably greater than 2 GPa.

[0106] According to another embodiment, the separation step d) can be performed during the last (nth) crystallization annealing of step c). In this case, it is optionally conceivable to perform at least one (n+1)th DLI-CVD deposition after the separation to further thicken the carrier substrate 20 and at least one (n+1)th crystallization annealing to form p-SiC.

[0107] After step d), a composite structure 1 is obtained, which comprises a thin layer 10 made of monocrystalline silicon carbide arranged on a carrier substrate 20 made of polycrystalline silicon carbide.

[0108] As known per se, at the end of separation step d), the free face 10a of the thin layer 10 of the composite structure 1 has a surface roughness of 5 to 100 nm RMS (measured with an atomic force microscope (AFM) within a scanning range of 20 micrometers x 20 micrometers).

[0109] It is therefore possible to envisage a step e) of mechanical and / or chemical treatment of the composite structure 1 in order to smooth the free surface 10a of the thin layer 10 and to correct the thickness uniformity of the composite structure 1 ( Figure 2e ).

[0110] Step e) may include mechanical chemical polishing (MCP) of the free surface 10a of the thin layer 10, typically removing about 50nm to 1000nm of material to obtain a final roughness of less than 0.5nm RMS or even less than 0.3nm (on an AFM field of view of 20×20μm). Step e) may also include chemical or plasma treatment (cleaning or etching), such as SC1 / SC2 type (standard cleaning 1, standard cleaning 2) and / or HF (hydrofluoric acid) and / or N2, Ar, CF4 and other plasma cleaning, to further improve the quality of the free surface 10a of the thin layer 10.

[0111] Furthermore, step e) may include mechanical chemical polishing (MCP) and / or chemical treatment (etching or cleaning) and / or mechanical treatment (grinding) of the back side 20b of the carrier substrate 20. This makes it possible to remove all or part of the residual cracks 2. Such treatment may also improve the thickness uniformity of the carrier substrate 20 and the roughness of its back side 20b. The roughness is expected to be less than 0.5 nm RMS (measured with an atomic force microscope (AFM) over a field of view of 20 microns x 20 microns) to manufacture vertical elements, for which at least one metal electrode will be present on the back side 20b of the composite substrate 1.

[0112] It should be noted that these treatments applied to the back side 20b of the carrier substrate 20 may optionally be applied just before the separation step d), i.e. before the front side 10a of the composite structure 1 is exposed, in order to limit its contamination, in particular during contaminating or restrictive treatments such as chemical etching or mechanical grinding.

[0113] The edges of the composite structure 1 may also be polished or ground during this step e) so that the shape of its rounded contour and the cut edge waste are compatible with the requirements of the microelectronic manufacturing process.

[0114] According to an advantageous embodiment, the mechanochemical treatment step e) comprises simultaneous polishing (MCP) of the front side 10a and the back side 20b of the composite structure 1, so as to smooth the structure 1 and improve its thickness uniformity. The polishing parameters of the front side and the back side can be different, and the smoothing of the c-SiC surface and the p-SiC surface generally requires different consumables. When the carrier substrate 20 is made of p-SiC, the mechanical element of polishing is particularly favorable to the back side 20b, so as to limit the preferential attack of the chemical components being polished at the grain connections. For example, polishing parameters such as rotation speed (polishing head and polishing plate), pressure, concentration and physical properties of abrasives (i.e. diamond nanoparticles with a diameter of about 10nm to 1μm) can be modified to highlight the mechanical elements.

[0115] Optionally, step e) is followed by a step e') of heat treatment at a temperature of 1000° C. to 1800° C. for about one hour to a maximum of several hours. The purpose of this step is to stabilize the composite structure 1 by repairing structural or surface defects still present in and / or on the thin layer 10 and, where appropriate, by evolving the crystalline configuration of the carrier substrate 20, so that the structure 1 is compatible with the high-temperature heat treatments subsequently required for the manufacture of components on the thin layer 10. Such a heat treatment may also have the advantage of restoring good electrical conductivity at the deposition interface of the layer that has formed the carrier substrate 20.

[0116] The method of the invention may comprise a second step f) of epitaxially growing a further layer 10' of single-crystalline silicon carbide on the thin layer 10 of the composite structure 1 Figure 2f ). Such a step is applied when the production of a component requires a working layer 100 of relatively large thickness (typically about 5 to 50 micrometers).

[0117] The temperature applied during this step f) may be chosen to be limited in order to limit the stresses induced in the working layer 100 (corresponding to the combination of the thin layer 10 and the further layer 10 ′) by the composite structure 1 .

[0118] Finally, the manufacturing method may include a step of reprocessing the remaining portion 111' of the donor substrate to reuse it as the initial substrate 11 or as the donor substrate 111. Such a reprocessing step is based on one or more treatments ( Figure 2d ), by surface or edge mechanochemical polishing, and / or by mechanical grinding, and / or by wet or dry chemical etching.

[0119] Preferably, the thickness of the donor layer 110 formed in step a″) is defined so that the remaining portion 111 ′ of the donor substrate 111 can be reused as the donor substrate 111 at least twice.

[0120] Preferably, when the conversion layer 13 is present, care will be taken to keep said layer intact, i.e. always keep a portion of the donor layer 10 on the rest 111 ' of the donor substrate. Thus, when this portion of the donor layer 10 is not sufficient to manufacture the composite structure 1, only the epitaxial growth step of the donor layer 110 is required, and not the steps preceding the growth of the conversion layer 13.

[0121] Example:

[0122] According to a non-limiting embodiment, the initial substrate 11 provided in step a′) of the manufacturing method is a wafer made of c-SiC of 4H polytype, oriented at 4.0°±0.5° relative to the <11-20> axis, with a diameter of 150 mm and a thickness of 350 μm.

[0123] Prior to step a″) of epitaxially growing the c-SiC donor layer 110 , a conventional RCA cleaning sequence (Standard Clean 1+Standard Clean 2) is performed on the initial substrate 11 , followed by Caro's acid (a mixture of sulfuric acid and hydrogen peroxide) and then HF (hydrofluoric acid).

[0124] Growth is performed in an epitaxial chamber at a temperature of 1650°C using precursors such as silane (SiH4) and propane (C3H8) or ethylene (C2H4) to produce a c-SiC donor layer 110 with a thickness of 30 μm (growth rate: 10 μm / h). The BPD defect density of the donor layer is about 1 / cm 2 .

[0125] Hydrogen ions with an energy of 150 keV and 6 E 16 H+ / cm 2 A dose of 100 nm is implanted through the free surface of the donor layer 110. Thus, a buried brittle plane 12 is produced in the initial substrate 11 at a depth of about 800 nm.

[0126] An RCA+Carrot acid cleaning process is performed on the donor substrate 111 to remove potential contaminants from the free surface of the donor layer 110 .

[0127] A first DLI-CVD deposition was performed on the donor layer 110 at a temperature of 650° C. using a disilabutane (DSB) precursor at a pressure of 50 Torr for 80 minutes to achieve a thickness of 140 microns for the first support layer 20 ′. Under these conditions, the support layer 20 ′ forms an amorphous SiC matrix including reaction byproducts originating from the deposited precursors.

[0128] The stack 211 is then subjected to a first crystallization annealing operation at 800° C. for less than 15 minutes in a neutral atmosphere of nitrogen or argon. The crystallization of the first p-SiC carrier layer 20 ′ leads to the appearance of cracks 2 .

[0129] Under the same conditions as the first deposition, a second DLI-CVD deposition is performed on the first crystalline carrier layer 20 ″ to a thickness of 140 microns. This deposition can also fill surface cracks in the first crystalline carrier layer 20 ″. The second carrier layer 20 ′ also forms an at least partially amorphous SiC matrix.

[0130] A second crystallization annealing operation similar to the first annealing operation is then carried out. Crystallization of the SiC matrix deposited in the crack 2″ makes it possible to repair the first crystallized support layer 20″. The second crystallized support layer 20″ is also formed of p-SiC and a crack 2 appears in this second layer 20″.

[0131] A third DLI-CVD deposition is performed on the second crystalline support layer 20 ″, followed by a third crystallization annealing operation, which is the same as the previous operation.

[0132] Finally, a fourth DLI-CVD deposition is performed on the third crystalline support layer 20 ″, followed by a fourth crystallization annealing operation, which is also the same as the previous operation.

[0133] It should be remembered that the various deposition and crystallization annealing operations can be carried out under completely different conditions from each other.

[0134] The fourth crystalline support layer 20 ″ is formed of p-SiC, and a crack 2 occurs in the fourth layer 20 ″.

[0135] The carrier substrate 20 formed by stacking four crystalline carrier layers 20 ″ has a thickness of about 560 μm.

[0136] The stack formed by the donor substrate 111 and the carrier substrate 20 is then subjected to an annealing at 1000° C. for 50 minutes. During said annealing, separation occurs at the level of the buried brittle plane 12. At the end of this separation step d), the composite structure 1 formed by the thin layer 10 and the carrier substrate 20 is separated from the remaining part 111 ′ of the donor substrate.

[0137] The back side of the carrier substrate 20 is ground to remove the region including the residual crack 2. To this end, a thickness of about 100 to 200 micrometers is removed from the back side of the carrier substrate 20.

[0138] One or more mechanochemical polishing operations are then carried out to restore the surface roughness of the thin layer 10 and the back side of the carrier substrate 20, followed by a conventional cleaning process.

[0139] It goes without saying that the invention is not limited to the described embodiments and examples, and implementation variations may be applied without departing from the scope of the invention defined by the claims.

Claims

1. A method for producing a composite structure (1), comprising a thin layer (10) made of single-crystalline silicon carbide arranged on a carrier substrate (20) made of silicon carbide, the method comprising: include: a) providing a substrate (111) made of single-crystal silicon carbide, b) a step of implanting light species ions into a donor substrate (111) to form a buried brittle plane (12), said buried brittle plane (12) defining a thin layer (10) between said buried brittle plane (12) and a free surface of said donor substrate (111), c) forming n consecutive steps of a crystalline carrier layer (20"), wherein n is greater than or equal to 2; n crystalline carrier layers (20") are sequentially stacked on the front side of the donor substrate (111) to form the carrier substrate (20); each forming step comprises: - performing direct liquid jet chemical vapor deposition at a temperature below 900° C. to form a carrier layer (20′), the carrier layer (20′) being formed of an at least partially amorphous SiC matrix and having a thickness less than or equal to 200 micrometers; - subjecting the carrier layer (20') to a crystallization heat treatment at a temperature less than or equal to 1000°C to form a crystallized carrier layer (20"); d) a step of separating along the buried fragile plane (12), thereby forming a composite structure (1) comprising the thin layer (10) on the carrier substrate (20) on the one hand and the remainder (111') of the donor substrate on the other hand.

2. The method of manufacturing according to the preceding claim, wherein include: e) a step of mechanically and / or chemically treating the composite structure (1), the treatment being applied to the free surface of the carrier substrate (20), the back surface of the composite structure (1), and / or to the free surface of the thin layer (10), the front surface of the composite structure (1).

3. The manufacturing method according to the preceding claim, in, Step e) comprises simultaneously performing mechanical chemical polishing on the front side and the back side of the composite structure (1).

4. The method of manufacturing according to any one of the preceding claims, in, Between step c) and step d), chemical etching, mechanical grinding and / or mechanochemical polishing are applied to the free face of the carrier substrate (20).

5. A method of production as claimed in any one of the preceding claims, in, The thickness of each deposited support layer (20') is less than or equal to 100 micrometers, or even less than 50 micrometers, or even less than 10 micrometers.

6. A method of production as claimed in any one of the preceding claims, in, The deposition in step c) is carried out at a temperature ranging from 100 to 800°C or even preferably from 200 to 600°C.

7. A method of production as claimed in any one of the preceding claims, in, The deposition in step c) is performed at a pressure of 1 to 500 torr.

8. A method of production as claimed in any one of the preceding claims, in, The precursor used during the deposition in step c) is selected from polysilylethylene and disilabutane.

9. The method of manufacturing as claimed in any one of the preceding claims, in, Step c) comprises n consecutive steps of forming a crystalline support layer (20"), wherein n is 3 to several tens.

10. The method of manufacturing as claimed in any one of the preceding claims, in, Step a) comprises: a') a step of providing an initial substrate (11) made of single-crystalline silicon carbide, a”) a step of epitaxially growing a single-crystal silicon carbide donor layer (110) on an initial substrate (11) to form the donor substrate (111), wherein the crystal defect density of the donor layer (110) is lower than that of the initial substrate (11).

11. The manufacturing method according to the preceding claim, in, Step a') comprises forming a single crystal conversion layer (13) on the initial substrate (11) to convert basal plane dislocation defects of the initial substrate (11) into edge dislocation defects.

12. The method of manufacturing as claimed in any one of the preceding claims, in, The epitaxial growth step a") is carried out at a temperature above 1200°C, preferably between 1500°C and 1650°C.

13. A method of production as claimed in any one of the preceding claims, in, Said separation step d) is carried out at a temperature greater than or equal to the crystallization heat treatment temperature of step c).

14. The manufacturing method according to any of the preceding claims, comprising the step of reprocessing the remaining part (111') of the donor substrate to reuse it as an initial substrate or as a donor substrate.

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