Micro voltage difference quantization circuit with non-uniformity calibration function and sensing device

Abstract

The application provides a micro voltage difference quantization circuit with in-band non-uniformity calibration function and a sensing device, and relates to the field of integrated circuits. The application comprises the following steps: a calibration unit acquires external calibration data, and combines a differential transconductance unit to convert the external calibration data into refined reference voltage; the differential transconductance unit receives a to-be-tested voltage from a quantum well, and generates two differential output currents based on the refined reference voltage and the to-be-tested voltage; an oscillation unit receives the two differential output currents, generates two pulse outputs, and a counting and reading unit counts the two pulse outputs, obtains a quantization result and outputs the quantization result. The micro voltage difference quantization circuit can adapt to a quantum well detection device, suppresses the nonlinearity and inter-pixel non-uniformity of the quantum well detection device, increases the hardware cost as little as possible, and makes the advantages of the quantum well detection device in an infrared imaging system fully play.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, in particular to a micro-voltage difference quantization circuit with on-chip non-uniformity calibration function and a sensing device. BACKGROUND

[0002] Infrared imaging systems have high reliability, strong anti-interference ability and other characteristics, and are widely used in military, medical, aerospace, astronomy, industrial control and other key fields. In recent years, they are also increasingly used in civilian areas. An infrared imaging system is usually divided into a detector and a readout circuit. The detector can convert light signals of a specific wavelength into electrical signals according to the radiation intensity, and the detector based on the quantum well principle has the advantages of strong wavelength detection specificity, small dark current and high signal-to-noise ratio. The readout circuit is in the form of an integrated chip, which together with the detector forms a pixel array, efficiently and accurately quantizes the electrical signals transmitted by each detector, and finally outputs a digital code stream as a readable signal that can be used by a computer.

[0003] However, the working principle of the quantum well determines that the photoelectric current is relatively weak when triggered, and the response characteristic peak of the infrared light wavelength is relatively narrow, which brings strong wavelength detection specificity and also makes the overall nonlinearity high. If a general pixel-level readout structure is used in an infrared imaging system of a quantum well device, the difference between different pixels will be highlighted, such as process fluctuation, surrounding electrical environment, etc. In addition, the nonlinearity of the quantum well detector itself will cause obvious non-uniformity between different imaging areas in the entire system, introduce fixed pattern noise, affect the imaging quality, and make the advantages of the quantum well device unable to be fully utilized.

[0004] Therefore, there is an urgent need for an improved pixel structure that can adapt to quantum well detector devices, suppress the nonlinearity of the device and the non-uniformity between pixels while increasing the hardware cost as little as possible, and make the advantages of the quantum well detector device in the infrared imaging system fully play out. SUMMARY

[0005] Based on the above problems, the present application is proposed to provide a micro-voltage difference quantization circuit with on-chip non-uniformity calibration function and a sensing device to overcome the above problems or at least partially solve the above problems.

[0006] The first aspect of the embodiment of the present application provides a micro-voltage difference quantization circuit with non-uniformity calibration function, which comprises a calibration unit, a differential transconductance unit, an oscillation unit and a counting readout unit.

[0007] The calibration unit obtains external calibration data, and converts the external calibration data into a refined reference voltage in combination with the differential transconductance unit.

[0008] The differential transconductance unit receives the voltage to be measured from the quantum well, and generates two differential output currents based on the refined reference voltage and the voltage to be measured, which are then output to the oscillation unit.

[0009] The oscillation unit receives two differential output currents, generates two pulse outputs, and transmits them to the counting and reading unit.

[0010] The counting and reading unit counts the two pulse outputs, obtains the quantization result, and outputs the quantization result.

[0011] Optionally, the calibration unit includes: a calibration data storage device and a calibration data digital-to-analog converter;

[0012] The calibration data memory is implemented in the form of an n+k bit D latch, which acquires and fixes the external calibration data during the preparation phase before each working cycle.

[0013] The calibration data storage will store the k-bit data D from the external calibration data. n+1 ~D n+k The data is sent to the calibration data digital-to-analog converter, and the n-bit data D1 to D2 in the external calibration data are converted into n bits. n Send to the differential transconductance unit;

[0014] The calibration data digital-to-analog converter is based on the k-bit data D. n+1 ~D n+k Two bias voltages are generated and sent to the differential transconductance unit.

[0015] Optionally, the calibration data digital-to-analog converter consists of a switch array;

[0016] The k-bit data D n+1 ~D n+k Using the aforementioned switch array, in 2 k +1 uniformly distributed voltages are selected from two adjacent voltages as the two bias voltages, which are: high bias voltage and low bias voltage;

[0017] Both the high bias voltage and the low bias voltage are sent to the differential transconductance unit.

[0018] Optionally, the differential transconductance unit is located in the n-bit data D1 to D2. n Under the control of [the system], the high bias voltage and the low bias voltage are subjected to 2 [conditions / effects]. n The data is divided into equal parts, and the external calibration data is ultimately converted into the refined reference voltage.

[0019] The values ​​of n and k can be varied according to actual needs.

[0020] Optionally, the differential transconductance unit comprises a plurality of input pair tubes, the plurality of input pair tubes are divided into two paths, each of the input pair tubes is composed of transistors with the same size, and the multiplication factors are different;

[0021] The gate end of the first path input pair tube receives the to-be-tested voltage, and the multiplication factor of the first path input pair tube is 2 n ;

[0022] The voltage value received by the gate end of the second path input pair tube is determined by the n-bit data D1-D n , and the multiplication factor of the second path input pair tube is divided into 1, 1, 2, …, 2 according to the binary code weight n-1 .

[0023] Optionally, the source end of the first path input pair tube is connected to a fixed current source, and the drain end outputs a first differential output current of the two differential output currents;

[0024] In the second path input pair tube, the source end of each input pair tube is also connected to the fixed current source, and the drain end of each input pair tube collectively outputs a second differential output current of the two differential output currents;

[0025] The gate end of the first input pair tube in the second path input pair tube receives the low bias voltage, and the multiplication factor of the first input pair tube is 1;

[0026] The gate end of each input pair tube in the second path input pair tube, except the first input pair tube, receives the high bias voltage through a first switch and receives the low bias voltage through a second switch, wherein if the multiplication factor of an input pair tube is 1, the first switch and the second switch corresponding to the gate end of the input pair tube are controlled by D1 in the n-bit data D1-D n , if the multiplication factor of an input pair tube is 2, the first switch and the second switch corresponding to the gate end of the input pair tube are controlled by D2 in the n-bit data D1-D n , if the multiplication factor of an input pair tube is 2 n-1 , the first switch and the second switch corresponding to the gate end of the input pair tube are controlled by D n in the n-bit data D1-D n .

[0027] Optionally, the oscillation unit comprises two oscillation circuits and two waveform shaping modules;

[0028] The first oscillation circuit in the two oscillation circuits receives the first differential output current, and oscillation generates a first path pulse output, which is transmitted to the counting and reading unit after being processed by a first waveform shaping module in the two waveform shaping modules;

[0029] The second oscillation circuit of the two oscillation circuits receives the second differential output current, and oscillation generates a second pulse output, which is transmitted to the counting readout unit after being processed by a second waveform shaping module of the two waveform shaping modules.

[0030] The oscillation circuit comprises a plurality of cascaded same inverters, a common-gate P-type transistor, an inverted wide-length ratio N-type transistor, and an N-type transistor with minimum size.

[0031] Optionally, for any oscillation circuit, the oscillation frequency f is approximately proportional to I in / C total wherein I in represents the magnitude of the first differential output current or the second differential output current, C total represents the total gate capacitance of the multi-stage inverter.

[0032] The counting readout unit counts any pulse output, and the corresponding counting result is proportional to T / f, wherein T represents a preset oscillation duration.

[0033] Optionally, if I0 represents the differential output current injected into each oscillation circuit in the balanced state, and ΔI represents the differential current value, then the differential counting result is proportional to that is, When the differential current value ΔI is much smaller than the magnitude of the balanced current I0, the second term in the denominator is a second-order small quantity, and is ignored.

[0034] G m represents the transconductance value of the differential transconductance unit, and ΔV represents the difference between the to-be-measured voltage and the reference voltage, then ΔI=G m ΔV, and the complete expression of the differential counting result is:

[0035]

[0036] wherein K is a determined proportional coefficient, that is, the differential counting result proportionally reflects the difference between the to-be-measured voltage and the reference voltage.

[0037] The second aspect of the embodiment of the present application provides a sensing device, which comprises a quantum well detector and a micro voltage difference quantization circuit as any one of the first aspect.

[0038] The micro voltage difference quantization circuit with non-uniformity calibration function provided by the application comprises a calibration unit, a differential transconductance unit and an oscillation unit.

[0039] The working current of the differential transconductance unit is a fixed value current, and the difference between the two input voltages will cause the current to be non-balancedly distributed on the two differential paths, thereby forming the differential output current of the two output terminals; the size and final layout of each transistor in the differential transconductance unit are carefully designed, which minimizes the introduced noise and has good matching, so that the differential transconductance unit has a relatively stable transconductance value within a proper input range, and the conversion from the voltage difference to the current difference is realized.

[0040] The foregoing calibration process ensures that the reference voltage is as close as possible to the measured voltage under the consideration of various deviations; and due to the high impedance characteristic of the quantum well detection device, the fluctuation of the measured voltage is usually small (the peak-to-peak value of the fluctuation is within 3% of the measured voltage value), which causes each pixel to work in a state close to the balance point, thereby effectively suppressing the nonlinearity of the quantum well detection device. At the same time, this also ensures that the input range of the differential transconductance unit is appropriate, further ensuring the accuracy of the conversion process.

[0041] The two current output terminals of the differential transconductance unit are connected to the oscillation unit, and the differential output current with low noise and high linearity obtained is injected into the oscillation unit to make it oscillate at different frequencies; the oscillation waveform of the oscillation unit is connected to the clock terminals of two counters in the counting readout unit after shaping. The purpose of shaping is to reduce the rise and fall time of the oscillation waveform, thereby avoiding unnecessary through current and additional power consumption for subsequent digital circuits such as counters as much as possible.

[0042] The difference between the results of the two counters within a fixed length of time, i.e. the difference between the oscillation cycle numbers of the two oscillation circuits, reflects the difference between the oscillation frequencies of the two oscillation circuits, and in turn reflects the sizes of the foregoing differential current, differential voltage and measured voltage value, and finally establishes a relationship with the intensity of the optical signal received by the quantum well detection device, thereby completing the image quantization function. The data terminal of the counting readout unit is connected to the readout structure to output quantization data in the form of binary code to the outside of the pixel, and after the difference is taken, the final data can be read and used by a data processor such as a computer. The micro voltage difference quantization circuit of the application can adapt to the quantum well detection device, suppress the nonlinearity of the quantum well detection device and the non-uniformity between pixels while increasing the hardware cost as little as possible, and make the advantages of the quantum well detection device in the infrared imaging system fully play out. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments of the present application will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0044] Figure 1 is a preferred structure diagram of a micro-voltage differential quantization with non-uniformity calibration function in an embodiment of the present application;

[0045] Figure 2 is a preferred structure diagram of a differential transconductance unit G m in an embodiment of the present application;

[0046] Figure 3 is a preferred structure diagram of any oscillation circuit and waveform shaping module in an oscillation unit in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are one embodiment of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without any creative effort belong to the scope of protection of the present application.

[0048] The micro-voltage differential quantization circuit with non-uniformity calibration function in the embodiments of the present application comprises a calibration unit, a differential transconductance unit, an oscillation unit and a counting and reading unit. The calibration unit obtains external calibration data and converts the external calibration data into refined reference voltage in combination with the differential transconductance unit. The differential transconductance unit receives a to-be-measured voltage from a quantum well and generates two differential output currents based on the refined reference voltage and the to-be-measured voltage, which are output to the oscillation unit.

[0049] The oscillation unit receives the two differential output currents, generates two pulse outputs, and transmits them to the counting and reading unit. The counting and reading unit counts the two pulse outputs, obtains a quantization result and outputs the quantization result.

[0050] Specifically, the calibration unit comprises a calibration data memory and a calibration data digital-to-analog converter. The external calibration data is taken as D1-D n+k for example. The calibration data memory is implemented in the form of an n+k-bit D latch, and the external calibration data is obtained and fixed in the preparation stage before each working period.

[0051] The calibration data memory obtains k-bit data Dn+1 ~D n+k The data is sent to the calibration data digital-to-analog converter, specifically the higher k bits of the external calibration data. Simultaneously, the calibration data memory stores the n bits of data D1 to D2 from the external calibration data. n Send to the differential transconductance unit, that is, send the lower n bits of data in the external calibration data to the differential transconductance unit.

[0052] The calibration data digital-to-analog converter is based on k-bit data D n+1 ~D n+k Two bias voltages are generated and sent to the differential transconductance unit. The calibration data digital-to-analog converter can consist of a switch array, with k-bit data D. n+1 ~D n+k Using a switch array, in 2 k +1 From a uniformly distributed voltage, two adjacent voltages are selected as the two bias voltages: a high bias voltage and a low bias voltage. It is understandable that the calibration data digital-to-analog converter can be composed of other methods, as long as it functionally meets the requirement of k-bit data D... n+1 ~D n+k In 2 k Choose two adjacent voltages from a uniformly distributed voltage range as two bias voltages. Then send both the high bias voltage and the low bias voltage to the differential transconductance unit.

[0053] Differential transconductance unit in n-bit data D1~D n Under the control of the high bias voltage and the low bias voltage, 2 n The data is divided equally, and the external calibration data is ultimately converted into a refined reference voltage; the values ​​of n and k can be varied according to actual needs. For example, they can be 2, 3, or 4, thus achieving 4-8 bit non-uniform calibration.

[0054] The differential transconductance unit in this embodiment of the invention includes: multiple input transistor pairs, which are divided into two paths. Each input transistor pair is composed of transistors of the same size, but with different multipliers. The gate of the first input transistor pair receives the voltage to be measured from the quantum well detector, and the multiplier of the first input transistor pair is 2. n The voltage value received at the gate of the second input pair is determined by n-bit data D1 to D2. n It is decided that the multiplier of the second input transistor is divided into 1, 1, 2...2 according to the binary code weight. n-1 For example, if n = k = 3, then the number of second input pairs is 4, and the multipliers of the second input pairs are 1, 1, 2, and 4 respectively, while the multiplier of the first input pair is 8.

[0055] In the specific connection structure, the source end of the first input pair of transistors is connected to a fixed current source, and the drain end outputs a first differential output current of the two differential output currents; the source end of each input pair of transistors is also connected to the fixed current source, and the drain end of each input pair of transistors collectively outputs a second differential output current of the two differential output currents.

[0056] The gate end of the first input pair of transistors in the second input pair of transistors receives a low bias voltage, and the multiplication factor of the first input pair of transistors is 1; the gate end of each input pair of transistors in the second input pair of transistors, except the first input pair of transistors, receives a high bias voltage through the first switch and a low bias voltage through the second switch. Among the gate ends of all the input pairs of transistors except the first input pair of transistors, if the multiplication factor of an input pair of transistors is 1, the first switch and the second switch corresponding to the gate end of the input pair of transistors are controlled by the n-bit data D1~D n , and if the multiplication factor of an input pair of transistors is 2, the first switch and the second switch corresponding to the gate end of the input pair of transistors are controlled by the n-bit data D1~D n , and so on. n-1 n n .

[0057] The structure of the differential transconductance unit is equivalent to a transistor with a multiplication factor of 2 n , and the gate end is connected to the reference voltage to be generated by the low n-bit calibration data D1~D n , so that the entire differential transconductance unit can easily complete the low n-bit conversion of the calibration data while realizing the conversion of the differential voltage (i.e. the difference between the to-be-measured voltage and the reference voltage) to the differential output current.

[0058] The working current of the differential transconductance unit is fixed, and the difference between the two input voltages will cause the current to be non-uniformly distributed in the two differential paths, thereby forming the differential output currents of the two output ends; the size and final layout of each transistor in the differential transconductance unit are carefully designed to minimize the introduced noise while having good matching, so that the differential transconductance unit has a relatively stable transconductance value within a proper input range, and realizes the proportional conversion of the voltage difference to the current difference.

[0059] ​​The foregoing calibration process ensures that the reference voltage is as close as possible to the to-be-measured voltage in consideration of various deviations; and due to the high impedance characteristics of the quantum well detector, the to-be-measured voltage usually has a small fluctuation (the peak-to-peak value of the fluctuation is within 3% of the to-be-measured voltage value), which enables each pixel to work in a state close to the balance point, thereby effectively suppressing the nonlinearity of the quantum well detector. Meanwhile, this also ensures that the input range of the differential transconductance unit is appropriate, further ensuring the accuracy of the conversion process.

[0060] In the embodiment of the present application, the oscillation unit comprises two oscillation circuits and two waveform shaping modules; the first oscillation circuit in the two oscillation circuits receives the first differential output current, and oscillation generates a first pulse output; the first pulse output is transmitted to the counting readout unit after being processed by the first waveform shaping module in the two waveform shaping modules; the second oscillation circuit in the two oscillation circuits receives the second differential output current, and oscillation generates a second pulse output; the second pulse output is transmitted to the counting readout unit after being processed by the second waveform shaping module in the two waveform shaping modules. The purpose of shaping is to reduce the rise and fall time of the oscillation waveform, thereby avoiding unnecessary through current and additional power consumption for subsequent digital circuits such as counters as much as possible.

[0061] For any oscillation circuit, it comprises a plurality of cascaded same inverters, a P-type transistor in common gate connection, an N-type transistor with a reversed width-length ratio, and an N-type transistor with a minimum size.

[0062] Based on the above structure, it is known that for any oscillation circuit, the oscillation frequency f is approximately proportional to I in / C total wherein I in represents the size of the first differential output current or the second differential output current, C total represents the total gate stage capacitance of the multi-stage inverter; the counting readout unit counts any pulse output, and the corresponding counting result is proportional to T / f, wherein T represents a preset oscillation duration.

[0063] If I0 represents the differential output current size injected into each oscillation circuit in the balance state (i.e. the differential voltage value is 0), and ΔI represents the differential current value, then the differential counting result is proportional to i.e. When the differential current value ΔI is much smaller than the balance current size I0, the second term in the denominator is a second-order small quantity, and can be ignored; G m represents the transconductance value of the differential transconductance unit, and ΔV represents the difference between the to-be-measured voltage and the reference voltage, then ΔI=G m ΔV, and the complete expression of the differential counting result is:

[0064]

[0065] Wherein, K is a certain proportion coefficient, that is, the difference counting result reflects the difference between the to-be-measured voltage and the reference voltage in proportion. And the linearity and accuracy of this quantization process can be guaranteed especially in the case of small input range, which is consistent with the feature that the signal change amount occupies a very small proportion.

[0066] In a fixed length of time, the difference between the two counter results, that is, the difference between the number of oscillation periods of the two oscillation circuits, reflects the difference between the oscillation frequencies of the two oscillation circuits, thereby reflecting the size of the aforementioned differential current, differential voltage and to-be-measured voltage value in turn, and finally establishing a connection with the light signal intensity received by the quantum well detection device to complete the quantization function of the image. The data end of the counting readout unit is connected to the readout structure to output quantization data in the form of binary code to the outside of the pixel, which can be read and used by a computer or other data processor after subtraction.

[0067] Since the interface of the quantum well detector is connected to one input end of the differential transconductance unit, from the perspective of the electrical equivalent model, when receiving infrared radiation of a specific wavelength from the outside world, the impedance of the quantum well detector will change slightly according to the radiation intensity, thereby causing a slight change in the interface voltage value, which is then quantized by the small voltage difference quantization circuit described in the present application to obtain the final quantization result. The nonlinearity of the quantum well device and the non-uniformity in the pixel array can be well suppressed; at the same time, the low-noise characteristic of the small voltage difference quantization circuit of the present application will well adapt to the characteristics of the quantum well detection device that detects specificity but has a small signal amount, so that the quantum well detector can fully exert its unique advantages when applied in an infrared imaging system.

[0068] In order to more clearly illustrate the small voltage difference quantization circuit with the in-situ non-uniformity calibration function described above, the structure and working principle of the small voltage difference quantization circuit with the in-situ non-uniformity calibration function will be described below by taking a specific circuit structure as an example.

[0069] Referring to Figure 1 , a preferred structure schematic diagram of the small voltage difference quantization circuit with the in-situ non-uniformity calibration function is shown, which specifically comprises: a quantum well detector interface J1, a calibration data storage n+k bit D latch, a calibration data digital-to-analog converter DAC, a differential transconductance unit G m , an oscillation circuit CCO1, an oscillation circuit CCO2, a counter Counter1, a counter Counter2, and a pixel-out subtractor SR.

[0070] The n+k bit calibration data storage stores k bit data D n+1 ~D n+kSend to the calibration data digital-to-analog converter (DAC), and convert n bits of data D1 to D from the external calibration data. n Send to differential transconductance unit G m .

[0071] The calibration data digital-to-analog converter (DAC) utilizes a switch array in 2 k +1 From a uniformly distributed voltage, select two adjacent voltages as two bias voltages, the two bias voltages being: high bias voltage V top and low bias V bot Differential transconductance unit G m In n-bit data D1~D n Under the control of V, further high bias voltage V top and low bias V bot Perform 2 n Divide into equal parts, and finally divide the external calibration data D1 to D2. n+k The voltage is converted into a refined reference voltage. Then, based on the refined reference voltage and the voltage to be measured, the first differential output current I1 and the second differential output current I2 are generated and then output to the oscillation circuits CCO1 and CCO2, respectively. After the oscillation period is counted by counters Counter1 and Counter2, the voltage is then transmitted to the external pixel subtractor SR for calculation to obtain the quantization result.

[0072] Figure 2 A preferred differential transconductance unit G is shown in an embodiment of the present invention. m Structure diagram, differential transconductance unit G m Includes: multiple input pairs, Figure 2 The example shown uses a P-type transistor as an example of an input transistor. Multiple input pairs are divided into two paths, and each input pair consists of transistors of the same size; that is, each P-type transistor is the same size, but the multiplier is different.

[0073] The gate of the first input transistor pair is connected to the quantum well detector interface J1 to receive the voltage to be measured. The multiplier of the first input transistor pair is 2. n That is, the gate of M1 is connected to the quantum well detector interface J1 to receive the voltage to be measured, and the multiplier of M1 is 2. n .

[0074] The number of transistors in the second input pair is determined by n, and the multiplier for the second input pair is divided into 1, 1, 2...2 according to the binary code weights. n-1 That is, the multiplier of M2 is 1, the multiplier of M3 is 1, the multiplier of M4 is 2, ..., the multiplier of Mn+2 is 2. n-1 .

[0075] The source terminals of M1 to Mn+2 are all connected to a fixed current source I. SSThe drain end of M1 outputs a first differential output current I1, and the drain ends of M2-Mn+2 collectively output a second differential output current I2. bot The gate end of M3-Mn+2 is connected to high bias voltage V top and low bias voltage V bot through two switches, respectively. For example, the gate end of M3 is controlled by D1 through a first switch, when D1 is 1, the first

[0076] ˉ

[0077] switch is closed, and the gate end of M3 receives high bias voltage V top , while the second switch is controlled by D1, when D1 is 1

[0078] ˉ

[0079] , D1 is 0, the second switch is open, and the gate end of M3 cannot receive low bias voltage V bot . The remaining cases can be similarly deduced and will not be described herein. This structure is equivalent to a transistor with a multiplication factor of 2 n , whose gate end is connected to the reference voltage to be generated by low n-bit calibration data D1-D n , so that the entire differential transconductance unit G m can easily complete the low n-bit conversion of the calibration data while converting the differential voltage (i.e., the difference between the measured voltage and the reference voltage) to a differential output current.

[0080] For example, when n=k=3 and the calibration intermediate value is set to 600mV, the above-mentioned involves 9 initial voltage values, which can be set to 616mV, 612mV, 608mV, 604mV, 600mV, 596mV, 592mV, 588mV and 584mV in turn; if D4-D6 are all "1", 616mV is selected as the high bias voltage and 612mV is selected as the low bias voltage; if D4-D6 are all "0", 588mV is selected as the high bias voltage and 584mV is selected as the low bias voltage; and so on. When D4-D6 are all "0", if D1-D3 are all "1", the final generated reference voltage is 587.5mV; if D1-D3 are all "0", the final generated reference voltage is 584mV; and so on, thus achieving 6-bit non-uniformity calibration in a total range of 32mV.

[0081] Referring to Figure 3 , a structure schematic diagram of any oscillation circuit and waveform shaping module in a preferred oscillation unit in the embodiment of the application is shown. Figure 3This includes: any differential output current injection interface J2, five cascaded identical inverters inr, a common-gate P-type transistor Mp, an inverted aspect ratio N-type transistor Md, and a minimum-size N-type transistor Mr. The P-type transistor Mp is used to suppress external disturbances, the inverted aspect ratio N-type transistor Md is used to raise the upper voltage limit of the oscillation waveform and limit transient large currents, and the minimum-size N-type transistor Mr acts as a set switch. The gate of the P-type transistor Mp receives a fixed bias voltage V. b The gate of the smallest N-type transistor Mr receives the set signal RST.

[0082] When the set signal RST is low during operation, the entire oscillation circuit oscillates normally. When RST is high, the injected current (i.e., the aforementioned differential output current) flows entirely into ground via the set switch, and the oscillation circuit remains stationary in a defined state. The original oscillation waveform of the oscillation circuit is processed by the waveform shaping module WFS before being connected to the clock terminal of the counter. Figure 3 (Not shown in the image). The function of the Waveform Shaping Module (WFS) is to sharpen the signal waveform, reduce its rise and fall times, and avoid unnecessary shoot-through current and additional power consumption for subsequent digital circuits such as counters; at the same time, it restores the original oscillation waveform to a signal with a full swing, that is, it raises the voltage range to match the voltage domain of the digital circuit. To achieve these objectives, the Waveform Shaping Module (WFS) can be constructed using multi-stage inverters in series or level shifters.

[0083] For any oscillating circuit, the oscillation frequency f is approximately proportional to I within a suitable input range. in / C total , where I in C represents the magnitude of the first differential output current or the second differential output current. total This represents the total gate capacitance of the multi-stage inverter; the counting and reading unit counts any pulse output, and the corresponding counting result is proportional to T / f, where T represents the preset oscillation duration.

[0084] If I0 represents the magnitude of the differential output current injected into each oscillator circuit in the equilibrium state (i.e., the differential voltage value is 0), and ΔI represents the differential current value, then the differential counting result is proportional to... Right now When the differential current ΔI is much smaller than the equilibrium current I0, the second term in the denominator is a second-order small quantity and can therefore be ignored; with G m Let ΔI represent the transconductance value of the differential transconductance unit, and ΔV represent the difference between the voltage to be measured and the reference voltage. Then, we have: ΔI = G m The complete expression for obtaining the difference counting result is: ΔV

[0085]

[0086] Wherein, K is a certain proportional coefficient, that is, the difference counting result reflects the difference between the to-be-measured voltage and the reference voltage in proportion. And the linearity and accuracy of this quantization process can be guaranteed especially in the case of small input range, which is also consistent with the feature that the signal change amount accounts for a very small proportion.

[0087] Of course, it can be understood that the differential transconductance unit G m And the oscillation circuit can also make the P-type and N-type transistors in it into a symmetrical transformation, so that the current flows from the N-type transistor side. The working principle of this transformation structure is completely similar to that of the original structure, and will not be described in detail.

[0088] In addition, in the embodiment of the present application, the two counters Counter1 and Counter2 are realized in the form of D flip-flop cascade, which are asynchronous binary counters. Compared with synchronous counters, the jump rate of internal nodes of asynchronous counters is much lower, thereby saving considerable power consumption; on the other hand, the inherent transmission delay, asynchronous of high and low data and other shortcomings of asynchronous counters can be ignored under the application conditions of micro signals and low oscillation frequency and the like. After a specified oscillation and counting duration, the oscillation circuit is set and static, and after stabilization, the two sets of counting results are efficiently read out in digital form and sent to the pixel external subtracter SR for difference operation. Finally, the counters will be cleared, waiting for the next working period.

[0089] Based on the above micro voltage difference quantization circuit, the embodiment of the present application also contains a sensing device, which comprises a quantum well detector and a micro voltage difference quantization circuit according to any one of the above embodiments.

[0090] The above examples show that the micro voltage difference quantization circuit of the present application can adapt to quantum well detector devices, while suppressing the nonlinearity and non-uniformity between pixels of the quantum well detector devices, the hardware cost is as little as possible, and the advantages of the quantum well detector devices in the infrared imaging system are fully brought into play.

[0091] It should be noted that in this document, the terms "comprise", "contain" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, article or device. Without more limitations, the element defined by the statement "comprises a" does not exclude the presence of additional identical elements in the process, method, article or device including the element.

[0092] The embodiments of the present application are described above with reference to the accompanying drawings, but the present application is not limited to the above-described specific embodiments, and the above-described specific embodiments are merely illustrative, but not restrictive, and a person of ordinary skill in the art can make many embodiments under the inspiration of the present application without departing from the purpose of the present application and the scope protected by the claims, and these contents are all within the protection scope of the present application.

Claims

1. A micro voltage difference quantizing circuit with a non-uniformity calibration function, characterized by comprising: a voltage difference quantizing circuit; a non-uniformity calibration circuit; and a control circuit. The micro-voltage difference quantization circuit comprises a calibration unit, a differential transconductance unit, an oscillation unit and a counting readout unit; The calibration unit acquires external calibration data and converts the external calibration data into refined reference voltage in combination with the differential transconductance unit; The differential transconductance unit receives a to-be-tested voltage from a quantum well and generates two differential output currents based on the refined reference voltage and the to-be-tested voltage, and outputs the two differential output currents to the oscillation unit; The oscillation unit receives the two differential output currents, generates two pulse outputs, and transmits the two pulse outputs to the counting readout unit; The counting readout unit counts the two pulse outputs to obtain a quantization result and outputs the quantization result.

2. The micro voltage delta quantization circuit of claim 1, wherein, The calibration unit comprises a calibration data memory and a calibration data digital-to-analog converter. The calibration data memory is implemented in the form of an n+k-bit D latch, acquires the external calibration data in a preparation stage before each working cycle, and fixes the external calibration data. The calibration data storage sends k-bit data D n+1 ~D n+k to the calibration data digital-to-analog converter, and sends n-bit data D1~D n to the differential transconductance unit; The calibration data digital-to-analog converter is based on the k-bit data D n+1 ~D n+k Two bias voltages are generated and sent to the differential transconductance unit.

3. The micro voltage delta quantization circuit of claim 2, wherein, The calibration data digital-to-analog converter is composed of a switch array. The k-bit data D n+1 ~D n+k With the switch array, in 2 k +1 uniformly distributed voltage, select adjacent two as two said bias voltage, two said bias voltage is: high bias and low bias respectively; The high bias voltage and the low bias voltage are both transmitted to the differential transconductance unit.

4. The micro voltage delta quantization circuit of claim 3, wherein, The differential transconductance unit divides the high bias voltage and the low bias voltage by 2 n under the control of the n-bit data D1~D n n, and finally converts the external calibration data into the refined reference voltage. The values of n and k can be changed according to actual requirements.

5. The micro voltage delta quantization circuit of claim 3, wherein, The differential transconductance unit comprises a plurality of input pair tubes, the plurality of input pair tubes are divided into two paths, each input pair tube is composed of transistors of the same size, and the multiplication numbers are different; The first input pair of the transistor receives the to-be-tested voltage at the grid, and the multiplication factor of the first input pair of the transistor is 2 n ; The voltage value received at the gate of the second input pair is determined by the n-bit data D1~D n It is decided that the multiplier of the second input pair is divided into 1, 1, 2...2 according to the binary code weight. n-1 .

6. The micro voltage delta quantization circuit of claim 5, wherein, The source end of the input pair tube in the first path is connected to a fixed current source, and the drain end outputs a first differential output current of the two differential output currents; In the second path of input pair tubes, the source end of each input pair tube is also connected to the fixed current source, and the drain end of each input pair tube collectively outputs a second differential output current of the two differential output currents; The gate end of the first input pair tube in the second path of input pair tubes receives the low bias voltage, and the multiplication number of the first input pair tube is 1; The second road input pair tube in addition to the first input pair tube of the rest of the input pair tube, all through the first switch receive the high bias, through the second switch receive the low bias, wherein, if a certain input pair tube multiplier is 1, the first switch and the second switch corresponding to the input pair tube gate end controlled by the n bit data D1~D n in D1, if a certain input pair tube multiplier is 2, the first switch and the second switch corresponding to the input pair tube gate end controlled by the n bit data D1~D n in D2…… If a certain input pair tube multiplier is 2 n-1 , the first switch and the second switch corresponding to the input pair tube gate end controlled by the n bit data D1~D n in D n .

7. The micro voltage delta quantization circuit of claim 6, wherein, The oscillation unit comprises two oscillation circuits and two waveform shaping modules; The first oscillation circuit in the two oscillation circuits receives the first differential output current, oscillates to generate a first pulse output, and the first pulse output is transmitted to the counting readout unit after being processed by a first waveform shaping module of the two waveform shaping modules; The second oscillation circuit in the two oscillation circuits receives the second differential output current, oscillates to generate a second pulse output, and the second pulse output is transmitted to the counting readout unit after being processed by a second waveform shaping module of the two waveform shaping modules. For any oscillation circuit, it comprises a plurality of cascaded same inverters, a P-type transistor in common gate connection, an N-type transistor with reversed width-length ratio, and an N-type transistor with minimum size.

8. The micro voltage delta quantization circuit of claim 7, wherein, For any oscillation circuit: the oscillation frequency f is approximately proportional to I within a suitable input range in / C total where I in denotes the magnitude of the first or second differential output current, C total denotes the sum of the gate stage capacitances of the multi-stage inverter; The counting readout unit counts any pulse output, and the corresponding counting result is proportional to T / f, where T represents a preset oscillation duration.

9. The micro voltage delta quantization circuit of claim 8, wherein, If I0 represents the size of the differential output current injected into each oscillation circuit in the equilibrium state, and ΔI represents the differential current value, then the differential counting result is proportional to That is When the differential current value ΔI is much smaller than the size of the current I0, the second term in the denominator is a second-order small quantity, and is ignored. G m represents the transconductance value of the differential transconductance unit, and ΔV represents the difference between the to-be-measured voltage and the reference voltage, then there is: ΔI = G m ΔV, and the complete expression of the differential counting result is: K is a certain proportional coefficient, that is, the differential counting result proportionally reflects the difference between the to-be-tested voltage and the reference voltage.

10. A sensing device, characterized by The sensing device comprises a quantum well detector and the micro-voltage difference quantization circuit according to any one of claims 1-9.

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