Random number generation circuit and random number generation method

Abstract

The application provides a random number generating circuit and a random number generating method, which are used for generating a random number code and include a number generating circuit, a frequency divider, a sampling circuit and a processing circuit. The number generating circuit generates a random variable according to a first setting value and a first operation rule. The frequency divider processes a first clock signal according to a second setting value to generate a second clock signal. The sampling circuit samples the random variable according to the second clock signal to generate the random number code. The processing circuit provides the first setting value and the second setting value according to a power-on time of a core logic. The application can realize that the rule of random number generation is not easy to be predicted, and improve the security of internal data of a computer.

Description

Technical Field

[0001] This invention relates to an electronic circuit, and more particularly to a random number generation circuit and a random number generation method. Background Technology

[0002] With the development of electronic devices, random numbers have been applied in fields such as computer security, especially in computer security. However, when the patterns of random number generation are easily predictable, it can compromise the security of data stored within the computer. Summary of the Invention

[0003] An embodiment of the present invention provides a random number generation circuit for generating a random number, comprising a number generation circuit, a frequency divider, a sampling circuit, and a processing circuit. The number generation circuit generates a random variable based on a first preset value and a first arithmetic rule. The frequency divider processes a first clock signal based on a second preset value to generate a second clock signal. The sampling circuit samples the random variable based on the second clock signal to generate the random number. The processing circuit provides the first and second preset values ​​based on a power-on time of a core logic.

[0004] Another embodiment of the present invention provides a random number generation circuit for generating a random number, comprising a number generation circuit, a frequency divider, and a sampling circuit. The number generation circuit selects a first specific rule from a plurality of calculation rules according to a preset value, and generates a random variable according to the first specific rule. The frequency divider processes a first clock signal according to the preset value to generate a second clock signal. The sampling circuit samples the random variable according to the second clock signal to generate the random number. The preset value is the random number.

[0005] The present invention also provides a method for generating random numbers, for generating a first random number. The method includes: detecting a power-on time of a core logic; using a first arithmetic rule based on the power-on time to generate a random variable; processing a first clock signal based on the power-on time to generate a second clock signal; and sampling the random variable based on the second clock signal to generate a random number.

[0006] The random number generation method of the present invention can be implemented by the random number generation circuit of the present invention, which is hardware or firmware capable of performing specific functions, or it can be implemented by including program code in a recording medium and combining it with specific hardware. When the program code is loaded and executed by an electronic device, processor, computer or machine, the electronic device, processor, computer or machine becomes used to implement the random number generation circuit of the present invention. Attached Figure Description

[0007] Figure 1 This is a possible schematic diagram of the random number generation circuit of the present invention;

[0008] Figure 2 This is a schematic diagram of voltages VDDA and V15;

[0009] Figure 3A This is another schematic diagram of the random number generation circuit of the present invention;

[0010] Figure 3B This is another schematic diagram of the random number generation circuit of the present invention;

[0011] Figure 4 This is a possible schematic diagram of the processing circuit of the present invention;

[0012] Figure 5 This is another schematic diagram of the random number generation circuit of the present invention;

[0013] Figure 6A This is a possible flowchart of the random number generation method of the present invention;

[0014] Figure 6B This is another possible flowchart of the random number generation method of the present invention;

[0015] Figure 7 This is another possible flowchart of the random number generation method of the present invention.

[0016] Icon labels:

[0017] 100, 300A, 300B, 500: Random number generation circuit;

[0018] 110, 310, 510: Digital generation circuit;

[0019] 120, 320, 520: Sampling circuit;

[0020] 130, 330, 530: Frequency dividers;

[0021] 140, 340A, 340B, 400: Processing circuits;

[0022] 150, 350: Core logic;

[0023] 160: Detection circuit;

[0024] 360: Switch;

[0025] 410: Counter;

[0026] 420: Processor;

[0027] N, M: Setting values;

[0028] randbit: random variable;

[0029] OCK: Operating clock signal;

[0030] SCK1, SCK2, SCK3: Clock signals;

[0031] RDN: Random Number;

[0032] V15, VDDA: Voltage;

[0033] V15_RDY, POR50: Ready signals;

[0034] T1, T2, T3: Time points;

[0035] 210, 220: Differences;

[0036] S611, S612, S613, S614, S615, S616, S617, S711, S712, S713: Steps. Detailed Implementation

[0037] To make the objectives, features, and advantages of this invention more apparent and understandable, embodiments are provided below, along with detailed descriptions in conjunction with the accompanying drawings. This specification provides different embodiments to illustrate the technical features of different implementations of the invention. The configuration of the elements in the embodiments is for illustrative purposes only and is not intended to limit the invention. Furthermore, the repetition of some reference numerals in the embodiments is for simplification and does not imply any correlation between different embodiments.

[0038] Figure 1 This is a possible schematic diagram of the random number generation circuit of the present invention. The random number generation circuit 100 includes a number generation circuit 110, a sampling circuit 120, a frequency divider 130, and a processing circuit 140. The number generation circuit 110 generates a random variable randbit according to a set value N, employing a first operation rule. In one possible embodiment, the number generation circuit 110 stores multiple operation rules and selects and uses different operation rules according to different set values ​​N. In other embodiments, these operation rules are stored in a memory (not shown) external to the number generation circuit 110. In this example, the number generation circuit 110 reads the external memory according to the set value N to adopt the corresponding operation rule.

[0039] In this embodiment, the number generation circuit 110 receives an operation clock signal OCK. In one possible embodiment, the operation clock signal OCK is generated by an oscillation circuit (not shown). The present invention does not limit the architecture of the number generation circuit 110. In one possible embodiment, the number generation circuit 110 includes a linear feedback shift register (LFSR). The set value N may be used as a tap bit of the linear feedback shift register. Since the random variable randbit generated by the linear feedback shift register has periodicity, the periodicity of the random variable randbit changes when the set value N changes. Because the periodicity of the random variable randbit is unpredictable, the security of the random number generation circuit 100 is significantly improved.

[0040] Frequency divider 130 processes the frequency of a clock signal SCK1 according to a set value M to generate a clock signal SCK2. In this embodiment, the frequency of clock signal SCK2 is less than the frequency of clock signal SCK1. In a possible embodiment, clock signal SCK1 is generated by another oscillation circuit (not shown). The frequency of clock signal SCK1 is less than the frequency of the operating clock signal OCK. In some embodiments, the frequency of the operating clock signal OCK is more than twice the frequency of clock signal SCK1.

[0041] The sampling circuit 120 samples the random variable randbit according to the clock signal SCK2 to generate a random number RDN. This invention does not limit the architecture of the sampling circuit 120. In one possible embodiment, the sampling circuit 120 is a D-type flip-flop, but this is not intended to limit the invention.

[0042] Processing circuit 140 detects the power-on time of core logic 150 and generates setpoints N and M based on this power-on time. During the power-on process of the integrated circuit (IC), the settling time of core logic 150 is affected by many factors, such as process voltage-temperature (PVT) variations. The power-on time of core logic 150 differs each time it is initially powered on, subsequently powered down, and then powered on again. Therefore, processing circuit 140 provides different setpoints (i.e., setpoints N and M) based on the power-on time of core logic 150 to increase the randomness of the random number generator (RDN).

[0043] In some embodiments, core logic 150 sets the level of the ready signal V15_RDY based on voltage V15. In one possible embodiment, voltage V15 is the operating power voltage of the core logic. In this example, voltage V15 may be generated by a low-dropout regulator (LDO). When voltage V15 is below a first target value, core logic 150 sets the ready signal V15_RDY to a first level. When voltage V15 reaches the first target value, core logic 150 sets the ready signal V15_RDY from the first level to a second level. In this embodiment, the first level is relative to the second level. For example, the first level may be a low level, and the second level may be a high level.

[0044] This invention does not limit how the processing circuit 140 detects the power-on time of the core logic 150. In one possible embodiment, the processing circuit 140 determines the power-on time of the core logic 150 based on the ready signal V15_RDY. For example, when the processing circuit 140 receives a clock signal SCK3, the processing circuit 140 begins a counting operation. When the ready signal V15_RDY changes from a first level to a second level, the processing circuit 140 stops the counting operation. In this example, the processing circuit 140 uses the execution time of the counting operation as the power-on time of the core logic 150. In one possible embodiment, the frequency of the clock signal SCK3 is approximately equal to the frequency of the operating clock signal OCK or the clock signal SCK1. In other embodiments, the frequency of the clock signal SCK3 is greater than the frequency of the clock signal SCK1. In some embodiments, the frequency of the clock signal SCK3 is approximately twice the frequency of the clock signal SCK1.

[0045] In another possible embodiment, the processing circuit 140 further receives a ready signal POR50. In this example, the processing circuit 140 performs a counting operation based on the ready signal POR50 and V15_RDY. For example, when the ready signal POR50 changes from a third level to a fourth level, the processing circuit 140 starts a counting operation. When the ready signal V15_RDY changes from a first level to a second level, the processing circuit 140 stops the counting operation. In this example, the processing circuit 140 uses the execution time of the counting operation as the power-on time of the core logic 150. The third level is relative to the fourth level. For example, when the third level is low, the fourth level is high. When the third level is high, the fourth level is low. In other embodiments, the third level may be the same as the first level or the second level.

[0046] In other embodiments, the ready signal POR50 is provided by a detection circuit 160. In this example, when the voltage VDDA is below a second target value, the detection circuit 160 sets the ready signal POR50 to a third level. When the voltage VDDA reaches the second target value, the detection circuit 160 sets the ready signal POR50 to change from the third level to a fourth level. In this embodiment, the voltage VDDA is greater than the voltage V15. In a possible embodiment, the voltage VDDA is the voltage of a battery. In this example, a voltage regulator (not shown) converts the voltage VDDA and uses the converted result as the voltage V15.

[0047] Figure 2 This is a schematic diagram of voltages VDDA and V15. Before time point T1, voltage VDDA starts from 0V and gradually increases. At time point T1, voltage VDDA reaches the second target value (e.g., 5V). Therefore, detection circuit 160 enables the ready signal POR50, causing POR50 to change from a low level L to a high level H. In other embodiments, when detection circuit 160 enables the ready signal POR50, the ready signal POR50 changes from a high level to a low level. Before time point T2, voltage V15 starts from 0V and gradually increases. At time point T2, voltage V15 reaches the first target value (e.g., 1.5V). Therefore, core logic 150 enables the ready signal V15_RDY. At this time, the ready signal V15_RDY changes from a low level L to a high level H. In other embodiments, when the core logic 150 enables the ready signal V15_RDY, the ready signal V15_RDY changes from a high level to a low level.

[0048] In one possible embodiment, processing circuit 140 provides setpoints N and M based on the difference 210 between time points T1 and T2. In another possible embodiment, at time point T3, the voltage VDDA rises to a specific value (e.g., 4V). Therefore, an oscillation circuit (not shown) starts operating to generate a clock signal SCK3. At this time, processing circuit 140 begins a counting operation. At time point T2, processing circuit 140 stops the counting operation because the ready signal V15_RDY is enabled. In this example, processing circuit 140 provides setpoints N and M based on the difference 220 between time points T3 and T2.

[0049] In other embodiments, processing circuit 140 may directly receive voltage V15. In this example, when processing circuit 140 receives clock signal SCK3, processing circuit 140 begins performing a counting operation. When voltage V15 reaches a first target value, processing circuit 140 stops the counting operation. Processing circuit 140 generates set values ​​N and M based on the execution time of the counting operation.

[0050] In some embodiments, the processing circuit 140 may directly receive the voltage VDDA. In this example, when the voltage VDDA reaches a second target value, the processing circuit 140 begins performing a counting operation. When the voltage V15 reaches a first target value, the processing circuit 140 stops the counting operation. The processing circuit 140 generates set values ​​N and M based on the execution time of the counting operation.

[0051] Figure 3A This is another schematic diagram of the random number generation circuit of the present invention. Figure 3A Similar to Figure 1 The difference lies in that the processing circuit 340A also receives random numbers (RDNs). This is because the characteristics of the number generation circuit 310, sampling circuit 320, and frequency divider 330 of the random number generation circuit 300A are similar to... Figure 1 The characteristics of the digital generation circuit 110, sampling circuit 120 and frequency divider 130 are not described in detail here.

[0052] In this embodiment, the processing circuit 340A adjusts the set values ​​N and M according to the random number RDN. For example, during an initial period, the processing circuit 340A generates the set values ​​N and M based on the power-on time of a core logic 350. During a normal operation period (continuing the initial period), the processing circuit 340A adjusts at least one of the set values ​​N and M according to the random number RDN. In some embodiments, during normal operation, the processing circuit 340A adjusts at least one of the set values ​​N and M according to the random number RDN at fixed intervals.

[0053] Assume that during normal operation, processing circuit 340A adjusts the setpoint N according to the random number RDN, but does not adjust the setpoint M. In this example, number generation circuit 310 uses a second operation rule to adjust the random variable randbit according to the adjusted setpoint N. At this time, since processing circuit 340A does not change the setpoint M, frequency divider 330 does not change the frequency of clock signal SCK2. In other words, the frequency of clock signal SCK2 remains unchanged during the initial period and normal operation. In this example, sampling circuit 320 samples the adjusted random variable randbit according to the unchanged clock signal SCK2 to generate a new random number RDN.

[0054] In another possible embodiment, during normal operation, processing circuit 340A adjusts the setpoint M according to the random number RDN, but does not adjust the setpoint N. In this example, frequency divider 330 changes the frequency of clock signal SCK2 according to the adjusted setpoint M. At this time, since processing circuit 340A does not change the setpoint N, the number generation circuit 310 continues to use the first operation rule. Sampling circuit 320 samples the random variable randbit according to the adjusted clock signal SCK2 to generate a new random number RDN.

[0055] In some embodiments, during normal operation, the processing circuit 340A adjusts the setpoints N and M based on the random number RDN. In this example, the number generation circuit 310 adjusts the random variable randbit using a second arithmetic rule based on the adjusted setpoint N. The frequency divider 330 changes the frequency of the clock signal SCK2 based on the adjusted setpoint M. The sampling circuit 320 samples the adjusted random variable randbit based on the adjusted clock signal SCK2 to generate a new random number RDN.

[0056] Figure 3B This is another schematic diagram of the random number generation circuit of the present invention. Figure 3B Similar to Figure 3A The difference is that, Figure 3B The random number generation circuit 300B further includes a switch 360. During an initial period, the processing circuit 340B does not turn on the switch 360. At this time, the processing circuit 340B controls the digital generation circuit 310 and the frequency divider 330 according to the power-on time of the core logic 350. During normal operation, the processing circuit 340B turns on the switch 360. At this time, the digital generation circuit 310 and the frequency divider 330 operate according to the random number RDN.

[0057] Figure 4 This is a possible schematic diagram of the processing circuit of the present invention. For example... Figure 4 As shown, the processing circuit 400 includes a counter 410 and a processor 420. When the counter 410 receives the clock signal SCK3, the counter 410 begins to adjust a count value CNV. When the ready signal V15_RDY is enabled, the counter 410 stops adjusting the count value CNV. This invention does not limit the type of counter 410. The counter 410 may be an up-counting counter or an down-counting counter. In other embodiments, the counter 410 is a timer.

[0058] In some embodiments, counter 410 directly receives voltage V15. In this example, counter 410 adjusts the count value CNV according to clock signal SCK3. When voltage V15 reaches a first target value, counter 410 stops adjusting the count value CNV.

[0059] In other embodiments, counter 410 may receive a ready signal POR50. In this example, when the ready signal POR50 is enabled, counter 410 begins adjusting the count value CNV. When the ready signal V15_RDY is enabled, counter 410 stops adjusting the count value CNV. In some embodiments, counter 410 directly receives the voltage VDDA. When the voltage VDDA reaches a second target value, counter 410 begins adjusting the count value CNV. In this example, when the voltage V15 reaches a first target value, counter 410 stops adjusting the count value CNV.

[0060] Processor 420 generates setpoints N and M based on the count value CNV. This invention does not limit how processor 420 generates the setpoints N and M. In one possible embodiment, processor 420 stores a lookup table. The lookup table records multiple count intervals, multiple first setpoints, and multiple second setpoints. Each count interval corresponds to one of the first setpoints and one of the second setpoints. In this example, processor 420 uses the lookup table to determine which specific count interval the count value CNV falls into, and generates setpoints N and M based on the first and second setpoints corresponding to that specific count interval. In other embodiments, processor 420 directly uses the first and second setpoints corresponding to the specific count interval as setpoints N and M. In some embodiments, the lookup table is stored in a memory (not shown) outside of processor 420.

[0061] Figure 5 This is another schematic diagram of the random number generation circuit of the present invention. The random number generation circuit 500 includes a number generation circuit 510, a sampling circuit 520, and a frequency divider 530. The number generation circuit 510 receives an operation clock signal OCK, and selects a first specific rule from multiple operation rules according to the random number RDN, and then generates a random variable randbit according to the first specific rule. In one possible embodiment, the operation rules are stored in the number generation circuit 510. In another possible embodiment, the operation rules are stored in an external memory (not shown).

[0062] Frequency divider 530 processes clock signal SCK1 based on random number generator (RDN) to generate clock signal SCK2. In this embodiment, frequency divider 530 adjusts the frequency of clock signal SCK1 and uses the adjusted result as clock signal SCK2. Sampling circuit 520 samples random variable randbit based on clock signal SCK2 to update random number generator (RDN).

[0063] In one possible embodiment, during an initial period, the random number RDN is equal to an initial value. At this time, the number generation circuit 510 and the frequency divider 530 operate according to the random number RDN. The sampling circuit 520 updates the random number RDN based on the outputs of the number generation circuit 510 and the frequency divider 530. Then, the number generation circuit 510 and the frequency divider 530 operate again based on the updated random number RDN.

[0064] In some embodiments, after a fixed period of time, the digital generation circuit 510 again selects another rule from multiple operation rules based on the random digital code RDN to adjust the random variable randbit. In one possible embodiment, when the digital generation circuit 510 selects a new operation rule, the frequency divider 530 also readjusts the clock signal SCK2, or does not change the clock signal SCK2. Similarly, after a fixed period of time, the frequency divider 530 may readjust the clock signal SCK2. At this time, the digital generation circuit 510 may select a new operation rule, or still use the same operation rule. By dynamically adjusting the sampling frequency (i.e., the clock signal SCK2) or the operation rule of the digital generation circuit 510 by the random digital code RDN, the unpredictability of the random digital code RDN can be increased.

[0065] Figure 6A This is a possible flowchart of the random number generation method of the present invention. The random number generation method of the present invention is used to generate a random number. First, a power-on time of a core logic is detected (step S611). In a possible embodiment, step S611 is to determine whether a first voltage (e.g., V15) reaches a first target value (e.g., 1.5V) and whether a second voltage (e.g., VDDA) reaches a second target value (e.g., 5V). When the second voltage reaches the second target value, a counting operation is performed. When the first voltage reaches the second target value, the counting operation is stopped. In this example, the duration of the counting operation is the power-on time of the core logic. In some embodiments, the second target value is greater than the first target value.

[0066] In other embodiments, step S611 involves determining whether a specific clock signal (or a third clock signal) has been generated and whether a ready signal has been enabled. When the specific clock signal is generated, a counting operation begins. When the ready signal is enabled, the counting operation stops. In this example, the duration of the counting operation is the power-on time of the core logic. Furthermore, the ready signal is related to a first voltage (e.g., V15). When the first voltage reaches a first target value, the ready signal is enabled. In this embodiment, the specific clock signal is a high-frequency signal.

[0067] Next, based on the power-on time of the core logic, a first operation rule is adopted to generate a first random variable (step S612). In one possible embodiment, step S612 utilizes a linear feedback shift register (LFSR) to generate the first random variable. In this example, the first operation rule may be stored in the linear feedback shift register (LFSR).

[0068] Based on the power-on time of the core logic, a first clock signal is processed to generate a second clock signal (step S613). In one possible embodiment, step S613 involves adjusting the frequency of the first clock signal and using the adjusted result as the second clock signal. In some embodiments, the frequency of the first clock signal is less than the frequency of the third clock signal.

[0069] Then, based on the second clock signal, the first random variable is sampled to generate a first random number (step S614). In this example, since the power-on time of the core logic is different each time, if the power-on time is used as the random number seed, the periodicity of the first random number will be unpredictable.

[0070] Figure 6B This is another possible flowchart of the random number generation method of the present invention. Figure 6B Similar to Figure 6A The difference is that, Figure 6B Steps S615, S616, and S617 are added. In this embodiment, steps S611, S612, S613, and S614 are executed during an initial period, while steps S615, S616, and S617 are executed during a normal operation period.

[0071] During normal operation, based on the first random number generated in step S614, a second calculation rule is applied to generate a second random variable (step S615). The second calculation rule differs from the first calculation rule in step S612. Furthermore, based on the first random number, the second clock signal is adjusted again (step S616). Finally, based on the adjusted second clock signal, the second random variable is sampled to generate a second random number (step S617).

[0072] In some embodiments, during an initial period, a first random number is generated using the power-on time of the core logic. During normal operation, a second random number is generated using the first random number. Therefore, the random number generated by this invention has higher randomness.

[0073] In other embodiments, step S615 may be omitted. In this example, during normal operation, step S616 adjusts the second clock signal according to the first random number (step S616). Step S617 samples the first random variable generated in step S612 according to the second clock signal adjusted in step S616 to generate a second random number.

[0074] In some embodiments, step S616 may be omitted. In this example, step S615 uses a second operation rule based on the first random number generated in step S614 to generate a second random variable. Step S617 samples the second random variable based on the second clock signal generated in step S613 to generate a second random number.

[0075] Figure 7 This is another possible flowchart of the random number generation method of the present invention. First, based on a random number, a first specific rule is selected from multiple operation rules, and a random variable is generated according to the first specific rule (step S711). Then, based on the random number, a first clock signal is processed to generate a second clock signal (step S712). In one possible embodiment, step S712 is to adjust the frequency of the first clock signal.

[0076] Then, based on the second clock signal, the random variable is sampled to update the random number (step S713), and the process returns to step S711. In some embodiments, step S711 selects a second specific rule from multiple calculation rules based on the random number updated in step S713, and generates a second random variable according to the second specific rule. In this example, step S712 adjusts the frequency of the second clock signal based on the random number updated in step S713. Step S713 samples the second random variable based on the adjusted second clock signal and updates the random number again.

[0077] The random number generation method, or a specific form or part thereof of the present invention, can exist in the form of program code. The program code can be stored on physical media, such as floppy disks, optical discs, hard disks, or any other machine-readable (e.g., computer-readable) storage media, or not limited to external computer program products. When the program code is loaded and executed by a machine, such as a computer, that machine becomes a participant in the random number generation circuit of the present invention. The program code can also be transmitted via some transmission medium, such as wires or cables, optical fibers, or any transmission method. When the program code is received, loaded, and executed by a machine, such as a computer, that machine becomes a participant in the random number generation circuit of the present invention. When implemented in a general-purpose processing unit, the program code, combined with the processing unit, provides a unique device that operates similarly to an application-specific logic circuit.

[0078] Unless otherwise defined, all terms herein (including technical and scientific terms) are as commonly understood by those skilled in the art. Furthermore, unless expressly stated otherwise, definitions of terms in general dictionaries should be interpreted as consistent with their meaning in the context of their relevant technical field, and not as idealized or overly formal expressions. While terms such as "first," "second," etc., may be used to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another.

[0079] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make modifications and refinements without departing from the spirit and scope of the invention. For example, the systems, apparatus, or methods described in the embodiments of the present invention can be implemented in physical embodiments of hardware, software, or a combination of hardware and software. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the appended claims.

Claims

1. A random number generation circuit, characterized in that, Used to generate a random number, including: A digital generation circuit generates a random variable based on a first set value, using a first operation rule, and according to the first operation rule. A frequency divider processes a first clock signal according to a second set value to generate a second clock signal; A sampling circuit samples the random variable based on the second clock signal to generate the random number; and A processing circuit provides the first set value and the second set value based on a power-on time of a core logic. The processing circuit performs a counting operation. When the operating voltage of the core logic reaches a first target value, the processing circuit stops the counting operation. The processing circuit adjusts the first set value and the second set value according to the execution time of the counting operation. The digital generation circuit includes a linear feedback shift register, and the first set value serves as the tap bit of the linear feedback shift register. The processing circuit uses the execution time of the counting operation as the power-on time of the core logic, and the tap bits of the linear feedback shift register are adjusted according to the power-on time of the core logic.

2. The random number generation circuit as described in claim 1, characterized in that, The digital generation circuit receives an operation clock signal, the frequency of which is greater than the frequency of the first clock signal.

3. The random number generation circuit as described in claim 1, characterized in that, The processing circuit includes: A counter adjusts a count value according to a third clock signal, and stops adjusting the count value when a first voltage reaches a first target value; and A processor generates the first set value and the second set value based on the count value.

4. The random number generation circuit as described in claim 3, characterized in that, The frequency of the third clock signal is greater than the frequency of the first clock signal.

5. The random number generation circuit as described in claim 4, characterized in that, When the counter receives the third clock signal, the counter begins to adjust the count value.

6. The random number generation circuit as described in claim 3, characterized in that, The frequency of the third clock signal is equal to the frequency of the first clock signal.

7. The random number generation circuit as described in claim 6, characterized in that, When a second voltage reaches a second target value, the counter begins to adjust the count value, which is higher than the first target value.

8. The random number generation circuit as described in claim 1, characterized in that: During an initial period, the processing circuit controls the digital generation circuit and the frequency divider according to the power-on time of the core logic; and During normal operation, the digital generation circuit and the frequency divider operate according to the random digital code.

9. The random number generation circuit as described in claim 8, characterized in that, During normal operation, the digital generation circuit uses a second calculation rule based on the random digital number, which is different from the first calculation rule.

10. A method for generating random numbers, characterized in that, Used to generate a first random number, including: Perform a counting operation; The counting operation stops when the operating voltage of a core logic reaches a first target value. Based on the execution time of the counting operation, a first set value and a second set value are generated; The first set value is used as the tap bit of a linear feedback shift register, wherein the linear feedback shift register uses a first operation rule according to the first set value to generate a first random variable. Based on the second set value, a first clock signal is processed to generate a second clock signal; and Based on the second clock signal, the first random variable is sampled to generate the first random number. The execution time of the counting operation is the power-on time of the core logic, and the tap bits of the linear feedback shift register are adjusted according to the power-on time of the core logic.

11. The random number generation method as described in claim 10, characterized in that, Including: Detect whether the first voltage reaches the first target value; Detect whether the second voltage reaches a second target value; When the second voltage reaches the second target value, the counting operation is performed; and When the first voltage reaches the second target value, the counting operation is stopped; The second target value is greater than the first target value.

12. The random number generation method as described in claim 10, characterized in that, Including: Determine whether a third clock signal has been generated; Determine whether a ready signal is enabled; When the third clock signal is generated, the counting operation is performed; and The counting operation stops when the ready signal is enabled. The frequency of the third clock signal is greater than the frequency of the first clock signal. When a first voltage reaches the first target value, the ready signal is enabled.

13. The random number generation method as described in claim 10, characterized in that, Including: During normal operation: Based on the first random number, a second operation rule is adopted to generate a second random variable; Adjust the second clock signal according to the first random number; and Based on the adjusted second clock signal, the second random variable is sampled to generate a second random number.

14. The random number generation method as described in claim 13, characterized in that, The second operation rule is different from the first operation rule.

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