Image processing chip, memory, board, device, data writing and reading method

Abstract

The embodiment of the present disclosure provides an image processing chip, a memory, a board card, an equipment and a data writing and reading method. The image processing chip comprises a processing unit, a storage unit and a data reading unit. The storage unit is used for storing pixel data of a target image. The data reading unit can determine a storage address of pixel data to be read based on a data reading request sent by the processing unit, access the storage address, read all pixel data stored in the storage address, buffer all the read pixel data in a storage subunit of the data reading unit, select the pixel data to be read from the buffered pixel data and output the pixel data to be read. Since all pixel data of the storage address is read out when the data reading unit accesses the storage address each time, the data of the same storage address does not need to be repeatedly accessed when the data is requested again, and the power consumption can be reduced.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuit design, and in particular, to an image processing chip, a memory, a board card, a device, and a data writing and reading method. BACKGROUND

[0002] In the scene of digital image processing, it is often necessary to use 3*3, 5*5, etc. image window to perform some operations, and thus some on-chip storage units, such as SRAM (Static Random-Access Memory), are needed to buffer multiple rows of pixel data of an image for performing the above operations in the process of image processing by the image processing chip. Currently, when storing pixel data by using the on-chip storage unit, only 1-2 pixel data are stored at each address, and this storage manner will cause large area and power consumption overheads of the chip. SUMMARY

[0003] The present disclosure provides an image processing chip, a memory, a board card, a device, and a data writing and reading method.

[0004] According to a first aspect of an embodiment of the present disclosure, an image processing chip is provided, which comprises a processing unit, a storage unit, and a data reading unit, wherein the data reading unit comprises a storage subunit.

[0005] The storage unit is configured to store pixel data of a target image.

[0006] The processing unit is configured to send a data reading request for reading the pixel data of the target image to the data reading unit.

[0007] The data reading unit is configured to determine a storage address of to-be-read pixel data in the storage unit based on the data reading request, access the storage address and read all pixel data stored in the storage address, buffer the read all pixel data in the storage subunit, and select and output the to-be-read pixel data from the buffered all pixel data.

[0008] In some embodiments, the number of pixel data stored in each storage address in the storage unit is greater than the number of pixel data required by the processing unit in each clock cycle in the process of processing the target image.

[0009] In some embodiments, the difference between the data bit width of each storage address in the storage unit and the depth of the storage address in the storage unit is less than a preset difference, wherein the data bit width is determined based on the number of pixel data that can be stored in each storage address and the bit width of each pixel data.

[0010] In some embodiments, the data reading unit is configured to access the storage address and read all pixel data stored in the storage address when the data reading request is received, and in particular is configured to:

[0011] In some embodiments, the data reading unit is configured to access the storage address and read all pixel data stored in the storage address when the data reading request is received, and in particular is configured to:

[0012] In some embodiments, the data reading unit is configured to access the storage address and read all pixel data stored in the storage address when the data reading request is received, and in particular is configured to:

[0013] In some embodiments, the data reading unit is configured to access the storage address and read all pixel data stored in the storage address when the data reading request is received, and in particular is configured to:

[0014] In some embodiments, the data reading unit is configured to access the storage address and read all pixel data stored in the storage address when the data reading request is received, and in particular is configured to:

[0015] In some embodiments, the data reading request carries position information of a starting pixel in the target image in the to-be-read pixel data, and a quantity of to-be-read pixel data, and the data reading unit is configured to determine storage addresses of the to-be-read pixel data in the storage unit based on the data reading request, and in particular is configured to:

[0016] In some embodiments, the data reading request carries position information of a starting pixel in the target image in the to-be-read pixel data, and a quantity of to-be-read pixel data, and the data reading unit is configured to determine storage addresses of the to-be-read pixel data in the storage unit based on the data reading request, and in particular is configured to:

[0017] In some embodiments, the image processing chip includes a plurality of storage units, each of which is configured to store a row of pixel data of the target image, and the data reading request further includes a quantity of rows of to-be-read pixel data, and the data reading unit is configured to determine one or more storage addresses of the storage unit for storing the to-be-read pixel data based on the position information of the starting pixel in the target image and the quantity, and in particular is configured to:

[0018] In some embodiments, the image processing chip includes a plurality of storage units, each of which is configured to store a row of pixel data of the target image, and the data reading request further includes a quantity of rows of to-be-read pixel data, and the data reading unit is configured to determine one or more storage addresses of the storage unit for storing the to-be-read pixel data based on the position information of the starting pixel in the target image and the quantity, and in particular is configured to:

[0019] In some embodiments, the data reading unit further comprises a FIFO register, and when the data reading unit is used to select the pixel data to be read from the buffered pixel data and output, in particular for:

[0020] selecting the pixel data to be read from the buffered pixel data, storing the pixel data to be read in the FIFO register, and outputting the pixel data to be read through the FIFO register.

[0021] In some embodiments, after storing the pixel data to be read in the FIFO register, the data reading unit is further used to:

[0022] returning a first signal to the processing unit, the first signal being used to indicate that the pixel data to be read is in an available state;

[0023] after receiving a second signal issued by the processing unit, outputting the pixel data to be read to the processing unit, the second signal being used to indicate that the processing unit is in a state of being able to receive the pixel data to be read.

[0024] In some embodiments, when the FIFO register has no available storage space, reading of pixel data from the storage unit is stopped.

[0025] In some embodiments, the storage unit comprises a single-port static random access memory (SRAM).

[0026] In some embodiments, the image processing chip further comprises a data writing unit, the data writing unit being used to receive a data writing request sent by the processing unit, and repeatedly perform the following operations until all pixel data to be written are written into the storage unit:

[0027] sequentially obtaining pixel data in an image row of a target image, wherein the number of pixel data obtained in each clock cycle is not greater than a target number, and the target number is the number of pixel data that can be stored in each storage address of the storage unit;

[0028] when it is counted that the number of target pixel data that has been obtained and not written into the storage unit is greater than or equal to the target number, performing a write operation once to write the first target number of pixel data in the target pixel data into one storage address of the storage unit.

[0029] In some embodiments, the data writing unit is further used to:

[0030] In a case where it is counted that the quantity of the target pixel data is less than the target quantity, and it is determined that all the pixel data to be written has been acquired, a one-time write operation is performed to write all the target pixel data into one storage address of the storage unit.

[0031] According to a second aspect of the embodiments of the present disclosure, an image processing chip is provided, which includes a processing unit, a storage unit, a data writing unit,

[0032] The processing unit is configured to send a data writing request of writing pixel data of a target image into the storage unit to the data writing unit.

[0033] The data writing unit is configured to repeatedly perform the following operations until all the pixel data to be written is written into the storage unit after receiving the data writing request:

[0034] acquire pixel data in image rows of the target image in sequence, wherein the quantity of the pixel data acquired in each clock cycle is not greater than a target quantity, and the target quantity is the quantity of pixel data that can be stored in each storage address of the storage unit.

[0035] In a case where it is counted that the quantity of the target pixel data is greater than or equal to the target quantity, a one-time write operation is performed to write the first target quantity of pixel data in the target pixel data into one storage address of the storage unit.

[0036] In some embodiments, the data writing unit is further configured to:

[0037] In a case where it is counted that the quantity of the target pixel data is less than the target quantity, and it is determined that all the pixel data to be written has been acquired, a one-time write operation is performed to write all the target pixel data into one storage address of the storage unit.

[0038] According to a third aspect of the embodiments of the present disclosure, a memory is provided, which is configured to store pixel data of an image, and the difference between the data bit width of each storage address of the memory and the depth of the storage address in the storage unit is less than a preset difference, wherein the data bit width is determined based on the quantity of pixel data that can be stored in each storage address and the bit width of each pixel data.

[0039] According to a fourth aspect of the embodiments of the present disclosure, an image processing chip is provided, which includes a processor and the memory mentioned in the third aspect.

[0040] According to a fifth aspect of the embodiments of the present disclosure, a board card is provided, which comprises a packaging structure packaging at least one chip mentioned in the first aspect, the second aspect and / or the fourth aspect, or the board card is packaged with at least one memory mentioned in the third aspect.

[0041] According to a sixth aspect of the embodiments of the present disclosure, an electronic device is provided, which comprises at least one chip mentioned in the first aspect, the second aspect and / or the fourth aspect, or comprises at least one memory mentioned in the third aspect, or comprises at least one board card mentioned in the fifth aspect.

[0042] According to a seventh aspect of the embodiments of the present disclosure, a data reading method is provided for reading pixel data of a target image from a memory, which comprises:

[0043] receiving a data reading request;

[0044] determining a storage address of the pixel data to be read in the memory based on the data reading request, accessing the storage address and reading and caching all pixel data stored in the storage address;

[0045] selecting the pixel data to be read from the cached all pixel data and outputting.

[0046] According to an eighth aspect of the embodiments of the present disclosure, a data writing method is provided for writing pixel data to be written of a target image into a memory, which comprises:

[0047] repeating the following operations until the pixel data to be written is all written into the memory:

[0048] sequentially obtaining each pixel data in an image row of the target image, wherein the number of pixel data obtained in each clock cycle is not greater than a target number, and the target number is the number of pixel data that can be stored in each storage address of the memory;

[0049] in a case where it is counted that the number of target pixel data that has been obtained and not written into the memory is greater than or equal to the target number, performing a write operation once to write the first target number of pixel data in the target pixel data into one storage address of the memory.

[0050] According to a ninth aspect of the embodiments of the present disclosure, a computer readable storage medium is provided, which stores computer instructions, and the computer instructions are executed to implement the method mentioned in the first aspect.

[0051] In the embodiments of the present disclosure, an image processing chip is provided. In order to reduce the area and power consumption of the chip as much as possible, when designing a storage unit for caching a target image on the chip, the number of pixel data stored in each storage address can be increased. Since the number of pixel data stored in each storage address is increased, the pixel data requested by the processing unit of the chip each time can be less than the pixel data stored in each storage address, or the requested data can be part of the pixel data in multiple storage addresses. Considering that the data requested by the processing unit continuously for multiple times is probably adjacent pixel data, a storage subunit can be arranged in the data reading unit of the chip. After receiving the data reading request issued by the processing unit of the chip, the data reading unit can determine the storage addresses of the pixel data to be read in the storage unit based on the request, then read all the pixel data in each storage address, cache the pixel data in the storage subunit, and select and output the pixel data requested by the processing unit from the cached pixel data. Since all the pixel data in the storage address is read out each time the data reading unit accesses the storage address of the storage unit, it can be avoided that the same storage address needs to be accessed repeatedly when the data in the storage address is requested subsequently, and the power consumption can be reduced.

[0052] It should be understood that the general description above and the detailed description below are only exemplary and explanatory, but not limiting the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0053] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the technical solutions of the present disclosure.

[0054] Figure 1 is a schematic diagram of shape changes of an SRAM when each storage address of the SRAM of the embodiments of the present disclosure stores different amounts of pixel data.

[0055] Figure 2 is a schematic diagram of an image processing chip according to an embodiment of the present disclosure.

[0056] Figure 3 is a schematic diagram of an image processing chip according to an embodiment of the present disclosure.

[0057] Figure 4 is a schematic diagram of an image processing chip according to an embodiment of the present disclosure.

[0058] Figure 5 is a schematic diagram of an image processing chip according to an embodiment of the present disclosure.

[0059] Figure 6 is a schematic diagram of an image processing chip according to an embodiment of the present disclosure.

[0060] Figure 7 FIG. 1 is a schematic diagram of a board card according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0061] The exemplary embodiments will be described in detail herein below with reference to the accompanying drawings. In the following description, unless otherwise indicated, the same reference numerals in different drawings denote the same or similar components. The embodiments described in the following exemplary embodiments do not represent all the embodiments consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0062] The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used in the present disclosure and the appended claims, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. In addition, the term "at least one of' as used herein means any one of or any combination of two or more of the listed items.

[0063] It should be understood that although the terms first, second, third, etc. can be used herein to describe various information, the information should not be limited to these terms. These terms are only used to distinguish one piece of information from another. For example, a first information can also be termed a second information, and similarly, a second information can also be termed a first information without departing from the scope of the present disclosure. Depending on the context, the word "if' as used herein can be interpreted as meaning "when" or "in response to determining" or "in response to ascertaining."

[0064] In order to enable persons skilled in the art to better understand the technical solutions in the embodiments of the present disclosure, and to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more apparent and easy to understand, the technical solutions in the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0065] In the scene of digital image processing, it is often necessary to use 3x3, 5x5 and other image windows to perform some operations, such as Gaussian denoising processing, convolution processing and the like. Generally, a window is used to slide in the image, and then the image block in the window is processed. Since multiple rows of image data are required for processing each time, some on-chip storage units, such as SRAM (Static Random-Access Memory), are usually provided in the image processing chip to buffer multiple rows of pixel data of the image for various processing. Since the throughput rate in the general image processing process is 1-2 pixels, that is, the chip needs to supply 1-2 pixels to the processing unit of the chip in each clock cycle during image processing. The on-chip storage unit usually uses a single-port SRAM, which only supports reading or writing in one clock cycle, that is, reading and writing cannot be performed simultaneously, and one read operation on the single-port SRAM can only read the pixel data stored in one address, and one write operation on the single-port SRAM can only write pixel data to one address.

[0066] In order to match the throughput rate of the image processing process, currently, when storing pixel data using SRAM, one SRAM is usually used to store one row of pixel data, and each address in the SRAM stores 2 pixel data. That is, 1 pixel data can be obtained in each clock cycle, and after 2 pixel data are accumulated, a write operation is performed, that is, a write operation is performed every 2 clock cycles, so that a clock cycle is left for reading operation to read the pixel data of one address to the processing unit for processing.

[0067] The above storage method can meet the current demand of the throughput rate of image processing, but as the image resolution becomes higher and higher, for example, with 8192 pixels per row and 14-bit pixel value per pixel, if 2 pixel data are stored in each address, the address depth (i.e. the number of storage addresses) is 4096, that is, the SRAM can be represented as 4096x28. In this case, the shape of the designed SRAM is usually long and narrow, which wastes the area of the chip. Moreover, since the address depth is large, the selector needs to select one address from 4096 addresses when performing read operation or write operation, which consumes a lot of power. In addition, in the scene of storing 2 pixel data in each address, the operations of reading pixel data from the SRAM and writing pixel data need to be alternately performed in each clock cycle, which requires frequent access to the SRAM, further increasing the power consumption.

[0068] If the depth of the storage address and the data bit width corresponding to each storage address of an on-chip storage unit such as a single-port SRAM are close to each other, the area and power consumption overhead of the on-chip storage unit are smaller. The data bit width of each storage address is determined by the maximum number of pixel data that can be stored in each storage address and the bit width of each pixel data. For example, if each storage address can store a maximum of 2 pixel data and each pixel data has a bit width of 14, then the data bit width of each storage address is 28.

[0069] For example, if the depth of the storage address of the SRAM is compared to the length of a rectangle and the data bit width is compared to the width of the rectangle, it is expected that the shape of the rectangle is close to a square or the length-to-width ratio is within a certain multiple (for example, 10 times), and then the area and power consumption overhead of the SRAM are smaller. For example, as shown in (a)-(d) of FIG. 1, when 1 pixel data, 2 pixel data, 8 pixel data, 16 pixel data, and 32 pixel data are respectively stored in each address, the shapes of the SRAM are shown. As can be seen, when the pixel data stored in each address is more, for example, reaches 8 or 16, the shape of the SRAM is closer to a square. Since the shape is closer to a square rather than a long and narrow shape, the chip area is not wasted too much, and since the data bit width is increased and the address depth is correspondingly reduced, the selector only needs to select an address from fewer addresses each time when reading and writing data in the SRAM, which can save power consumption. In addition, since the number of pixel data stored in each address is increased, the pixel data read and written each time the SRAM is accessed is also increased, which can further reduce the frequency of accessing the SRAM and further reduce power consumption. Figure 1

[0070] In order to reduce the area and power consumption overhead of the chip as much as possible, when designing the on-chip storage unit, the number of pixel data stored in each storage address can be increased, and is no longer limited to 2, but can be set to more, such as 8, 16, or 32, and the like. However, since only one or two pixel data needs to be read and written in each clock cycle during image processing, the number of pixel data that can be accessed by the on-chip storage unit at a time (for example, 8) does not match, and therefore, the scheme for reading and writing pixel data from the on-chip storage unit can be adaptively improved, so that the reading and writing of pixel data is more convenient and flexible, and the power consumption of the chip can be maximized.

[0071] Based on this, the embodiment of the present disclosure provides an image processing chip, as shown in Figure 2 ​As shown, the image processing chip 10 includes a processing unit 11, a storage unit 12, and a data reading unit 13. The image processing chip can be various chips for processing images, such as ASIC chips, ISP chips, etc. The processing unit 11 can be a processor, a core, etc. in the chip for performing operations on pixel data in an image. The storage unit 12 can be various memories in the chip for caching pixel data to be operated on by the processing unit, such as SRAM, DRAM, etc. In some embodiments, the storage unit can be a single-port RAM. Each cache unit can store one row of pixel data of a target image, or can store multiple rows of pixel data.

[0072] The data reading unit 12 can be various data reading controllers, etc. for controlling reading of data from the storage unit, and the data reading unit 13 can include a storage subunit 131, which can be various cache memories (such as cache). The processing unit 11 can acquire pixel data from the storage subunit 131 at a speed greater than that of acquiring pixel data from the storage unit 12, i.e., the processing unit 11 can acquire pixel data from the storage subunit 131 in less time than that of acquiring pixel data from the storage unit 12.

[0073] In processing a target image, the chip can first acquire pixel data to be used by the processing unit 11 in a period of time from a memory storing pixel data of the target image, which can be an external memory connected to the chip, or can be some non-volatile memory on the chip, and then cache the acquired pixel data in the storage unit 12. When the processing unit 11 needs to use pixel data, it can send a data reading request for reading pixel data of the target image to the data reading unit 13, and the data reading unit 13 can determine a storage address of the pixel data to be read in the storage unit 12 based on the data reading request after receiving the data reading request, and then access the storage address. For example, the data reading request can carry the storage address of the pixel data to be read, or can carry other information that can be used to determine the storage address of the pixel data to be read.

[0074] In order to reduce the area and power consumption of the chip, the number of pixel data stored in each storage address of the storage unit is increased compared with the existing storage unit, and is no longer limited to 2. Therefore, the pixel data requested by the processing unit 11 is no longer the pixel data stored in only one storage address, and is often greater than the pixel data required by the processing unit 11 in each clock cycle. Alternatively, the number of pixel data requested by the processing unit 11 can be only part of the pixel data stored in each storage address, or the pixel data requested by the processing unit 11 can be distributed in multiple storage addresses, and only part of the pixel data in each storage address is the pixel data currently requested by the processing unit 11.

[0075] For example, assuming that each storage address stores 8 pixel data (for example, pixel data 1-7 are stored), the data read request of the processing unit 11 requests only 1-2 pixel data. Alternatively, the processing unit requests 8-9 pixel data, which are respectively stored in two storage addresses. Considering that the pixel data requested by the processing unit 11 in continuous data read requests are usually adjacent, when accessing each storage address, the data reading unit 12 not only reads the pixel data currently requested by the processing unit 11, but also reads all the pixel data stored in the current storage address at one time and stores them in the storage subunit 131. Then, the pixel data currently requested by the processing unit 11 (i.e., the pixel data to be read) can be selected from the cached pixel data and output to the processing unit 11.

[0076] Since the data reading unit 13 reads all the pixel data of the storage address when accessing the storage address of the storage unit 12 at one time, it can avoid repeatedly accessing the storage unit 13 when requesting data of the same storage address again in the future, and can reduce the power consumption.

[0077] In some embodiments, the number of pixel data stored in each storage address of the storage unit 12 is greater than the number of pixel data required to be read by the processing unit 11 in each clock cycle in the process of processing the target image. In most cases, the pixel data requested by the processing unit 11 is the pixel data required to be processed in the current clock cycle, and the number thereof is often small, usually 1-2. In order to reduce the area and power consumption of the chip, the number of pixel data stored in each storage address of the storage unit 12 is often greater than 1-2, such as 8, 16 or 32, which is determined according to the resolution of the image and the bit width of each pixel data.

[0078] As introduced above, the closer the data bit width of each storage address of the storage unit 13 is to the depth of the storage addresses in the storage unit, the smaller the overall area and power consumption of the chip will be. Therefore, in order to reduce the power consumption of the chip as much as possible, in some embodiments, when designing the storage unit, the difference between the data bit width of each storage address of the storage unit and the depth of the storage addresses in the storage unit can be controlled to be less than a preset difference, wherein the data bit width can be determined based on the maximum number of pixel data that each storage address can store and the bit width of each pixel data, such as data bit width of each storage address = the maximum number of pixel data that each storage address can store × the bit width of each pixel data. The preset difference can be a value set in advance to ensure that the data bit width of each storage address of the storage unit is as close as possible to the depth of the storage addresses in the storage unit, and the specific value can be set flexibly based on the actual situation. The depth of the storage addresses refers to the number of storage addresses contained in the storage unit. Usually, the bit width of each pixel data in an image is fixed, so the data bit width of each storage address can be controlled by adjusting the number of pixel data stored by each storage address. At the same time, for the storage unit 12 used to store images of different resolutions, since the corresponding value of the data bit width of each storage address is close to the depth of the storage addresses in the storage unit 12, the number of pixel data that each storage address can store is also different, so the number of pixel data that each storage address can store can also be adjusted based on the resolution of the image that the storage unit 12 needs to store, so as to design a storage unit 12 with better adaptability for images of different resolutions.

[0079] In some embodiments, the data reading unit 13 can determine whether the pixel data to be read is cached in the storage sub-unit 131 before accessing the storage unit 12 upon receiving a data reading request from the processing unit 11. If the pixel data to be read is cached in the storage sub-unit 131, the data reading unit 13 can directly read the pixel data to be read from the storage sub-unit 131. If the pixel data to be read is not cached in the storage sub-unit 131, the data reading unit 13 can access the storage unit 12 and read all the pixel data stored in the accessed storage address. For example, assume that each storage address of the storage unit 12 stores 8 pixel data, storage address 1 stores pixel data 1-8, and storage address 2 stores pixel data 9-15. Assume that the processing unit 11 initiates a data reading request for pixel data 4-5. Upon receiving the data reading request, the data reading unit 13 can first determine whether the pixel data 4-5 is cached in the storage sub-unit 131. If the pixel data 4-5 is not cached in the storage sub-unit 131, the data reading unit 13 can access storage address 1 and read all the pixel data 1-8 stored in storage address 1. The data reading unit 13 can then cache the pixel data 1-8 in the storage sub-unit 131. When the processing unit 11 initiates a data reading request for pixel data 6-7, the data reading unit 13 can directly read the pixel data 6-7 from the storage sub-unit 131.

[0080] In some embodiments, the pixel data to be read is stored in a plurality of storage addresses. The data reading unit 13 can read all the pixel data stored in each determined storage address and cache the pixel data in the storage sub-unit 131. The data reading unit 13 can then select a portion of the pixel data to be read from each storage address from the storage sub-unit 131, and combine the pixel data selected from each storage address to obtain the pixel data to be read and output the pixel data to be read. For example, assume that each storage address of the storage unit 12 stores 8 pixel data, storage address 1 stores pixel data 1-8, and storage address 2 stores pixel data 9-15. Assume that the processing unit 11 initiates three data reading requests for pixel data 4-5, 6-7, and 8-9. When the processing unit 11 initiates a data reading request for pixel data 4-5, the data reading unit 13 can read pixel data 1-8 from storage address 1 and cache the pixel data 1-8 in the storage sub-unit 131. When the processing unit 11 initiates a data reading request for pixel data 6-7, the data reading unit 13 can directly read the pixel data 6-7 from the storage sub-unit 131. When the processing unit 11 initiates a data reading request for pixel data 8-9, the data reading unit 13 can access storage address 2, read pixel data 9-17 from storage address 2, and cache the pixel data 9-17 in the storage sub-unit 131. The data reading unit 13 can then select pixel data 9 from the pixel data 9-17 cached in the storage sub-unit 131, combine the pixel data 9 with pixel data 8 cached in the storage sub-unit 131, and output the combined pixel data 8-9 to the processing unit 11.

[0081] In the current image processing process, when the processing unit 11 sends a data reading request to the data reading unit 13, the processing unit 11 usually carries the storage address of the pixel data to be read in the storage unit 12 in the data reading request. Since there is no cache subunit 131 in the previous data reading unit 13, the processing unit 11 directly obtains the pixel data from the storage unit 12, and thus the processing unit 11 usually sends a data reading request when the pixel data is needed, and each request carries only one storage address, and only requests 1-2 pixel data to be processed. That is, in the previous technology, the processing unit 11 can only obtain the pixel data of one storage address in the storage unit 12 each time. This data request method has the following disadvantages: one is that the processing unit 11 needs to calculate the storage address multiple times and then continuously sends data reading requests to the data reading unit 13, which makes the data reading inconvenient and the timing of the read data is also relatively chaotic. Another is that the processing unit 11 directly requests the storage address, which is more abstract than the position of the pixel in the image and is not easy to understand, and it is easy to cause redundant design when the chip code is designed by programmers.

[0082] Since the data to be processed by the processing unit 11 in a period of time is usually a continuous segment of pixel data, in some embodiments, when the processing unit 11 sends a data reading request to the data reading unit 13, the data reading request can carry the position information of the starting pixel in the target image in the pixel data to be read and the number of pixel data to be read. The data reading unit 13 can pre-store the mapping relationship between the position information of the pixel point in the target image in the target image and the storage address of the pixel point in the storage unit 12, and then determine the storage address of the starting pixel based on the position information of the starting pixel in the target image and the mapping relationship. Since continuous pixels are usually stored in continuous storage addresses, the storage address of the one or more storage addresses storing all the pixel data to be read can be determined based on the storage address of the starting pixel, the number of pixel data stored in each storage address, and the number of pixel data to be read. After determining the one or more storage addresses of the pixel data to be read, the data reading unit 13 can automatically initiate multiple data reading operations, i.e., multiple accesses to the storage unit 12, to read all the pixel data to be read.

[0083] For example, assuming that the processing unit 11 processes image rows pixel by pixel, and each row has 8192 pixels, in the prior art, the processing unit 11 needs to initiate a data read request each time according to the processing timing, and the request carries a storage address and requests 2 pixels. After processing the pixels in this row, the processing unit 11 needs to initiate 4096 requests in total. In the manner of the embodiment, the processing unit 11 can initiate a request, which indicates the starting pixel position of the image (for example, the first column in the Nth row) and indicates that the number of pixels to be read is 8192. After receiving the request, the data read unit 13 automatically determines the storage address of the pixels in this row, and then automatically initiates multiple read operations to read the pixel data from each storage address until the pixel data in this row is read and then stored in the storage subunit 131.

[0084] In this way, the data read operation can be simplified, and the processing unit 11 only needs to send one data read request to read a segment of pixel data, so that the data read is more flexible.

[0085] In the image processing process, the pixel data at the same position in multiple rows is usually processed. For example, a 5x5 image window is used to process the image, and 5 pixels at the same position in 5 rows are processed each time. Therefore, in some embodiments, one data read request can be used to request pixel data in multiple rows. As shown in Figure 3 As shown in Figure 3As shown, the first row of pixel data of the target image can be stored in storage unit 1, and the second row of pixel data can be stored in storage unit 2. The processing unit 11 can also request multiple rows of pixel data at a time when requesting the data. For example, the data read request can also include the number of rows of pixel data to be read, and the data read unit 13, upon receiving the data read request, can determine the storage unit 12 for storing each row of pixel data to be read, and determine one or more storage addresses from the determined storage unit 12 based on the position information of the starting pixel in the target image and the number of pixel data to be read in the data read request. Since image processing is usually performed on an image block, such as a 5x5 image block, a request can be to request pixel data in the same column in different rows (e.g., 5 rows of 5 columns of pixel data). Therefore, when sending the data read request, the data read unit 13 only needs to be told the position information of the starting pixel in the target image in the first row, the number of pixel data to be read in the row, and the number of rows, and the data read unit 13 then knows the number of pixel data to be read in the same column in the next 4 rows. Of course, the position information of the starting pixel in the target image can also be the starting pixel of the last row, the number of pixel data to be read can also be the total number of rows, etc., as long as the position of all pixel data to be read in the image can be determined based on this information, which can be flexibly set.

[0086] After the data read unit 13 reads the pixel data requested by the processing unit 11 from the storage unit 12, it can be stored in the cache subunit 131, and then output from the cache subunit 131 to the processing unit 11. In the prior art, when the processing unit 11 needs to use the pixel data, it sends a data read request to the data read unit 13, and the data read unit 13 reads the pixel data from the storage unit 12 and returns it to the processing unit 11 after receiving the data read request. Since it takes a long time to obtain pixel data from the storage unit 12, it takes a long time to obtain pixel data, and if the operation result needs to be returned in a fixed clock cycle, the processing unit 11 has a short time to perform the operation, resulting in poor timing of the overall processing process. Therefore, in some embodiments, the data read unit 13 can be configured to read the pixel data from the storage unit 12 and store it in the cache subunit 131 in advance, and then output it to the processing unit 11 when the processing unit 11 needs to use the pixel data. Figure 4As shown, the data reading unit 13 further comprises a FIFO register 132. The processing unit 11 can send a data reading request in advance. After receiving the data reading request, the data reading unit 13 can read all the pixel data stored in the storage address from the storage unit 12, and store the pixel data in the storage subunit 131. Then, the data reading unit 13 can select the pixel data to be read (i.e. the pixel data requested by the processing unit) from all the pixel data, and store the pixel data to be read in the FIFO register 132. Since the FIFO register is closer to the processing unit 11, the speed of reading the pixel data from the FIFO register 132 is faster than that of reading the pixel data from the storage unit 12 or the storage subunit 131. Therefore, when the processing unit 11 needs to use the pixel data, the processing unit 11 can obtain the pixel data from the FIFO register 132, so that the speed of obtaining the pixel data is faster, and more time is available for calculation.

[0087] In the prior art, after the data reading unit 13 obtains the pixel data from the storage unit 12, the data reading unit 13 outputs the pixel data to the processing unit 11. At this time, the processing unit 11 can not be ready to receive the data. For example, the processing unit 11 can need to wait for other pixel data to be available before starting processing. If the pixel data is directly returned to the processing unit 11, the processing unit 11 can not need to use the pixel data at present, and thus the register resource of the processing unit 11 is occupied. In view of the above problem, in an embodiment, a handshake mechanism between the processing unit 11 and the data reading unit 13 can be established. After the data reading unit 13 reads the pixel data requested by the processing unit 11 from the storage unit 12, the data reading unit 13 can first output the pixel data to the FIFO register 132, and then return a first signal to the processing unit 11. The first signal is used to indicate that the pixel data requested is in an available state. When the processing unit 11 is ready to receive the pixel data (for example, other pixel data is available), the processing unit 11 can send a second signal to the data reading unit 13. The second signal is used to indicate that the processing unit 11 is ready to receive the data. After receiving the second signal, the data reading unit 13 can output the pixel data buffered in the FIFO register to the processing unit 11.

[0088] In some embodiments, since the pixel data stored in the FIFO register can not be taken away in time, if the FIFO register in the data reading unit is full of pixel data, i.e. there is no available storage space in the FIFO register, the data reading unit 13 can stop reading the pixel data from the storage unit 12.

[0089] Because the amount of pixel data stored at each address in storage unit 12 has increased, the writing method for writing pixel data to storage unit 12 also needs to be adjusted accordingly. In some embodiments, such as Figure 5 As shown, the image processing chip 10 also includes a data writing unit 14. The data writing unit 14, upon receiving a data write request from the processing unit 11, retrieves one or more rows of pixel data of the target image from a memory storing the target image and writes them into the storage unit 12. The memory storing the pixel data of the target image can be an external memory connected to the chip, or it can be some non-volatile memory on the chip. The data writing unit 14 can be a controller for controlling the writing of image data to the storage unit 12. The data writing unit 14 and the data reading unit 13 can be integrated into one hardware component or can be two independent hardware components.

[0090] When writing pixel data of a target image to storage unit 12, for each row of pixel data in the target image, data writing unit 14 can sequentially acquire each pixel data in that row from left to right. The number of pixel data acquired by data writing unit 14 per clock cycle can be flexibly set, as long as it does not exceed the target number of pixel data that each storage address of storage unit 12 can store. At the same time, data writing unit 14 can count in real time the number of pixel data that has been acquired but not yet written to the storage unit (hereinafter referred to as target pixel data). If the number of target pixel data is greater than or equal to the target number, a write operation is performed, writing the first target number of pixel data from the target pixel data to a storage address of storage unit 12.

[0091] For example, suppose each memory address of memory cell 12 can store 8 pixels of data, and each clock cycle, data writing unit 14 can acquire 3 pixels of data. Each time pixel data is acquired, data writing unit 14 can count the number of target pixel data that has been acquired but not yet written to the memory cell. For example, in the first three clock cycles, the cumulative number of target pixel data is 3, 6, and 9 respectively. In the first two clock cycles, the number of target pixel data is less than 8, so no write operation is performed. In the third clock cycle, the number of target pixel data is greater than 8, so a write operation can be performed to write the first 8 pixels of data to a memory address of memory cell 14.

[0092] Of course, since the number of pixel data to be written can not be exactly divisible by the number of pixel data that each storage address of the storage unit 12 can store. Therefore, in some embodiments, the data writing unit 14 also performs a write operation to write the target pixel data into one storage address of the storage unit 12 in the case where it is counted that the number of target pixel data is less than the target number and it is determined that all the pixel data to be written has been acquired.

[0093] For example, assuming that each storage address of the storage unit 12 can store 8 pixel data, to write a row of pixel data into one storage unit 12, assuming that a row of pixel data is 8196, when performing a write operation every time 8 pixel data is accumulated to write the row of pixel data into the storage unit 12, there will still be 4 pixel data at the end of the row. In this case, even if the target pixel data is less than 8, a write operation will be performed.

[0094] In addition, the present disclosure also provides an image processing chip, such as Figure 6 As shown, the image processing chip includes a processing unit 11, a storage unit 12, a data writing unit 14,

[0095] The processing unit 11 is configured to send a data writing request of writing pixel data of a target image into the storage unit 12 to the data writing unit 14;

[0096] The data writing unit 14 repeatedly performs the following operations after receiving the data writing request until all the pixel data to be written is written into the storage unit 12:

[0097] acquire pixel data in the image row of the target image in sequence, wherein the number of pixel data acquired in each clock cycle is not greater than a target number, and the target number is the number of pixel data that each storage address of the storage unit can store;

[0098] In the case where it is counted that the number of target pixel data that has been acquired and not written into the storage unit is greater than or equal to the target number, a write operation is performed to write the first target number of pixel data in the target pixel data into one storage address of the storage unit.

[0099] In some embodiments, the data writing unit 14 is further configured to:

[0100] In the case where it is counted that the number of target pixel data is less than the target number and it is determined that all the pixel data to be written has been acquired, a write operation is performed to write the target pixel data into one storage address of the storage unit.

[0101] Correspondingly, the embodiment of the present disclosure also provides a memory for storing pixel data of an image, a data bit width of each storage address of the memory is less than a preset difference from a depth of a storage address in the memory, wherein the data bit width is determined based on a number of pixel data that can be stored by each storage address and a bit width of each pixel data. Using the memory as an on-chip storage unit of an image processing chip can reduce the area and power consumption overhead of the chip.

[0102] Correspondingly, the embodiment of the present disclosure provides an image processing chip, which comprises a processor and the memory mentioned in the above embodiment, the memory is used for storing pixel data of an image, a data bit width of each storage address of the memory is less than a preset difference from a depth of a storage address in the memory, wherein the data bit width is determined based on a number of pixel data that can be stored by each storage address and a bit width of each pixel data. Using the memory as an on-chip storage unit of an image processing chip can reduce the area and power consumption overhead of the chip.

[0103] Correspondingly, the embodiment of the present disclosure also provides a data reading method for reading pixel data of a target image from a memory, the method comprises the following steps:

[0104] receiving a data reading request;

[0105] determining a storage address of the pixel data to be read in the memory based on the data reading request, accessing the storage address and reading and caching all the pixel data stored in the storage address;

[0106] selecting the pixel data to be read from the cached all the pixel data and outputting.

[0107] In some embodiments, the number of pixel data stored by each storage address in the memory is greater than the number of pixel data required in each clock cycle in the process of processing the target image.

[0108] In some embodiments, a data bit width of each storage address in the memory is less than a preset difference from a depth of a storage address in the memory, wherein the data bit width is determined based on a number of pixel data that can be stored by each storage address and a bit width of each pixel data.

[0109] In some embodiments, the all the pixel data is cached in a cache memory, and the accessing the storage address and reading all the pixel data stored in the storage address comprises:

[0110] In a case where it is determined that the to-be-read pixel data is cached in the cache memory, the to-be-read pixel data is acquired from the cache memory; otherwise, the storage address is accessed and all pixel data stored in the storage address is read.

[0111] In some embodiments, the to-be-read pixel data is stored in a plurality of storage addresses, the all pixel data read is cached in the cache memory, and the to-be-read pixel data is selected from the cached all pixel data and output, comprising:

[0112] For each storage address, all pixel data read from the storage address is cached in the cache memory;

[0113] The to-be-read pixel data read from each storage address is selected from the cache memory and spliced to obtain the to-be-read pixel data and output.

[0114] In some embodiments, the data read request carries position information of a starting pixel in the to-be-read pixel data in the target image, a quantity of the to-be-read pixel data, the storage address of the to-be-read pixel data in the storage is determined based on the data read request, comprising:

[0115] The one or more storage addresses for storing the to-be-read pixel data in the storage are determined based on the position information of the starting pixel in the target image, a mapping relationship between a position of a pixel in the target image and a storage address of the target image, and the quantity.

[0116] In some embodiments, the storage has a plurality of storage, each of the storage is used to store a row of pixel data of the target image, the data read request further includes a row number of the to-be-read pixel data, the one or more storage addresses for storing the to-be-read pixel data in the storage are determined based on the position information of the starting pixel in the target image and the quantity, comprising:

[0117] For each row of pixel data in the to-be-read pixel data, a storage for storing the row of pixel data is determined, the one or more storage addresses for storing the to-be-read pixel data in the storage are determined based on the position information of the starting pixel in the target image, a mapping relationship between a position of a pixel in the target image and a storage address of the target image, and the quantity.

[0118] In some embodiments, the to-be-read pixel data is selected from the cached all pixel data and output, comprising:

[0119] selecting the to-be-read pixel data from the all pixel data stored in the cache, and storing the to-be-read pixel data in a FIFO register, so as to output the to-be-read pixel data through the FIFO register.

[0120] In some embodiments, after storing the to-be-read pixel data in the FIFO register, the method further includes:

[0121] returning a first signal to a processor for processing the pixel data, the first signal being used to indicate that the to-be-read pixel data is in an available state;

[0122] outputting the to-be-read pixel data to the processor after receiving a second signal sent by the processor, the second signal being used to indicate that the processor is in a state of being able to receive the to-be-read pixel data.

[0123] In some embodiments, the method further includes:

[0124] stopping reading pixel data from the memory in the case that the FIFO register has no available storage space.

[0125] In some embodiments, the memory includes a single-port static random access memory (SRAM). The data reading method can be executed by an image processing chip, such as a processor of the image processing chip or a controller specially used for controlling reading data from the memory. The specific implementation details of reading pixel data from the memory can refer to the descriptions of the embodiments of the image processing chip, which will not be described here.

[0126] Correspondingly, the disclosure also provides a data writing method for writing to-be-written pixel data of a target image into a memory, the method including the following steps:

[0127] repeating the following operations until the to-be-written pixel data are all written into the memory:

[0128] sequentially obtaining pixel data in each image row of the target image, wherein the number of pixel data obtained in each clock cycle is not greater than a target number, and the target number is the number of pixel data that can be stored in each storage address of the memory.

[0129] in the case that the number of target pixel data that have been obtained and not written into the memory is greater than or equal to the target number, performing a writing operation to write the first target number of pixel data in the target pixel data into one storage address of the memory.

[0130] In some embodiments, the method further includes:

[0131] In a case where the number of the target pixel data is less than the target number and it is determined that all the pixel data to be written has been acquired, a write-once operation is performed to write the target pixel data into one storage address of the memory.

[0132] The data reading method can be executed by an image processing chip, for example, a processor of the image processing chip, or a controller specially used for controlling writing of data into the memory. Details of writing data into the memory can refer to descriptions of the image processing chip in the above embodiments, which will not be repeated here.

[0133] It can be understood that the schemes described in the above embodiments can be combined in the absence of conflicts, and the embodiments of the present disclosure will not be repeated one by one.

[0134] In addition, the embodiments of the present disclosure also provide a board card including a packaging structure in which at least one image processing chip mentioned in the above embodiments is packaged, or at least one memory mentioned in the above embodiments. Refer to Figure 7 which provides an exemplary board card, and the above board card includes the image processing chip 700, and can further include other components, including but not limited to: a memory device 702, an interface device 704, and a control device 706.

[0135] The memory device 702 is connected to the image processing chip 700 in the image processing chip packaging structure through a bus, and is used for storing data. The memory device 702 can include a plurality of groups of storage units 7021, for example, DDR SDRAM (English: Double Data Rate SDRAM, double data rate synchronous dynamic random access memory) and the like. Each group of storage units 7021 is connected to the image processing chip 700 through a bus.

[0136] The interface device 704 is electrically connected to the image processing chip 700 in the chip packaging structure. The interface device 704 is used to realize data transmission between the image processing chip and an external device 800 (for example, a terminal, a server, a camera, and the like). In an embodiment, the interface device 704 can include a PCIE interface, and can also be a network interface or other interfaces, which are not limited by the present disclosure.

[0137] The control device 706 is electrically connected to the chip 700 in the image processing chip packaging structure. The control device 706 can be an MCU or the like, which is not limited by the present disclosure.

[0138] The embodiment of the present disclosure further provides a computer readable storage medium, which stores a computer program, and the program is executed by a processor to implement the method in any of the foregoing embodiments.

[0139] The embodiment of the present disclosure further provides an electronic device, which comprises at least one chip mentioned in each of the foregoing embodiments, or comprises at least one memory mentioned in each of the foregoing embodiments, or comprises at least one board card mentioned in each of the foregoing embodiments.

[0140] Computer readable media includes permanent and non-permanent, removable and non-removable media, which can be implemented by any method or technology to store information. The information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information accessible by a computing device. According to the definition herein, computer readable media does not include transitory computer readable media, such as modulated data signals and carriers.

[0141] From the above description of the embodiments, those skilled in the art can clearly understand that the embodiments of the present disclosure can be implemented by means of software plus necessary universal hardware platforms. Based on such an understanding, the technical solutions of the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in each embodiment or some parts of the embodiments of the present disclosure.

[0142] The system, device, module or unit illustrated in the foregoing embodiments can be specifically implemented by a computer chip or entity, or by a product with certain functions. A typical implementation device is a computer, and the specific form of the computer can be a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email transceiver device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0143] The various embodiments described in the specification are progressive in nature, and each of the embodiments can be incorporated into the other embodiments, as appropriate, unless described otherwise. For example, the method embodiments can be applicable to the device embodiments, and vice versa. In particular, the device embodiments are described in less detail, as they are substantially similar to the method embodiments. The device embodiments described above are merely exemplary, in which the modules described as separate components can or can not be physically separate, and the functions of the modules can be implemented in one or more software and / or hardware in implementing the embodiments of the present disclosure. Some or all of the modules can be selected to achieve the purposes of the embodiments of the present disclosure, as appropriate. Those of ordinary skill in the art can understand and implement without creative effort.

[0144] The above is merely a specific implementation of the embodiments of the present disclosure, and it should be noted that those of ordinary skill in the art can make several improvements and refinements without departing from the principles of the embodiments of the present disclosure, and these improvements and refinements should also be considered within the protection scope of the embodiments of the present disclosure.

Claims

1. An image processing chip, characterized by, The image processing chip comprises a processing unit, a storage unit and a data reading unit, the data reading unit comprises a storage subunit; The storage unit is configured to store pixel data of a target image; The processing unit is configured to send a data reading request for reading pixel data of the target image to the data reading unit; The data reading unit is configured to determine a storage address of the pixel data to be read in the storage unit based on the data reading request, access the storage address and read all pixel data stored in the storage address, cache the read all pixel data in the storage subunit, and select the pixel data to be read from the cached all pixel data and output; The image processing chip further comprises a data writing unit, the data writing unit is configured to receive a data writing request sent by the processing unit, repeatedly execute the following operations until all pixel data to be written are written into the storage unit: Obtain pixel data in each image row of the target image in sequence, wherein the number of pixel data obtained in each clock cycle is not greater than a target number, and the target number is the number of pixel data that can be stored in each storage address of the storage unit; In a case where it is counted that the number of target pixel data that has been obtained and not written into the storage unit is greater than or equal to the target number, perform a write operation once to write the first target number of pixel data in the target pixel data into one storage address of the storage unit.

2. The image processing chip of claim 1, wherein, The number of pixel data stored in each storage address of the storage unit is greater than the number of pixel data required by the processing unit in each clock cycle in the process of processing the target image.

3. The image processing chip of claim 1, wherein, The difference between the data bit width of each storage address in the storage unit and the depth of the storage address in the storage unit is less than a preset difference, wherein the data bit width is determined based on the number of pixel data that can be stored in each storage address and the bit width of each pixel data.

4. The image processing chip of claim 1, wherein, When the data reading unit is used to access the storage address and read all pixel data stored in the storage address, it is specifically used to: In a case where it is determined that the pixel data to be read is cached in the storage subunit, obtain the pixel data to be read from the storage subunit; otherwise, access the storage address and read all pixel data stored in the storage address.

5. The image processing chip of claim 1, wherein, The pixel data to be read is stored in a plurality of storage addresses, and when the data reading unit is used to cache all pixel data read in the storage subunit and select the pixel data to be read from the cached all pixel data and output, it is specifically used to: For each storage address, cache all pixel data read from the storage address in the cache subunit; Select a part of the pixel data to be read from each storage address from the cache subunit and splice to obtain the pixel data to be read and output.

6. The image processing chip according to any of claims 1-5, characterized in that, The data reading request carries position information of a starting pixel in the target image in the pixel data to be read, and a quantity of the pixel data to be read, and the data reading unit is configured to determine one or more storage addresses of the storage unit for storing the pixel data to be read based on the position information of the starting pixel in the target image, a mapping relationship between positions of pixels in the target image and storage addresses of the target image, and the quantity. The data reading unit is configured to determine one or more storage addresses of the storage unit for storing the pixel data to be read based on the position information of the starting pixel in the target image, a mapping relationship between positions of pixels in the target image and storage addresses of the target image, and the quantity.

7. The image processing chip of claim 6, wherein, The image processing chip comprises a plurality of storage units, each of which is configured to store one row of pixel data of the target image, and the data reading request further comprises a row number of the pixel data to be read, and the data reading unit is configured to determine one or more storage addresses of the storage unit for storing the pixel data to be read based on the position information of the starting pixel in the target image and the quantity. The data reading unit is configured to determine one or more storage addresses of the storage unit for storing the pixel data to be read based on the position information of the starting pixel in the target image, a mapping relationship between positions of pixels in the target image and storage addresses of the target image, and the quantity.

8. The image processing chip of claim 1, wherein, The data reading unit further comprises a FIFO register, and the data reading unit is configured to select the pixel data to be read from the buffered entire pixel data and output the pixel data to be read, and specifically configured to: select the pixel data to be read from the buffered entire pixel data, and store the pixel data to be read in the FIFO register, so as to output the pixel data to be read through the FIFO register.

9. The image processing chip of claim 8, wherein, After storing the pixel data to be read in the FIFO register, the data reading unit is further configured to: return a first signal to the processing unit, the first signal being used to indicate that the pixel data to be read is in an available state; output the pixel data to be read to the processing unit after receiving a second signal sent by the processing unit, the second signal being used to indicate that the processing unit is in a state of being able to receive the pixel data to be read.

10. The image processing chip according to claim 8 or 9, characterized in that, In the case that there is no available storage space in the FIFO register, stop reading pixel data from the storage unit.

11. The image processing chip of claim 1, wherein, The storage unit comprises a single-port static random access memory (SRAM).

12. The image processing chip of claim 1, wherein, The data writing unit is further configured to: in the case that it is determined that the quantity of the target pixel data is less than the target quantity and that the pixel data to be written has been completely acquired, perform a one-time write operation to write the target pixel data into one storage address of the storage unit.

13. A memory, comprising: The storage unit is configured to constitute the storage unit in the image processing chip according to any one of claims 1 to 12. The memory is configured to store pixel data of an image, and a data bit width of each storage address of the memory is less than a preset difference from a depth of the storage address in the memory, wherein the data bit width is determined based on a number of pixel data that can be stored by each storage address and a bit width of each pixel data.

14. An image processing chip, characterized by The image processing chip comprises a processor and the memory of claim 13.

15. A board card, characterized by The board card comprises a packaging structure in which at least one image processing chip of any one of claims 1-12 or 14 is packaged, or the board card comprises a packaging structure in which at least one memory of claim 13 is packaged.

16. An electronic device, comprising: The electronic device comprises at least one image processing chip of any one of claims 1-12 or 14, or comprises at least one memory of claim 13, or comprises at least one board card of claim 15.

17. A data reading method, characterized by, The method is applied to the image processing chip of any one of claims 1-12, and is configured to read pixel data of a target image from the memory, and the method comprises: receiving a data read request; determining, based on the data read request, a storage address of the pixel data to be read in the memory, accessing the storage address, reading all pixel data stored in the storage address, and caching; selecting the pixel data to be read from the cached all pixel data and outputting.

18. A data writing method, characterized by, The method is applied to the image processing chip of any one of claims 1-12, and is configured to write pixel data to be written of a target image into the memory, and the method comprises: repeatedly performing the following operations until the pixel data to be written is all written into the memory: obtaining pixel data in each image row of the target image in sequence, wherein a number of pixel data obtained in each clock cycle is not greater than a target number, and the target number is a number of pixel data that can be stored by each storage address of the memory; in a case where a number of target pixel data that has been obtained and not written into the memory is greater than or equal to the target number, performing a write operation once to write a first target number of pixel data in the target pixel data into one storage address of the memory.

19. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the method of any one of claims 17 or 18.

Images