Non-volatile memory device for performing dual-sensing operations

Abstract

The present disclosure relates to a non-volatile memory device for performing dual-sensing operation. A non-volatile memory device includes a cell string including a plurality of memory cells, a bit line coupled to the cell string, and a page buffer adapted to pre-charge the bit line, a first sensing node, and a second sensing node to a preset level in a first period, and to perform dual-sensing of the bit line through the first sensing node and the second sensing node in a second period, wherein the page buffer includes a first coupling unit adapted to couple the bit line and the first sensing node, a second coupling unit adapted to couple the first sensing node and the second sensing node, and to control the first sensing node and the second sensing node to have a voltage level interval according to a preset ratio in the second period, and first and second latching units adapted to latch logic levels corresponding to voltage levels of the first sensing node and the second sensing node, respectively.

Description

TECHNICAL FIELD

[0001] Various embodiments relate to a semiconductor device, and more particularly, to a nonvolatile memory device for performing a dual sensing operation. BACKGROUND

[0002] A semiconductor memory device is a memory device implemented using a semiconductor such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP). The semiconductor memory device can be roughly classified into a volatile memory device and a nonvolatile memory device.

[0003] A nonvolatile memory device indicates a memory device that retains data stored therein even if power supplied thereto is removed. Examples of the nonvolatile memory device can include ROM (Read Only Memory), PROM (Programmable ROM), EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), a flash device, PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), and FRAM (Ferroelectric RAM). The flash can be roughly classified into NOR flash and NAND flash.

[0004] Among nonvolatile memory devices, a flash device can store data in a memory cell by controlling an amount of electric charge remaining in a conduction band of a floating gate so that a threshold voltage of the memory cell changes. That is, when a program pulse is applied to the floating gate, the threshold voltage of the memory cell can increase. By using the program pulse, the flash device can change the threshold voltage of the memory cell according to a value of data to be stored in the memory cell. However, the nonvolatile memory device can include a plurality of memory cells, and the memory cells can have different characteristics. Accordingly, the threshold voltages of the memory cells in which the same data is stored can have a predetermined distribution rather than one value. SUMMARY

[0005] Various embodiments relate to a nonvolatile memory device capable of performing a dual sensing operation by using two sensing voltages at a time.

[0006] The technical problems to be solved by the disclosure are not limited to those mentioned above, and other technical problems not mentioned can be clearly understood by those skilled in the art to which the disclosure pertains from the following description.

[0007] According to an embodiment of the present application, a nonvolatile memory device can include a cell string including a plurality of memory cells coupled in series, a bit line coupled to the cell string, and a page buffer adapted to pre-charge the bit line, a first sensing node, and a second sensing node to a preset level in a first period, and to double sense the bit line through the first sensing node and the second sensing node in a second period. The page buffer can include a first coupling unit adapted to couple the bit line and the first sensing node in response to a first control signal, a second coupling unit adapted to couple the first sensing node and the second sensing node in response to a second control signal, and to control the first sensing node and the second sensing node to have a voltage level interval according to a preset ratio in the second period, a first latching unit adapted to latch a logic level corresponding to a voltage level of the first sensing node in response to a third control signal, and a second latching unit adapted to latch a logic level corresponding to a voltage level of the second sensing node in response to a fourth control signal.

[0008] The second coupling unit can include a switch adapted to selectively couple the first sensing node and the second sensing node in response to the second control signal, and a capacitor coupled in parallel with the switch between the first sensing node and the second sensing node.

[0009] The switch can include an NMOS transistor adapted to selectively couple the first sensing node and the second sensing node connected to a drain and a source of the NMOS transistor in response to the second control signal applied to a gate of the NMOS transistor.

[0010] The page buffer can further include a third coupling unit adapted to selectively couple a core voltage terminal and the first sensing node in response to a fifth control signal, and can further include a control signal generator adapted to generate the first control signal to the fifth control signal.

[0011] The control signal generator can be further adapted to activate the first control signal, the second control signal, and the fifth control signal in the first period, to deactivate the second control signal and the fifth control signal and activate the first control signal in a third period included in the second period, and to deactivate the first control signal, the second control signal, and the fifth control signal and switch the third control signal and the fourth control signal in a fourth period included in the second period and following the third period.

[0012] The page buffer can pre-charge the bit line and the first and second sense nodes to a core voltage level by coupling the bit line and the first and second sense nodes via the first through third coupling units to the core voltage terminal in the first period. The page buffer can further be adapted to evaluate voltage levels of the bit line and the first sense node by decoupling the first sense node from the core voltage terminal via the third coupling unit and coupling the bit line and the first sense node via the first coupling unit in the third period. The page buffer can control the first and second sense nodes to have voltage level intervals according to a preset ratio by coupling the first and second sense nodes via the capacitor of the second coupling unit in the third period. The page buffer can further be adapted to decouple the first sense node from the core voltage terminal and couple the first sense node and the bit line by the first and third coupling units and latch logic levels corresponding to voltage levels of the first and second sense nodes in the first and second latch units, respectively, in response to switching of the third and fourth control signals in the fourth period.

[0013] The control signal generator can further be adapted to activate the first and second control signals and deactivate the fifth control signal in a fifth period included in the second period and before the third period.

[0014] The page buffer can further be adapted to evaluate voltage levels of the bit line and the first and second sense nodes by decoupling the first sense node from the core voltage terminal via the third coupling unit and coupling the bit line and the first and second sense nodes via the first and second coupling units in the fifth period.

[0015] The control signal generator can further be adapted to adjust a length of the fifth period by adjusting a length of a period in which the second control signal is activated while the first control signal is activated and the fifth control signal is deactivated.

[0016] The page buffer can further use a ratio of respective lengths of the third and fifth periods as the preset ratio.

[0017] The page buffer can control the first and second sense nodes to have greater voltage level intervals by reducing a length of the fifth period and increasing a length of the third period. The page buffer can control the first and second sense nodes to have smaller voltage level intervals by increasing a length of the fifth period and reducing a length of the third period.

[0018] According to an embodiment of the present application, a nonvolatile memory device can include a bit line coupled to a cell string, a page buffer including a coupling circuit including a switching element and a capacitive element coupled in parallel between a first node and a second node, first and second latching circuits coupled to the respective first and second nodes, and a control circuit configured to pre-charge the bit line and the first and second nodes by providing a pre-charge voltage to the first node coupled to the bit line and turning on the switching element, and after the pre-charge, electrically isolate the first node from the bit line while controlling the first and second latching circuits to latch logic levels of the respective first and second nodes. The control circuit can be further configured to turn off the switching element after the pre-charge and before the electrical isolation of the first node from the bit line. The latched logic levels can be used for a double sensing operation for memory cells of the cell string.

[0019] According to the present embodiment, the nonvolatile memory device can divide a sensing node of a page buffer for sensing a program state of a memory cell into two nodes selectively coupled according to a control signal, and control the two nodes to have a voltage level interval as a result of a first sensing operation according to a preset ratio, thereby performing a double sensing operation using two sensing voltages at a time.

[0020] Such an operation can significantly reduce a time required to perform a double sensing operation. BRIEF DESCRIPTION OF DRAWINGS

[0021] FIG. 1A is a graph illustrating a distribution of threshold voltages of a multi-level cell each capable of storing 2-bit data therein.

[0022] FIG. 1B is a graph for describing a double sensing operation.

[0023] FIG. 2 is a graph illustrating a configuration of a nonvolatile memory device according to an embodiment.

[0024] FIG. 3 is a graph for describing a feature operation of the nonvolatile memory device according to the present embodiment. FIG. 2

[0025] FIG. 4 is a graph illustrating a configuration of a page buffer included in the nonvolatile memory device according to the present embodiment. FIG. 3

[0026] FIG. 5 is a graph for describing an example of an operation of the nonvolatile memory device according to the present embodiment.

[0027] ​​FIG. 6A and FIG. 6B is a diagram for describing another example of an operation of a nonvolatile memory device according to the present embodiment.

[0028] FIG. 7A and FIG. 7B is a diagram for comparing and describing an operation of a nonvolatile memory device according to the present embodiment and an operation of a nonvolatile memory device according to the related art.

[0029] FIG. 8A is a diagram for describing a double sensing operation applied during a read process.

[0030] FIG. 8B is a diagram for describing a double sensing operation applied after a retention time. DETAILED DESCRIPTION

[0031] Various examples of the present disclosure are described in greater detail below with reference to the accompanying drawings. However, aspects and features of the present application can be implemented in different ways to form other embodiments including variations of any disclosed embodiments. Therefore, the present application is not limited to the embodiments set forth herein. Rather, the described embodiments are provided so that the present disclosure is thorough and complete, and to fully convey the present disclosure to those skilled in the art to which the present application pertains. Throughout the present disclosure, like reference numerals refer to like parts throughout the various drawings and examples of the present disclosure. It is noted that references to "an embodiment," "another embodiment," etc. do not necessarily refer to the same embodiment, and that different references to any such phrases do not necessarily refer to the same embodiment.

[0032] It will be understood that, although the terms "first," "second," "third," etc. can be used herein to identify various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element in one example can be called a second element or a third element in another example without indicating any order of elements.

[0033] The drawings are not necessarily to scale and, in some instances, proportions can have been exaggerated in order to illustrate features more clearly. When an element is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or be indirectly on or connected to the other element through one or more intervening elements. Further, it will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements or one or more intervening elements can also be present.

[0034] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the word "or" is intended to mean either or both of the items it connects.

[0035] It will also be understood that the terms "comprising," "including," "having" and "with" when used herein, specify the presence of stated elements and do not preclude the presence or addition of one or more other elements, regardless of whether the other elements are related to the stated elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0036] Unless otherwise defined, all terms used in disclosing elements of the application, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art in the field of the application to which this application belongs in view of the present disclosure. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and should not be interpreted in an overly legal sense unless expressly so defined herein.

[0037] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the application. The application can be practiced without some or all of these specific details. In other instances, well known process structures and / or processes have not been described in detail in order not to unnecessarily obscure the application.

[0038] It should also be noted that, in some instances, features or elements related to one embodiment can be used singularly or in combination with other features or elements of another embodiment, as would be apparent to one of ordinary skill in the relevant art, unless otherwise specifically indicated.

[0039] Embodiments of the present disclosure are described in detail below with reference to the attached drawing figures, wherein the same or like reference numerals are used to denote similar elements throughout the several views.

[0040] FIG. 1A are graphs illustrating threshold voltage distributions of multi-level cells each capable of storing 2 bits of data therein.

[0041] As FIG. 1AAs shown, the memory cells have different threshold voltages depending on the program state of the memory cells. The threshold voltage level of the memory cell in the erase state ERA can be lower than the first voltage level PV1, the threshold voltage level of the memory cell in the first program state PG1 can be higher than the first voltage level PV1 and lower than the second voltage level PV2, the threshold voltage level of the memory cell in the second program state PG2 can be higher than the second voltage level PV2 and lower than the third voltage level PV3, and the threshold voltage level of the memory cell in the third program state PG3 can be higher than the third voltage level PV3. The erase state ERA and the first to third program states PG1 to PG3 indicate states in which data having different values is stored in the respective memory cells.

[0042] The first to third voltage levels PV1 to PV3 can be used as reference voltages for determining which state among the erase state ERA and the first to third program states PG1 to PG3 the memory cell has. Thus, when verifying whether the memory cell is normally programmed or when reading data stored in the memory cell, a sensing operation using the first to third voltages PV1 to PV3 can be performed.

[0043] In an embodiment, the sensing operation during the programming process for the memory cell can be performed as follows: a program pulse can be applied to the word line corresponding to the memory cell to be programmed, and then a sensing voltage can be applied to the word line corresponding to the memory cell to be programmed in order to verify whether the memory cell is normally programmed. As the sensing voltage, the first to third voltages PV1 to PV3 can be used. When the program verification result indicates that the memory cell is not normally programmed, a program pulse can be further applied to the memory cell. When the program verification result indicates that the memory cell is normally programmed, the programming operation for the memory cell can be ended.

[0044] In an embodiment, the sensing operation during the process of reading data stored in the memory cell can be performed as follows: a sensing voltage can be applied to the word line corresponding to the memory cell to be read in order to read data stored in the memory cell. As the sensing voltage, the first to third voltages PV1 to PV3 can be used. The read result can indicate which state among the erase state ERA and the first to third program states PG1 to PG3 the data stored in the memory cell has.

[0045] Since the multi-level cell has a plurality of threshold voltage distributions, the width of the threshold voltage distribution based on the respective states ERA and PG1 to PG3 needs to be narrowed in order to secure sufficient sensing margin when performing the sensing operation for each state. Hereinafter, a reference will be made to FIG. 1BA dual-sensing operation is described as a method for narrowing the width of a threshold voltage distribution.

[0046] FIG. 1B is a diagram for describing a dual-sensing operation applied during a programming process.

[0047] FIG. 1B How a dual-sensing operation is applied during a programming process for a memory cell is shown. For reference, FIG. 1B A case where a memory cell is programmed to FIG. 1A a first program state PG1 is exemplified.

[0048] In the case of a programming process using a single-sensing operation, in order to verify whether the memory cell is programmed to the first program state PG1, only the first voltage PV1 can be used as a sensing voltage to perform verification. However, in the case of a programming process using a dual-detection operation, the first voltage PV1 and a first sub-voltage DPV1 lower than the first voltage PV1 can be used together as a sensing voltage to verify the threshold voltage of the memory cell twice in order to check whether the memory cell is programmed to the first program state PG1.

[0049] In an embodiment, a programming process using a dual-sensing operation can be performed as follows: a program pulse can be applied to a word line corresponding to a memory cell in an erased state ERA to be programmed. After applying the program pulse, the threshold voltage of the memory cell can be verified using the first sub-voltage DPV1 whether it is higher than the first sub-voltage DPV1, and then the threshold voltage of the memory cell can be verified using the first voltage PV1 whether it is higher than the first voltage PV1. Hereinafter, in order to distinguish between a state where programming has been completed and a state where programming has not been completed but the memory cell is programmed to have a threshold voltage equal to or higher than the first sub-voltage DPV1, the former state can be referred to as a target program state, and the latter state can be referred to as a sub-program state.

[0050] When the verification result indicates that the threshold voltage of the memory cell is lower than the first sub-voltage DPV1, a program pulse can be applied to the memory cell under the same conditions as the previous conditions. In addition, when the verification result indicates that the threshold voltage of the memory cell is higher than the first sub-voltage DPV1 and lower than the first voltage PV1 (sub-program state), the voltage of the bit line can be raised more than before, and a program pulse can be applied to the memory cell. When the verification result indicates that the threshold voltage of the memory cell is higher than the first voltage PV1 (target program state), a prohibit voltage can be applied to the bit line, and a program pulse can be applied to the memory cell.

[0051] Similarly, even when the memory cell is programmed to the second program state PG2, the second sub-voltage lower than the second voltage PV2 and higher than the first voltage PV1 can be used to verify the memory cell twice. However, since the third program state PG3 is distributed at the rightmost side, it is not necessary to reduce the width of the distribution of the threshold voltage. Accordingly, the verification through the double sensing operation can not be performed.

[0052] Generally, when a program pulse is applied, the degree to which the threshold voltage of the memory cell changes can decrease as the voltage of the bit line increases. Accordingly, when a program pulse is applied to a memory cell whose threshold voltage does not correspond to a sub-program state or a target program state, the threshold voltage of the memory cell can change significantly. When a program pulse is applied to a memory cell whose threshold voltage corresponds to a sub-program state, the threshold voltage of the memory cell can change less than the threshold voltage of a memory cell in an erased state. Although a program pulse is applied to a memory cell whose threshold voltage corresponds to a program state, the threshold voltage of the memory cell hardly changes. Accordingly, the width of the threshold voltage of the memory cell in the first program state PG1 can be reduced. However, since the programming process using the double sensing operation includes a double verification operation using two sensing voltages in order to verify whether the memory cell is programmed to one program state, the time required for performing the double verification operation can increase significantly.

[0053] FIG. 2 FIG. 1 is a diagram illustrating a configuration of a non-volatile memory device according to an embodiment.

[0054] Referring to FIG. 2 The non-volatile memory device can include a page buffer 200, a memory cell array 210, control logic 220, a voltage generator 250, a row decoder 260, and an I / O (input / output) circuit 240.

[0055] First, the memory cell array 210 can include a plurality of memory cells. For example, the plurality of memory cells can be flash memory cells. Hereinafter, a case in which the plurality of memory cells are cells of a NAND flash memory device will be described as an example. However, the technical spirit of the present disclosure is not limited thereto. In another embodiment, the plurality of memory cells can be cells of a memory device such as a PRAM (Phase-change RAM), an MRAM (Magnetic RAM), an RRAM (Resistive RAM), or an FRAM (Ferroelectric RAM).

[0056] The memory cell array 210 can be a 3D memory cell array. The 3D memory cell array can be formed at one or more physical heights of the memory cell array, each having an active region disposed on a silicon substrate and a circuit formed on or in the substrate as a circuit related to the operation of the memory cell. The layers constituting the memory cell array at the respective heights can be stacked directly above the layer at the bottom height of the memory cell array. The 3D memory cell array can include NAND strings disposed vertically such that at least one memory cell is located above another memory cell. The at least one memory cell can include a charge trap layer. However, the present disclosure is not limited thereto. In another embodiment, the memory cell array 210 can be a 2D memory cell array.

[0057] In the present embodiment, each memory cell included in the memory cell array 210 can store 1-bit data or 2-bit or more data therein. In general, a memory cell capable of storing 1-bit data therein can be referred to as an SLC (Single Level Cell), a memory cell capable of storing 2-bit or more data therein can be referred to as an MLC (Multi Level Cell), a memory cell capable of storing 3-bit data therein can be referred to as a TLC (Triple Level Cell), a memory cell capable of storing 4-bit data therein can be referred to as a QLC (Quad Level Cell), and a memory cell capable of storing 5-bit or more data therein can be referred to as a multi-level cell. The SLC can have an erase state and a program state according to its threshold voltage, and the MLC, the TLC, the QLC, and the multi-level cell can each have an erase state and a plurality of program states according to their threshold voltages. The present disclosure is not limited thereto. However, in another embodiment, some of the memory cells included in the memory cell array 210 can be SLCs each capable of storing 1-bit data therein, and other memory cells can be MLCs.

[0058] The control logic 220 can output various control signals X_ADDR, CON_SIG, and CON_VOL for writing data to or reading data from the memory cell array 210 based on a command CMD and an address ADDR received from an external memory controller.

[0059] The page buffer 200 can write input data to the memory cell array 210 in response to an operation control signal CON_SIG transferred from the control logic 220. For example, during a write operation, the page buffer 200 can transfer a bit line voltage corresponding to data to be written to a bit line BL of the memory cell array 210. Also, the page buffer 200 can read or verify data stored in the memory cell array 210 in response to an operation control signal CON_SIG transferred from the control logic 220. For example, during a read operation or a verify operation, the page buffer 200 can sense data stored in a selected memory cell through a bit line. The page buffer 200 can include a plurality of latch circuits, and latch data sensed through a bit line during a read operation or a verify operation.

[0060] The voltage generator 250 can generate various types of voltages for performing a write operation, a read operation, and an erase operation on the memory cell array 210, based on a voltage control signal CON_VOL transferred from the control logic 220. For example, the voltage generator 250 can generate a word line voltage VWL, e.g., a program voltage (or write voltage), a read voltage, a pass voltage (or word line unselected voltage), a verify voltage, or a recovery voltage.

[0061] The row decoder 260 can select some word lines among a plurality of word lines WL included in the memory cell array 210 in response to a row address X-ADDR transferred from the control logic 220. The row decoder 260 can transfer a word line voltage to the word lines. For example, during a program operation, the row decoder 260 can apply a program voltage and a verify voltage to selected word lines and apply a program inhibit voltage to unselected word lines. During a read operation, the row decoder 260 can apply a read voltage to selected word lines and apply a read inhibit voltage to unselected word lines. During a recovery operation, the row decoder 260 can apply a recovery voltage to selected word lines. Also, in response to the row address X-ADDR, the row decoder 260 can select some string selection lines among string selection lines or some ground selection lines among ground selection lines.

[0062] The I / O circuit 240 can receive data from the outside (e.g., a memory controller) and transfer the received data to the page buffer 200 to store the received data in the memory cell array 210. The I / O circuit 240 can read data from the memory cell array 210 through the page buffer 200 and output the read data to the outside.

[0063] FIG. 3 is a diagram for describing a characteristic operation of a nonvolatile memory device according to the present embodiment. FIG. 2

[0064] Referring to FIG. 3 ​The nonvolatile memory device according to the present embodiment can include a cell string 310, a bit line BL, a control signal generator 330, and a page buffer 300. The page buffer 300 can include a first coupling cell 301, a second coupling cell 302, a third coupling cell 303, a first latch cell 304, and a second latch cell 305.

[0065] For reference, FIG. 3 The cell string 310 and the bit line BL illustrated can correspond to any one of a plurality of cell strings included in FIG. 2 the memory cell array 210 and any one of a plurality of bit lines corresponding to the cell string, respectively. Similarly, FIG. 3 The page buffer 300 illustrated can be FIG. 2 one of the page buffers 200 specifically exemplified as an example and corresponding to one or more bit lines. Further, FIG. 3 The control signal generator 330 illustrated can be a component included in FIG. 2 the control logic 220. In FIG. 2 , the control signal transferred from the control logic 220 to the page buffer 200 is simply denoted by "CON_SIG". However, in FIG. 3 , a case in which the control signal generator 330 generates first to fifth control signals TRANSO, PRECHSO_N, SC, ASET, and BSET and transfers the generated signals to the page buffer 300 will be exemplified.

[0066] In an embodiment, the cell string 310 can include a plurality of memory cells C0 to CN coupled in series. The cell string 310 can refer to a string structure in which a plurality of memory cells C0 to CN are coupled in series between a source select transistor configured to receive an SSL and a drain select transistor configured to receive a DSL. Various voltages can be applied to the floating gates of the plurality of memory cells C0 to CN through a plurality of word lines WL0 to WLN.

[0067] The bit line BL can be coupled to the cell string 310.

[0068] The control signal generator 330 can generate a plurality of control signals for controlling the operation of the page buffer 300, for example, a first control signal TRANSO, a second control signal SC, a third control signal ASET, a fourth control signal BSET, and a fifth control signal PRECHSO_N. For reference, FIG. 3The control signal generator 330 generates five signals TRANSO, SC, ASET, BSET, and PRECHSO_N to control the operation of the page buffer 300, but this is only one embodiment. Depending on the design, the control signal generator 330 can generate different types or different numbers of signals to control the operation of the page buffer 300.

[0069] The page buffer 300 can pre-charge the bit line BL, the first sensing node SO_A, and the second sensing node SO_B to a preset level, and then double-sense the bit line BL through the first sensing node SO_A and the second sensing node SO_B.

[0070] In an embodiment, the first coupling unit 301 included in the page buffer 300 can couple the bit line BL and the first sensing node SO_A in response to the first control signal TRANSO. The first coupling unit 301 can include an NMOS transistor N1 configured to selectively couple the bit line BL and the first sensing node SO_A connected to the drain and the source thereof in response to the first control signal TRANSO applied to the gate thereof.

[0071] The second coupling unit 302 included in the page buffer 300 can couple the first sensing node SO_A and the second sensing node SO_B in response to the second control signal SC and control the first sensing node SO_A and the second sensing node SO_B to have a first voltage level interval according to a preset ratio in a second period.

[0072] The first latch unit 304 included in the page buffer 300 can latch a logic level corresponding to the voltage level of the first sensing node SO_A in response to the third control signal ASET.

[0073] The second latch unit 305 included in the page buffer 300 can latch a logic level corresponding to the voltage level of the second sensing node SO_B in response to the fourth control signal BSET.

[0074] The third coupling unit 303 included in the page buffer 300 can selectively couple the core voltage terminal VCORE and the first sensing node SO_A in response to the fifth control signal PRECHSO_N. The third coupling unit 303 can include a PMOS transistor P1 configured to selectively couple the core voltage terminal VCORE and the first sensing node SO_A connected to the drain and the source thereof in response to the fifth control signal PRECHSO_N applied to the gate thereof.

[0075] FIG. 4 is an example of a page buffer according to the present embodiment. FIG. 3a diagram of a configuration of a page buffer in a nonvolatile memory device.

[0076] FIG. 4 a detailed configuration of the page buffer 300 shown in FIG. 1 is illustrated. FIG. 3 a detailed configuration of the page buffer 300 shown in FIG. 1 is illustrated.

[0077] In an embodiment, the page buffer 300 can include a first coupling unit 301, a second coupling unit 302, a third coupling unit 303, a first latching unit 304, and a second latching unit 305.

[0078] The first coupling unit 301 included in the page buffer 300 can couple the bit line BL and the first sensing node SO_A in response to a first control signal TRANSO. The first coupling unit 301 can include an NMOS transistor N1 configured to selectively couple the bit line BL and the first sensing node SO_A connected to a drain and a source thereof in response to the first control signal TRANSO applied to a gate thereof.

[0079] The second coupling unit 302 included in the page buffer 300 can couple the first sensing node SO_A and the second sensing node SO_B in response to a second control signal SC and control the first sensing node SO_A and the second sensing node SO_B to have voltage level intervals according to a preset ratio in a second period. In an embodiment, the second coupling unit 302 can include a switch NSC and a capacitor CSC. The switch NSC can selectively couple the first sensing node SO_A and the second sensing node SO_B in response to the second control signal SC. The switch NSC can be an NMOS transistor configured to selectively couple the first sensing node SO_A and the second sensing node SO_B connected to a drain and a source thereof in response to the second control signal SC applied to a gate thereof. The capacitor CSC can be coupled in parallel with the switch NSC between the first sensing node SO_A and the second sensing node SO_B.

[0080] The first latch unit 304 included in the page buffer 300 can latch a logic level corresponding to a voltage level of the first sense node SO_A in response to a third control signal ASET. In an embodiment, the first latch unit 304 can include a first latch inverter INVA1, a first inverting latch inverter INVA2, an NMOS transistor NA1, an NMOS transistor NA2, and an NMOS transistor NA3. The first latch inverter INVA1 can have an input terminal coupled to a first latch node QA and an output terminal coupled to a first inverting latch node QA_N. The first inverting latch inverter INVA2 can have an input terminal coupled to the first inverting latch node QA_N and an output terminal coupled to the first latch node QA. The NMOS transistor NA1 can selectively couple the first inverting latch node QA_N and a first source node SA connected to a drain and a source thereof in response to the third control signal ASET applied to a gate thereof. The NMOS transistor NA2 can selectively couple the first latch node QA and the first source node SA connected to a drain and a source thereof in response to an inverted signal ARST of the third control signal ASET applied to a gate thereof. The NMOS transistor NA3 can control an amount of current flowing between the first source node SA and a ground voltage terminal VSS connected to a drain and a source thereof according to a voltage level of the first sense node SO_A connected to a gate thereof.

[0081] The second latch unit 305 included in the page buffer 300 can latch a logic level corresponding to a voltage level of the second sense node SO_B in response to a fourth control signal BSET. In an embodiment, the second latch unit 305 can include a second latch inverter INVB1, a second inverting latch inverter INVB2, an NMOS transistor NB1, an NMOS transistor NB2, and an NMOS transistor NB3. The second latch inverter INVB1 can have an input terminal coupled to a second latch node QB and an output terminal coupled to a second inverting latch node QB_N. The second inverting latch inverter INVB2 can have an input terminal coupled to the second inverting latch node QB_N and an output terminal coupled to the second latch node QB. The NMOS transistor NB1 can selectively couple the second inverting latch node QB_N and a second source node SB connected to a drain and a source thereof in response to the fourth control signal BSET applied to a gate thereof. The NMOS transistor NB2 can selectively couple the second latch node QB and the second source node SB connected to a drain and a source thereof in response to an inverted signal BRST of the fourth control signal BSET applied to a gate thereof. The NMOS transistor NB3 can control an amount of current flowing between the second source node SB and a ground voltage terminal VSS connected to a drain and a source thereof according to a voltage level of the second sense node SO_B connected to a gate thereof.

[0082] The third coupling unit 303 included in the page buffer 300 can selectively couple the core voltage terminal VCORE and the first sensing node SO_A in response to the fifth control signal PRECHSO_N. The third coupling unit 303 can include a PMOS transistor P1 configured to selectively couple the core voltage terminal VCORE and the first sensing node SO_A connected to a drain and a source thereof in response to the fifth control signal PRECHSO_N applied to a gate thereof.

[0083] FIG. 5 is a diagram for describing an example of an operation of a nonvolatile memory device according to the present embodiment.

[0084] FIG. 5 An example of a double sensing operation performed by a page buffer included in a nonvolatile memory device according to the present embodiment is illustrated.

[0085] In an embodiment, the page buffer 300 included in the nonvolatile memory device can precharge the bit line BL, the first sensing node SO_A, and the second sensing node SO_B to a preset level in the first period t1, and then perform double sensing on the bit line BL through the first sensing node SO_A and the second sensing node SO_B in the second periods t2 and t3.

[0086] The control signal generator 330 included in the nonvolatile memory device can activate the first control signal TRANSO, the second control signal SC, and the fifth control signal PRECHSO_N in the first period t1. In the third period t2 included in the second periods t2 and t3, the control signal generator 330 can deactivate the second control signal SC and the fifth control signal PRECHSO_N and activate the first control signal TRANSO. In the fourth period t3 included in the second periods t2 and t3 after the third period t2, the control signal generator 330 can deactivate the first control signal TRANSO, the second control signal SC, and the fifth control signal PRECHSO_N and switch the third control signal ASET and the fourth control signal BSET.

[0087] In response to the above-described operation of the control signal generator 330 to generate the first to fifth control signals TRANSO, SC, ASET, BSET, and PRECHSO_N, the page buffer 300 can operate as follows.

[0088] First, in the first period t1, the page buffer 300 can couple the bit line BL, the first sensing node SO_A, the second sensing node SO_B, and the core voltage terminal VCORE through the first to third coupling units 301 to 303, thereby pre-charging the bit line BL, the first sensing node SO_A, and the second sensing node SO_B to the core voltage level VCORE. That is, the first period t1 can be a pre-charge period.

[0089] In the third period t2, the page buffer 300 can decouple the first sensing node SO_A from the core voltage terminal VCORE through the third coupling unit 303, and couple the bit line BL and the first sensing node SO_A through the first coupling unit 301, thereby evaluating voltage levels of the bit line BL and the first sensing node SO_A. That is, the third period t2 can be an evaluation period of the bit line BL and the first sensing node SO_A.

[0090] Further, in the third period t2, the page buffer 300 can couple the first sensing node SO_A and the second sensing node SO_B through the capacitor CSC included in the second coupling unit 302, and thus control the first sensing node SO_A and the second sensing node SO_B to have voltage level intervals according to a preset ratio. That is, in the third period t2, the page buffer 300 can turn off the switch NSC included in the second coupling unit 302, and thus control the first sensing node SO_A and the second sensing node SO_B to be coupled through the capacitor CSC coupled between the first sensing node SO_A and the second sensing node SO_B in parallel with the switch NSC.

[0091] In the evaluation period of the bit line BL and the first sensing node SO_A after the pre-charge period (i.e., in the third period t2), the voltage level of the bit line BL can vary according to the state of the target cell included in the cell string 310. As a result, the voltage level of the first sensing node SO_A electrically coupled to the bit line BL through the first coupling unit 301 can vary as shown. FIG. 5

[0092] For example, FIG. 5 A specific sensing voltage (e.g., PV1) (see FIG. 1A ) can be applied to the selected word line (e.g., the target word line WL0) (see FIG. 3 ​) and is applied to the other word lines by the voltage. In this state, when the threshold voltage of the target cell CO coupled to the target word line WL0 is lower than PV1 and higher than DPV1 or lower than DPV1, the target cell CO can be turned on so that the current flows from the bit line BL to the ground voltage terminal VSS. Accordingly, the voltage level of the bit line BL that has risen to the preset level in the first period t1 can become lower than the preset level in the third period t2. As a result, in the third period t2, the voltage level of the first sensing node SO_A can be lowered as FIG. 5 indicated.

[0093] At this time, in the third period t2, the target cell CO whose threshold voltage is lower than PV1 and higher than DPV1 can be less turned on than the target cell CO whose threshold voltage is lower than DPV1. In this case, a relatively small current can flow from the bit line BL to the ground voltage terminal VSS. Accordingly, the slope of the voltage level of the bit line BL lowered by the target cell CO whose threshold voltage is lower than PV1 and higher than DPV1 in the third period t2 can be smaller than the slope of the voltage level of the bit line BL lowered by the target cell CO whose threshold voltage is lower than DPV1. That is, the level determined after the voltage level of the first sensing node SO_A is lowered by the target cell CO whose threshold voltage is lower than PV1 and higher than DPV1 during the third period t2 can be higher than the level determined after the voltage level of the first sensing node SO_A is lowered by the target cell CO whose threshold voltage is lower than DPV1 during the third period t2.

[0094] Further, in the third period t2, the switch NSC between the first sensing node SO_A and the second sensing node SO_B can be turned off so that the first sensing node SO_A and the second sensing node SO_B are coupled through the capacitor CSC. Accordingly, as FIG. 5 indicated, the voltage level of the second sensing node SO_B can be lowered while having a voltage level interval from the voltage level of the first sensing node SO_A according to a preset ratio.

[0095] For example, when it is assumed that the voltage level of the first sensing node SO_A decreases at a first slope in the third period t2 in response to the voltage level of the bit line BL lowered by the target cell C0 whose threshold voltage is lower than PV1 and higher than DPV1, the voltage level of the second sensing node SO_B can decrease at a second slope. At this time, the first slope can be greater than the second slope, and the slope difference therebetween can vary according to the capacitance value of the capacitor CSC coupled between the first sensing node SO_A and the second sensing node SO_B. Also, when it is assumed that the voltage level of the first sensing node SO_A decreases at a third slope in the third period t2 in response to the voltage level of the bit line BL lowered by the target cell C0 whose threshold voltage is lower than DPV1, the voltage level of the second sensing node SO_B can decrease at a fourth slope. At this time, the third slope can be greater than the fourth slope, and the slope difference therebetween can vary according to the capacitance value of the capacitor CSC coupled between the first sensing node SO_A and the second sensing node SO_B.

[0096] When the capacitor CSC coupled between the first sensing node SO_A and the second sensing node SO_B has a constant capacitance value, the slope of the voltage level of the bit line BL lowered by the target cell C0 whose threshold voltage is lower than PV1 and higher than DPV1 is smaller than the slope of the voltage level of the bit line BL lowered by the target cell C0 whose threshold voltage is lower than DPV1. Accordingly, the first slope can be smaller than the third slope, and the second slope can be smaller than the fourth slope.

[0097] When the threshold voltage of the target cell C0 coupled to the target word line WL0 is higher than PV1, the target cell C0 can be turned off so that no current flows from the bit line BL to the ground voltage terminal VSS. In this case, the voltage level of the bit line BL can be substantially maintained as it is. As a result, the voltage level of the first sensing node SO_A can be substantially maintained as it is, unlike the voltage level shown in FIG. 4. Accordingly, the voltage level of the second sensing node SO_B can also be substantially maintained as it is. FIG. 5

[0098] The page buffer 300 can decouple the first sensing node SO_A from the bit line BL through the first coupling unit 301 in the fourth period t3. The page buffer 300 can decouple the first sensing node SO_A from the core voltage terminal VCORE through the third coupling unit 303 in the fourth period t3. The page buffer 300 can latch a logic level corresponding to the voltage level of the first sensing node SO_A in the first latch unit 304 in response to the third control signal ASET switched in the fourth period t3. Also, the page buffer 300 can latch a logic level corresponding to the voltage level of the second sensing node SO_B in the second latch unit 305 in response to the fourth control signal BSET switched in the fourth period t3.​

[0099] As described above, the page buffer 300 can control the first and second sensing nodes SO_A and SO_B to have the voltage level intervals according to the preset ratio in the third period t2. Accordingly, as FIG. 5 illustrated, the page buffer 300 can latch the logic levels corresponding to the voltage levels of the first and second sensing nodes SO_A and SO_B as different values in the fourth period t3. That is, the page buffer 300 can double sense the state of the target cell based on the different sensing voltage levels of the first and second sensing nodes SO_A and SO_B in the second and third periods t2 and t3.

[0100] For example, as FIG. 5 illustrated, it can be assumed that the first and second latching units 304 and 305 decide the logic levels corresponding to the voltage levels of the first and second sensing nodes SO_A and SO_B based on the same trip voltage level Vtrip. Further, as FIG. 5 illustrated, it can be assumed that the voltage level of the first sensing node SO_A is changed to a level lower than the trip voltage level Vtrip and the voltage level of the second sensing node SO_B is changed to a level higher than the trip voltage level Vtrip in the third period t2, in which case, in the fourth period t3, the logic level of the first sensing node SO_A latched in the first latching node QA of the first latching unit 304 can become logic "low", and the logic level of the second sensing node SO_B latched in the second latching node QB of the second latching unit 305 can become logic "high", so that the first and second latching units 304 and 305 latch different logic levels.

[0101] On the other hand, as FIG. 5 illustrated, when the voltage levels of the first and second sensing nodes SO_A and SO_B are substantially maintained as they are in the third period t2, the page buffer 300 can latch the logic levels corresponding to the respective voltage levels of the first and second sensing nodes SO_A and SO_B as the same value in the fourth period t3.

[0102] FIG. 6A and FIG. 6B are diagrams for describing another example of an operation of a nonvolatile memory device according to the present embodiment.

[0103] FIG. 6A and FIG. 6B Another example of a double sensing operation performed by a page buffer included in a nonvolatile memory device according to the present embodiment is exemplified.

[0104] For reference, by FIG. 6A and FIG. 6B The dual sensing operation performed by the page buffer 300 shown is related to the... FIG. 5 The difference in the dual sensing operation performed by the page buffer 300 shown is that... FIG. 6A and FIG. 6B The second phase of the dual-sensing operation was divided into three phases (i.e., phase 3 t2, phase 4 t3, and phase 5 t4), while FIG. 5 The second time period t2 and t3 of the dual-sensing operation are divided into two time periods. Therefore, the following description will focus on the process by... FIG. 5 The dual sensing operation performed by the page buffer 300 shown is related to the... FIG. 6A and FIG. 6B The differences between the dual sensing operations performed by the page buffer 300 shown are illustrated, and their overlapping content will be omitted in this document.

[0105] Reference FIG. 6A The control signal generator 330, included in the non-volatile memory device, can activate the first control signal TRANSO, the second control signal SC, and the fifth control signal PRECHSO_N during the first time period t1. Furthermore, during the third time period t2, which includes the second time periods t2, t3, and t4, the control signal generator 330 can deactivate the second control signal SC and the fifth control signal PRECHSO_N and activate the first control signal TRANSO. During the fourth time period t3, which follows the third time period t2 and includes the second time periods t2, t3, and t4, the control signal generator 330 can deactivate the first control signal TRANSO, the second control signal SC, and the fifth control signal PRECHSO_N, and switch the third control signal ASET and the fourth control signal BSET. Furthermore, during the fifth time period t4, which includes the second time periods t2, t3, and t4 and precedes the third time period t2, the control signal generator 330 can activate the first control signal TRANSO and the second control signal SC and deactivate the fifth control signal PRECHSO_N. Additionally, as... FIG. 6A As indicated by the dashed line, the control signal generator 330 can adjust the length of the fifth time period t4 by adjusting the length of the time period in which the second control signal SC is activated, the first control signal TRANSO is activated, and the fifth control signal PRECHSO_N is deactivated.

[0106] In response to the above-described operation of the control signal generator 330 in generating the first to fifth control signals TRANSO, SC, ASET, BSET and PRECHSO_N, the page buffer 300 may operate as follows.

[0107] In the first period t1, the page buffer 300 can couple the bit line BL, the first sensing node SO_A, the second sensing node SO_B, and the core voltage terminal VCORE through the first to third coupling units 301 to 303, thereby pre-charging the bit line BL, the first sensing node SO_A, and the second sensing node SO_B to the core voltage level VCORE. That is, the first period t1 can be a pre-charge period.

[0108] In the fifth period t4, the page buffer 300 decouples the first sensing node SO_A from the core voltage terminal VCORE through the third coupling unit 303, and couples the bit line BL to the first and second sensing nodes SO_A and SO_B through the first and second coupling units 301 and 302, thereby evaluating the voltage levels of the bit line BL and the first and second sensing nodes SO_A and SO_B. That is, the fifth period t4 can be an evaluation period of the bit line BL and the first and second sensing nodes SO_A and SO_B.

[0109] In the third period t2, the page buffer 300 can decouple the first sensing node SO_A from the core voltage terminal VCORE through the third coupling unit 303, and couple the bit line BL and the first sensing node SO_A through the first coupling unit 301, thereby evaluating the voltage levels of the bit line BL and the first sensing node SO_A. That is, the third period t2 can be an evaluation period of the bit line BL and the first sensing node SO_A.

[0110] In the third period t2, the page buffer 300 can couple the first and second sensing nodes SO_A and SO_B through the capacitor CSC included in the second coupling unit 302, and thus control the first and second sensing nodes SO_A and SO_B to have voltage level intervals according to a preset ratio. That is, in the third period t2, the page buffer 300 can turn off the switch NSC included in the second coupling unit 302, and thus control the first and second sensing nodes SO_A and SO_B to be coupled through the capacitor CSC coupled in parallel with the switch NSC.

[0111] In the evaluation period of the bit line BL and the first and second sensing nodes SO_A and SO_B after the pre-charge period (i.e., in the fifth period t4), the voltage level of the bit line BL can vary according to the state of the target cell included in the cell string 310. As a result, the voltage levels of the first and second sensing nodes SO_A and SO_B electrically coupled to the bit line BL through the first and second coupling units 301 and 302 can vary as indicated by the dotted lines in FIG. 4. FIG. 6A

[0112] ​For example, it can be assumed that a certain sensing voltage (e.g., PV1) (see FIG. 1A ) is applied to a selected word line (e.g., target word line WL0) (see FIG. 3 ), and a voltage is applied to the other word lines. In this state, when the threshold voltage of the target cell CO coupled to the target word line WL0 is lower than PV1 and higher than DPV1 and when the threshold voltage of the target cell CO coupled to the target word line WL0 is lower than DPV1, the target cell CO can be turned on so that a current flows from the bit line BL to the ground voltage terminal VSS. Accordingly, the voltage level of the bit line BL that has risen to a preset level in the first period t1 can become lower than the preset level in the fifth period t4. As a result, in the fifth period t4, the voltage levels of the first sensing node SO_A and the second sensing node SO_B can decrease as indicated by the dotted line in FIG. 6A .

[0113] At this time, the target cell CO whose threshold voltage is lower than PV1 and higher than DPV1 in the fifth period t4 can be less turned on than the target cell CO whose threshold voltage is lower than DPV1. Accordingly, a relatively small current can flow from the bit line BL to the ground voltage terminal VSS. Thus, the slope of the voltage level of the bit line BL decreased by the target cell CO whose threshold voltage is lower than PV1 and higher than DPV1 in the fifth period t4 can be smaller than the slope of the voltage level of the bit line BL decreased by the target cell CO whose threshold voltage is lower than DPV1. That is, the level determined after the voltage level of the first sensing node SO_A is decreased by the target cell CO whose threshold voltage is lower than PV1 and higher than DPV1 during the fifth period t4 can be higher than the voltage level determined after the voltage level of the first sensing node SO_A is decreased by the target cell CO whose threshold voltage is lower than DPV1 during the fifth period t4.

[0114] In the fifth period t4, the switch NSC between the first sensing node SO_A and the second sensing node SO_B can be turned on so that the first sensing node SO_A and the second sensing node SO_B are electrically coupled to each other. Accordingly, as shown in FIG. 6A , the voltage level of the second sensing node SO_B can decrease with the same slope as the voltage level of the first sensing node SO_A. That is, in the fifth period t4, in response to the decreased voltage level of the bit line BL, the voltage levels of the first sensing node SO_A and the second sensing node SO_B can decrease with the slope indicated by the dotted line in FIG. 6A .

[0115] In the evaluation period of the bit line BL and the first sensing node SO_A after the fifth period t4 (i.e., in the third period t2), the switch NSC between the first sensing node SO_A and the second sensing node SO_B can be turned off, and the first sensing node SO_A and the second sensing node SO_B can be coupled through the capacitor CSC. Thus, as indicated by the dotted line in FIG. 6A , the voltage level of the second sensing node SO_B can decrease while having a voltage level interval from the voltage level of the first sensing node SO_A according to a preset ratio. That is, until the fifth period t4, the voltage levels of the first sensing node SO_A and the second sensing node SO_B can decrease with the same slope in response to the decreased voltage level of the bit line BL. However, in the third period t2, the voltage levels of the first sensing node SO_A and the second sensing node SO_B can decrease with different slopes.

[0116] For example, when it is assumed that the voltage level of the first sensing node SO_A decreases with a first slope in the third period t2 in response to the voltage level of the bit line BL decreased by the target cell C0 having a threshold voltage lower than PV1 and higher than DPV1, the voltage level of the second sensing node SO_B can decrease with a second slope. At this time, the first slope can be greater than the second slope, and the slope difference therebetween can vary according to the capacitance value of the capacitor CSC coupled between the first sensing node SO_A and the second sensing node SO_B. Also, when it is assumed that the voltage level of the first sensing node SO_A decreases with a third slope in the third period t2 in response to the voltage level of the bit line BL decreased by the target cell C0 having a threshold voltage lower than DPV1, the voltage level of the second sensing node SO_B can decrease with a fourth slope. At this time, the third slope can be greater than the fourth slope, and the slope difference therebetween can vary according to the capacitance value of the capacitor CSC coupled between the first sensing node SO_A and the second sensing node SO_B.

[0117] When the capacitor CSC coupled between the first sensing node SO_A and the second sensing node SO_B has a constant capacitance value, the slope of the voltage level of the bit line BL decreased by the target cell C0 having a threshold voltage lower than PV1 and higher than DPV1 is less than the slope of the voltage level of the bit line BL decreased by the target cell C0 having a threshold voltage lower than DPV1. Thus, the first slope can be less than the third slope, and the second slope can be less than the fourth slope.

[0118] Also, referring to FIG. 6A and FIG. 6B , in a state in which the first control signal TRANSO is activated and the fifth control signal PRECHSO_N is deactivated (i.e., in a state after the first period t1), the control signal generator 330 can adjust the voltage level of the second sensing node SO_B to be higher than the voltage level of the first sensing node SO_A by adjusting the voltage level of the second power supply line VDD2 asFIG. 6A The length of the fifth period t4 can be adjusted by the length of the period in which the second control signal SC indicated by the dotted line is activated. In response to the operation of the control signal generator 330 adjusting the length of the activation period of the second control signal SC, the page buffer 300 can adjust the preset ratio to determine the voltage level interval between the first sensing node SO_A and the second sensing node SO_B. This can be because, although the voltage levels of the first sensing node SO_A and the second sensing node SO_B change at the same slope in the fifth period t4, the voltage levels of the first sensing node SO_A and the second sensing node SO_B change at different slopes in the third period t3.

[0119] That is, according to the length of the period in which the second control signal SC is activated while the first control signal TRANSO is activated and the fifth control signal PRECHSO_N is deactivated by the control signal generator 330, the ratio of the length of the third period t2 to the length of the fifth period t4 in the second periods t2, t3, and t4 can be determined and used as the preset ratio.

[0120] For example, the page buffer 300 can control the first sensing node SO_A and the second sensing node SO_B to have a greater voltage level interval by reducing the length of the fifth period t4 and increasing the length of the third period t2 in the second periods t2, t3, and t4. On the other hand, the page buffer 300 can control the first sensing node SO_A and the second sensing node SO_B to have a smaller voltage level interval by increasing the length of the fifth period t4 and reducing the length of the third period t2 in the second periods t2, t3, and t4.

[0121] In FIG. 6A and FIG. 6B , the solid line can show that the double sensing operation is performed in the same manner as the double sensing operation of the page buffer 300 described with reference to FIG. 5 . That is, the solid line can indicate that the length of the fifth period t4 in the second periods t2, t3, and t4 is zero, and the length of the third period t2 is the greatest. In addition, in FIG. 6A and FIG. 6B , the dotted line can show that the length of the fifth period t4 in the second periods t2, t3, and t4 is almost similar to the length of the third period t2 thereof, which indicates that the length of the third period t2 has been significantly reduced compared to that shown by the solid line. Accordingly, the voltage level interval between the first sensing node SO_A and the second sensing node SO_B indicated by the solid line in FIG. 6A and FIG. 6B may be greater than the voltage level interval between the first sensing node SO_A and the second sensing node SO_B indicated by the dotted line in FIG. 6A and FIG. 6B .

[0122] FIG. 7A and FIG. 7B are diagrams for comparing and describing operations of a nonvolatile memory device according to the present embodiment and operations of a nonvolatile memory device according to the related art.

[0123] First, FIG. 7A It is shown that a nonvolatile memory device according to the related art performs two verifications using two sensing voltages in order to perform a double sensing operation.

[0124] FIG. 7A It is exemplified that when a double sensing operation is performed on one target cell, the length of the evaluation period tA2 in the first verification operation and the length of the evaluation period tA5 in the second verification operation are set differently to control the two sensing voltages to have different levels.

[0125] In the embodiment, the first verification operation can include a first pre-charge period tA1, a first evaluation period tA2, and a first latching period tA3. That is, the first verification operation can include the steps of pre-charging the sensing node SO to a core voltage level in the first pre-charge period tA1, evaluating the voltage levels of the sensing node SO and the bit line BL in the first evaluation period tA2, and latching a logic level corresponding to the voltage level of the sensing node SO in the first latching period tA3. At this time, the length of the first evaluation period tA2 can be kept to a length sufficient to sufficiently lower the level of the sensing node SO in response to the state of the cell (on state under the assumption that a predetermined amount of current flows from the sensing node to the bit line). Accordingly, the logic level of the sensing node SO latched in the first latching period tA3 can become logic "low".

[0126] The second verification operation can include a second pre-charge period tA4, a second evaluation period tA5, and a second latching period tA6. That is, the second verification operation can include the steps of pre-charging the sensing node SO to a core voltage level in the second pre-charge period tA4, evaluating the voltage levels of the sensing node SO and the bit line BL in the second evaluation period tA5, and latching a logic level corresponding to the voltage level of the sensing node SO in the second latching period tA6. At this time, the length of the second evaluation period tA5 can be kept to a length smaller than the length of the first evaluation period tA2, such that in response to the state of the cell (on state under the assumption that a predetermined amount of current flows from the sensing node to the bit line), the level of the sensing node SO is lowered but not lower than the level in the first evaluation period tA2. Accordingly, the logic level of the sensing node SO latched in the second latching period tA6 can become logic "high".

[0127] FIG. 7BIt is shown that the non-volatile memory device according to the present embodiment performs one verification using two sensing voltages at the same time in order to perform a double sensing operation.

[0128] FIG. 7B It is shown that the first sensing node SO_A and the second sensing node SO_B have a voltage level interval according to a preset ratio in an evaluation period t2 included in one verification operation when a double sensing operation is performed on one target cell. Thus, in FIG. 7B , the non-volatile memory device can perform one verification using two sensing voltages at the same time through one latch period t3 after one evaluation period t2.

[0129] Thus, FIG. 7A and FIG. 7B The comparison between

[0130] For reference, since a detailed description of operations corresponding to FIG. 7B is included in the description of FIG. 2 to FIG. 6B , a detailed description thereof will be omitted herein.

[0131] FIG. 8A is a diagram for describing a double sensing operation applied during a read process.

[0132] FIG. 8A It is shown how the double sensing operation according to the present embodiment can be applied during a programming process for a memory cell. For reference, FIG. 8A a case where data stored in a memory cell is in a first program state PG1 is exemplified. FIG. 1A

[0133] In the case of a read process using a single sensing operation, a first voltage PV1 can be used as a sensing voltage to perform a first verification operation, and then a second voltage PV2 can be used for a sensing voltage to perform a second verification operation in order to check whether data stored in a memory cell is in a first program state PG1 and read the data.

[0134] However, in the case of a read process using a double sensing operation according to the present embodiment, a first voltage PV1 and a second voltage PV2 can be used as sensing voltages at the same time to perform one verification operation in order to check whether data stored in a memory cell is in a first program state PG1 and read the data.

[0135] Thus, the double sensing operation according to the present embodiment can be reliably applied to a read process for a memory cell. ​

[0136] FIG. 8B is a diagram for describing a dual-sensing operation applied after a retention time.

[0137] FIG. 8B It is shown how the dual-sensing operation according to the present embodiment is applied when the width of the threshold voltage distribution of the memory cell is wider than in the initial stage because a retention time has elapsed after data is stored in the memory cell. For reference, FIG. 8B a case where a retention time has elapsed after the memory cell is programmed in the first programmed state PG1 of FIG. 1A is exemplified.

[0138] In order to check the state of the data stored in the memory cell after the retention time by a single-sensing operation, the first voltage PV1 can be used as a sensing voltage to perform a first verify operation. Then, the first sub voltage DPV1 lower than the first voltage PV1 can be used as a sensing voltage to perform a second verify operation, which makes it possible to check how much the width of the threshold voltage distribution of the data stored in the memory cell has widened due to the retention time.

[0139] However, when the state of the data stored in the memory cell is checked after the retention time by the dual-sensing operation according to the present embodiment, the first voltage PV1 and the first sub voltage DPV1 lower than the first voltage PV1 can be simultaneously used as sensing voltages to perform a verify operation at once, which makes it possible to check how much the width of the threshold voltage distribution of the data stored in the memory cell has widened due to the retention time.

[0140] Thus, even when the width of the threshold voltage distribution of the memory cell is wider than in the initial stage because a retention time has elapsed after data is stored in the memory cell, the dual-sensing operation according to the present embodiment can be reliably applied.

[0141] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the application as defined in the appended claims.

[0142] For example, the positions and types of the logic gates and transistors exemplified in the present embodiment can be differently implemented depending on the polarity of the signal input thereto.

[0143] CROSS-REFERENCE TO RELATED APPLICATIONS

[0144] This application claims priority to Korean Patent Application No. 10-2021-0028760, filed on March 4, 2021, the entire contents of which are incorporated herein by reference.

Claims

1. A nonvolatile memory device, the nonvolatile memory device comprising: a cell string including a plurality of memory cells coupled in series; a bit line coupled to the cell string; and a page buffer precharging the bit line, a first sense node, and a second sense node to a preset level in a first period and double sensing the bit line through the first sense node and the second sense node in a second period, wherein the page buffer includes: a first coupling unit coupling the bit line and the first sense node in response to a first control signal; a second coupling unit coupling the first sense node and the second sense node in response to a second control signal and controlling the first sense node and the second sense node to have a voltage level interval according to a preset ratio in the second period; a first latching unit latching a logic level corresponding to a voltage level of the first sense node in response to a third control signal; and a second latching unit latching a logic level corresponding to a voltage level of the second sense node in response to a fourth control signal. the second coupling unit includes:

2. The nonvolatile memory device of claim 1, wherein, a switch selectively coupling the first sense node and the second sense node in response to the second control signal; and a capacitor coupled in parallel with the switch between the first sense node and the second sense node. the switch includes an NMOS transistor selectively coupling the first sense node and the second sense node connected to a drain and a source of the NMOS transistor in response to the second control signal applied to a gate of the NMOS transistor.

3. The nonvolatile memory device of claim 2, wherein, 4. The nonvolatile memory device of claim 2, the page buffer further includes a third coupling unit selectively coupling a core voltage terminal and the first sense node in response to a fifth control signal, and wherein the nonvolatile memory device further includes a control signal generator generating the first control signal to the fifth control signal. the control signal generator further:

5. The nonvolatile memory device of claim 4, wherein, activates the first control signal, the second control signal, and the fifth control signal in the first period, deactivates the second control signal and the fifth control signal and activates the first control signal in a third period included in the second period, and deactivates the first control signal, the second control signal, and the fifth control signal and switches the third control signal and the fourth control signal in a fourth period included in the second period and following the third period.

6. The nonvolatile memory device of claim 5, ​ wherein, the page buffer precharges the bit line and the first and second sense nodes to a core voltage level in the first period by coupling the bit line and the first and second sense nodes to the core voltage terminal via the first through third coupling units, wherein the page buffer further evaluates voltage levels of the bit line and the first sense node in the third period by decoupling the first sense node from the core voltage terminal via the third coupling unit and coupling the bit line and the first sense node via the first coupling unit, wherein the page buffer controls the first and second sense nodes to have the voltage level interval in the third period by coupling the first and second sense nodes via the capacitor of the second coupling unit, and wherein the page buffer further decouples the first sense node from the core voltage terminal and couples the first sense node and the bit line in the fourth period by the first and third coupling units, and latches logic levels corresponding to voltage levels of the first and second sense nodes in the first and second latch units, respectively, in response to switching of the third and fourth control signals.

7. The nonvolatile memory device of claim 5, wherein, the control signal generator further activates the first and second control signals and deactivates the fifth control signal in a fifth period included in the second period and before the third period.

8. The nonvolatile memory device of claim 7, wherein, the page buffer further evaluates the voltage levels of the bit line and the first and second sense nodes in the fifth period by decoupling the first sense node from the core voltage terminal via the third coupling unit and coupling the bit line and the first and second sense nodes via the first and second coupling units.

9. The nonvolatile memory device of claim 8, wherein, the control signal generator further adjusts a length of the fifth period by adjusting a length of a period in which the second control signal is activated while the first control signal is activated and the fifth control signal is deactivated.

10. The nonvolatile memory device of claim 9, wherein, the page buffer uses a ratio of respective lengths of the third and fifth periods as the preset ratio.

11. The non-volatile memory device of claim 10, wherein, the page buffer controls the first and second sense nodes to have a greater voltage level interval by reducing a length of the fifth period and increasing a length of the third period, and wherein the page buffer controls the first and second sense nodes to have a smaller voltage level interval by increasing a length of the fifth period and reducing a length of the third period.

12. A non-volatile memory device, the non-volatile memory device comprising: a bit line coupled to a cell string; a page buffer comprising: a coupling circuit including a switching element and a capacitive element coupled in parallel between a first node and a second node; and first and second latch circuits coupled to the respective first and second nodes; and a control circuit that: precharges the bit line and the first and second nodes by providing a precharge voltage to the first node coupled to the bit line and turning on the switching element, and after the precharge, electrically isolates the first node from the bit line while controlling the first and second latch circuits to latch logic levels of the respective first and second nodes, wherein the control circuit further turns off the switching element after the precharge and before the electrical isolation of the first node from the bit line, and wherein the latched logic levels are used for a double sensing operation for memory cells of the cell string.

Images