Storage device and method of operating the same

Abstract

The present invention provides a storage device and an operating method thereof. The storage device includes a plurality of memory blocks each including a plurality of word lines arranged between a first select line and a second select line, a peripheral circuit that performs an erase operation by applying an erase voltage to a source line or a drain line of a selected memory block, and control logic that controls the peripheral circuit to sequentially select the plurality of word lines included in the selected memory block one by one from a word line closest to the first select line and the second select line to a word line farthest from the first select line and the second select line, apply a first erase enable voltage to a selected word line, and apply a second erase enable voltage higher in potential level than the first erase enable voltage to the remaining word lines other than the selected word line in a period in which the erase operation is performed.

Description

TECHNICAL FIELD

[0001] Various embodiments relate to a semiconductor design technology, and more particularly, to a storage device capable of efficiently performing a gate-induced drain leakage (GIDL)-based erase operation and an operating method thereof. BACKGROUND

[0002] A storage system is a storage device implemented using a semiconductor such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), etc. A storage system is classified into a volatile storage device and a non-volatile storage device. The volatile storage device is a storage device in which stored data is lost at the time of power interruption. Representative examples of the volatile storage device include static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), etc. The non-volatile storage device is a storage device in which stored data is retained even at the time of power interruption. Representative examples of the non-volatile storage device include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. The flash memory is mainly classified into NOR-type memory and NAND-type memory. SUMMARY

[0003] Various embodiments of the disclosure relate to a storage device capable of efficiently performing a gate-induced drain leakage (GIDL)-based erase operation and an operating method thereof.

[0004] The technical problems to be solved by the disclosure are not limited to the above-mentioned problems, and other technical problems not mentioned can be clearly understood by those skilled in the art to which the disclosure pertains from the following description.

[0005] According to an embodiment of the present invention, a memory device can include: an array of memory cells including a plurality of memory blocks each including a plurality of memory cells and a plurality of word lines arranged between a first select line and a second select line; a peripheral circuit adapted to perform an erase operation by applying an erase voltage to a source line or a drain line of a memory block selected from the plurality of memory blocks; and control logic adapted to control the peripheral circuit, in a period of performing the erase operation, to sequentially select at least one by one the plurality of word lines included in a selected memory block from a word line closest to the first select line and the second select line to a word line farthest from the first select line, apply a first erase enable voltage to a selected word line, and apply a second erase enable voltage to the remaining word lines other than the selected word line. The first erase enable voltage can have a lower potential level than the second erase enable voltage.

[0006] The control logic can further control the peripheral circuit to apply the second erase enable voltage to all the word lines after the sequential selection and the application of the first erase enable voltage to all the word lines, until a period of a predetermined time ends.

[0007] The control logic can further control the peripheral circuit to repeat the sequential selection, the application of the first erase enable voltage, and the application of the second erase enable voltage, until a period of a predetermined time ends.

[0008] The second erase enable voltage can have a ground voltage level, and the first erase enable voltage can have a negative level lower than the ground voltage level.

[0009] The plurality of word lines can include a first dummy word line closest to the first select line, a second dummy word line closest to the second select line, and a third dummy word line farthest from the first select line and the second select line.

[0010] The peripheral circuit can include: a source line driver adapted to apply the erase voltage to the source line; a page buffer group coupled to a bit line of each of the memory blocks and adapted to control the bit line of a selected memory block to float in the period; and a row decoder coupled to a local line of the plurality of memory blocks and adapted to cause the first select line and the second select line among the local line of a selected memory block to float in the period, apply the first erase enable voltage to the selected word line, and apply the second erase enable voltage to the remaining word lines.

[0011] The control logic can also control the peripheral circuit to perform an erase verify operation after a predetermined time period of performing the erase operation. The control logic can also control the peripheral circuit to raise a potential level of an erase voltage according to an incremental step pulse erase (ISPE) method when a result of the erase verify operation indicates that the erase operation has failed, and can also control the peripheral circuit to perform the erase operation again with the raised erase voltage.

[0012] According to an embodiment of the present invention, a memory device can include an array of memory cells including a plurality of memory blocks each including a plurality of memory cells and a plurality of word lines arranged between a first select line and a second select line, and a peripheral circuit adapted to perform an erase operation by applying an erase voltage to a source line or a drain line of a memory block selected from the plurality of memory blocks. In a time period of performing the erase operation, the peripheral circuit can also be adapted to sequentially select the plurality of word lines included in a selected memory block one by one from a word line closest to the first select line and the second select line to a word line farthest from the first select line and the second select line, apply a first erase enable voltage to a selected word line, and apply a second erase enable voltage to the remaining word lines other than the selected word line. The first erase enable voltage can have a lower potential level than the second erase enable voltage.

[0013] The peripheral circuit can also be adapted to apply the second erase enable voltage to all of the word lines after the sequentially selecting and applying the first erase enable voltage to all of the word lines until a predetermined time period ends.

[0014] The peripheral circuit can also be adapted to repeat the sequentially selecting, applying the first erase enable voltage, and applying the second erase enable voltage until a predetermined time period ends.

[0015] The second erase enable voltage can have a ground voltage level, and the first erase enable voltage can have a negative level lower than the ground voltage level.

[0016] The plurality of word lines can include a first dummy word line closest to the first select line, a second dummy word line closest to the second select line, and a third dummy word line farthest from the first select line and the second select line.

[0017] The peripheral circuit can include a source line driver adapted to apply the erase voltage to the source line, a page buffer group coupled to the bit lines of each of the memory blocks and adapted to control the bit lines of a selected memory block to float during the time period, and a row decoder coupled to the local lines of the plurality of memory blocks and adapted to float the first select line and the second select line among the local lines of a selected memory block during the time period, apply the first erase enable voltage to a selected word line, and apply the second erase enable voltage to the remaining word lines.

[0018] According to embodiments of the present application, there is provided an operating method of a memory device including an array of memory cells including a plurality of memory blocks each having a plurality of memory cells and a plurality of word lines arranged between a first select line and a second select line, the operating method can include an erase step of performing an erase operation by applying an erase voltage to a source line or a drain line of a memory block selected from the plurality of memory blocks such that the plurality of memory cells included in the selected memory block have a threshold voltage equal to or less than a target erase voltage. The erase step can include a step of sequentially selecting the plurality of word lines included in the selected memory block one by one at least from a word line closest to the first select line and the second select line to a word line farthest from the first select line, applying a first erase enable voltage to a selected word line, and applying a second erase enable voltage to the remaining word lines other than the selected word line. The first erase enable voltage can have a lower potential level than the second erase enable voltage.

[0019] The operating method can further include applying the second erase enable voltage to all the word lines after the step of sequentially selecting and applying the first erase enable voltage to all the word lines until the erase step ends after a predetermined time is performed.

[0020] The operating method can further include repeating the step of sequentially selecting, the step of applying the first erase enable voltage, and the step of applying the second erase enable voltage until the erase step ends after a predetermined time is performed.

[0021] The second erase enable voltage can have a ground voltage level, and the first erase enable voltage can have a negative level lower than the ground voltage level.

[0022] The plurality of word lines can include a first dummy word line closest to the first select line, a second dummy word line closest to the second select line, and a third dummy word line farthest from the first select line and the second select line.

[0023] According to an embodiment of the present application, a method of erasing a nonvolatile memory block coupled to a source line, a first select line, a second select line, and a word line disposed between the first select line and the second select line can include applying an erase voltage to the source line while floating the first select line and the second select line, performing one or more iterations to erase the nonvolatile memory block, and verifying whether the erase of the nonvolatile memory block is successful. Each iteration can include sequentially applying a first erase enable voltage to the word lines from an outermost word line to an innermost word line with respect to the first select line and the second select line while applying a second erase enable voltage higher than the first erase enable voltage to the remaining word lines.

[0024] The method can further include applying the second erase enable voltage to the word lines between the performing and the verifying.

[0025] The method can further include repeating the applying, the performing, and the verifying by raising the erase voltage when the erase of the nonvolatile memory block is verified to fail.

[0026] According to an embodiment of the present application, a storage device using a GIDL-based erase operation can apply two types of erase enable voltages having different potential levels to a plurality of word lines included in an erase target memory block during an erase operation period.

[0027] Specifically, during the erase operation period, the storage device can sequentially select the plurality of word lines included in the erase target memory block at least one by one from a word line located at an edge of the memory block to a word line located at a center of the memory block, and apply a negative voltage to the selected word line.

[0028] Through this operation, when the GIDL-based erase operation is performed, the storage device can significantly increase the hole mobility of the voltage level corresponding to the erase voltage. Accordingly, the time required for the erase operation can be minimized, and the erase stress applied to the erase target memory block can be reduced. Further, according to an incremental step pulse erase (ISPE) method, the number of times of increasing the potential level of the erase voltage can be minimized. Further, the power consumption required to generate the erase voltage having a high potential level can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 FIG. 1 is a diagram illustrating an example of a storage system according to an embodiment of the present application.

[0030] Figure 2 FIG. 2 is a diagram illustrating an example of a storage device according to an embodiment of the present application. Figure 1 FIG. 3 is a diagram illustrating an example of a storage device according to an embodiment of the present application.

[0031] Figure 3 FIG. 4 is a diagram illustrating an example of a storage device according to an embodiment of the present application.Figure 2 FIG. 1 is a diagram illustrating an example of a storage block.

[0032] Figure 4 FIG. 2 is a diagram illustrating another example of a storage block. Figure 2 FIG. 3 is a diagram illustrating yet another example of a storage block.

[0033] Figure 5 FIG. 4 is a diagram illustrating a method of an erase operation of a storage device according to an embodiment of the present application. Figure 2 FIG. 5 is a diagram illustrating another example of a storage block.

[0034] Figure 6 FIG. 6 is a flowchart illustrating an example of an erase operation performed by a storage device according to an embodiment of the present application.

[0035] Figure 7 FIG. 7 is a flowchart illustrating another example of an erase operation performed by a storage device according to an embodiment of the present application.

[0036] Figures 8A to 8C FIG. 8 is a diagram illustrating a method of an erase operation of a storage device according to an embodiment of the present application. DETAILED DESCRIPTION

[0037] Various examples of the present disclosure are described in detail below with reference to the attached drawings. Aspects and features of the present application, however, can be implemented in various ways to form other embodiments, including variations of any of the disclosed embodiments. Accordingly, the present application is not limited to the embodiments set forth herein. Rather, the described embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the disclosure to those skilled in the art to which the present application pertains. Throughout the present disclosure, like reference numerals refer to like parts throughout the various drawings and examples of the present disclosure. It is noted that references to "an embodiment," "another embodiment," etc. do not necessarily refer to the same embodiment, and different embodiments can be described using different terminology. Moreover, these terms are not necessarily used consistently throughout the present disclosure.

[0038] It is to be understood that, although the terms "first," "second," "third," and the like can be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element in one instance can be termed a second or third element in another instance without referring to a change in the elements' identities.

[0039] The accompanying drawings are not necessarily drawn to scale, and in some instances, the dimensions of the various features can have been exaggerated or minimized for the purpose of clarity. When one element is referred to as being "on" or "connected" or "coupled" to another element, it can be directly on or connected or coupled to the other element, or intervening elements can be present. In addition, when one element is referred to as being "between" two other elements, it can be the only element between the two other elements, or one or more intervening elements can also be present.

[0040] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the terms "one", "another", "at least one" and the like are also intended to encompass the plural forms unless the context clearly dictates otherwise.

[0041] It will be further understood that the terms "comprises" and "comprising", when used in this specification, specify the presence of stated elements, but do not preclude the presence or addition of one or more other elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0042] Unless otherwise defined, all terms used in disclosing elements of the application, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs in view of the present disclosure. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and should not be interpreted in an overly idealized or overly formal sense unless expressly so defined herein.

[0043] In the following description, numerous specific details are set forth to provide a thorough understanding of the present application. The present application can be practiced without some or all of these specific details. In other instances, well known process structures and / or processes have not been described in detail in order not to unnecessarily obscure the present application.

[0044] It should also be noted that, in some instances, features or elements described in connection with an implementation can be used singly or in any combination other than the combination explicitly disclosed, unless expressly indicated otherwise.

[0045] Embodiments of the present disclosure are described in detail below with reference to the attached drawing figures, wherein the same elements are referred to with the same reference numerals, and in which:

[0046] Figure 1 is a diagram that describes an example of a storage system according to an embodiment of the present application.

[0047] Referring to Figure 1 The data processing system 100 can include a host 102 interfaced or operatively coupled with a storage system 110.

[0048] The host 102 can include any portable electronic device (e.g., a mobile phone, an MP3 player, a laptop computer, etc.) and an electronic device (e.g., a desktop computer, a game player, a television (TV), a projector, etc.).

[0049] The host 102 further includes at least one operating system (OS) that can generally manage and control functions and operations performed in the host 102. The OS can provide interoperability between the host 102 interfaced with the storage system 110 and a user using the storage system 110. The OS can support functions and operations corresponding to user requests. By way of example and not limitation, the OS can be classified into a general-purpose operating system and a mobile operating system according to mobility of the host 102. The general-purpose operating system can be classified into a personal operating system and an enterprise operating system according to system requirements or user environments. The personal operating system (including Windows and Chrome) can be used for general-purpose support services. However, the enterprise operating system (including Windows server, Linux, Unix, etc.) can be used exclusively to ensure and support high performance. In addition, the mobile operating system can include Android, iOS, Windows mobile, etc. The mobile operating system can support services or functions of mobility (e.g., power saving functions). The host 102 can include a plurality of operating systems. The host 102 can execute a plurality of operating systems corresponding to user requests in conjunction with the storage system 110. The host 102 can transmit a plurality of commands corresponding to user requests to the storage system 110, thereby performing operations corresponding to the commands inside the storage system 110.

[0050] The storage device of the storage system 110 can be implemented with a volatile storage device (e.g., a dynamic random access memory (DRAM) and a static RAM (SRAM)) and / or a non-volatile storage device (e.g., a read only memory (ROM), a mask ROM (MROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a ferroelectric RAM (FRAM), a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (RRAM or ReRAM), and a flash memory).

[0051] The storage system 110 can include a controller 130 and a storage device 150. The storage device 150 can store data to be accessed by the host 102. The controller 130 can control operations of storing data in the storage device 150.

[0052] The controller 130 and the storage device 150 included in the storage system 110 can be integrated into a single semiconductor device, which can be included in any of the various types of storage systems discussed in the above examples.

[0053] By way of example and not limitation, the controller 130 and the storage device 150 can be implemented with an SSD. When the storage system 110 is used as an SSD, the operating speed of the host 102 connected to the storage system 110 can be improved more than that of the host 102 implemented with a hard disk. In addition, the controller 130 and the storage device 150 can be integrated into one semiconductor device to form a memory card, such as a PC card (PCMCIA), a compact flash card (CF), a memory card such as a smart media card (SM, SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a universal flash storage, etc.

[0054] The storage system 110 can be configured as a part of, for example, a computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a tablet PC, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game player, a navigation system, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a three-dimensional (3D) TV, a smart TV, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device configured for a data center, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices configured for a home network, one of various electronic devices configured for a computer network, one of various electronic devices configured for a telematics network, a radio frequency identification (RFID) device, or one of various components configured for a computing system.

[0055] The storage device 150 can be a non-volatile storage device, and can retain data stored therein even when there is no power supply. The storage device 150 can store data provided by the host 102 through a write operation, and provide data stored therein to the host 102 through a read operation.

[0056] Figure 2 FIG. 1 is a diagram illustrating an example of a storage system according to an embodiment of the present application. Figure 1 FIG. 1 is a diagram illustrating an example of a storage system according to an embodiment of the present application.

[0057] Reference will now be made to Figure 2The storage device 150 can include a storage cell array 151 in which data is stored. The storage device 150 can include a peripheral circuit 200 configured to perform a program operation of storing data in the storage cell array 151, a read operation of outputting stored data, and an erase operation of erasing stored data. The storage device 150 can include control logic 300 configured to control the peripheral circuit 200 under the control of a storage controller (130). Figure 1

[0058] The storage cell array 151 can include a plurality of storage blocks 152, where k is a positive integer. A local line LL and bit lines BL1 to BLn can be coupled to each of the storage blocks 152, where n is a positive integer. For example, the local line LL can include a first selection line, a second selection line, and a plurality of word lines arranged between the first selection line and the second selection line. The local line LL can also include a dummy line arranged between the first selection line and the word lines, a dummy line arranged between the second selection line and the word lines, and a dummy line arranged between the word lines. The first selection line can be a source selection line, and the second selection line can be a drain selection line. For example, the local line LL can include a word line, a drain selection line, a source selection line, and a source line SL. For example, the local line LL can also include a dummy line. For example, the local line LL can also include a pipeline. The local line LL can be coupled to each of the storage blocks 152, and the bit lines BL1 to BLn can be commonly coupled to the storage blocks 152. The storage blocks 152 can be implemented in a 2D or 3D structure. For example, each of the storage blocks 152 having a 2D structure can include storage cells arranged in a direction parallel to a substrate. For example, each of the storage blocks 152 having a 3D structure can include storage cells stacked in a direction perpendicular to the substrate.

[0059] The peripheral circuit 200 can be configured to perform, under the control of the control logic 300, a program operation, a read operation, and an erase operation on a storage block selected from the storage blocks 152. For example, the peripheral circuit 200 can include a voltage generation circuit 210, a row decoder 220, a page buffer group 230, a column decoder 240, an input / output circuit 250, a pass / fail check circuit 260, and a source line driver 270.

[0060] The voltage generation circuit 210 can generate various operation voltages Vop for the program operation, the read operation, and the erase operation in response to an operation signal OP_CMD. In addition, the voltage generation circuit 210 can selectively discharge the local line LL in response to the operation signal OP_CMD. For example, the voltage generation circuit 210 can generate, under the control of the control logic 300, a program voltage, a verify voltage, a pass voltage, an erase voltage, and a select transistor operation voltage. ​

[0061] The row decoder 220 can transfer the operating voltage Vop to the local line LL coupled with the selected memory block 152 in response to the row decoder control signal AD_signal. For example, the row decoder 220 can selectively apply the operating voltage (e.g., a program voltage, a verify voltage, a pass voltage, etc.) generated by the voltage generation circuit 210 to the local line LL or float a portion of the line (e.g., a word line and a source select line) in response to the row decoder control signal AD_signal.

[0062] The page buffer group 230 can include a plurality of page buffers PB1 to PBn (231) coupled to the bit lines BL1 to BLn, respectively. The page buffers PB1 to PBn (231) can operate in response to a page buffer control signal PBSIGNAL. For example, the page buffers PB1 to PBn (231) can control the bit lines BL1 to BLn to be floated during an erase voltage application operation of an erase operation and sense a current or a voltage level of the bit lines BL1 to BLn during an erase verify operation of the erase operation.

[0063] The column decoder 240 can transfer data between the input / output circuit 250 and the page buffer group 230 in response to a column address CADD. For example, the column decoder 240 can exchange data with the page buffer 231 through a data line DL or exchange data with the input / output circuit 250 through a column line CL.

[0064] The input / output circuit 250 can transfer a command CMD and an address ADD received from the memory controller 130 of the memory device 100 to the control logic 300 or exchange data DATA with the column decoder 240. Figure 1 The input / output circuit 250 can transfer a command CMD and an address ADD received from the memory controller 130 of the memory device 100 to the control logic 300 or exchange data DATA with the column decoder 240.

[0065] During a read operation or a verify operation, the pass / fail check circuit 260 can generate a reference current in response to an enable bit VRY_BIT<#> and output a pass signal PASS or a fail signal FAIL by comparing a sense voltage VPB received from the page buffer group 230 with a reference voltage generated by the reference current.

[0066] The source line driver 270 can be coupled to the memory cells included in the memory cell array 151 through a source line SL and control a voltage applied to the source line SL. For example, during an erase operation, the source line driver 270 can generate an erase voltage and apply the erase voltage to the source line.

[0067] The source line driver 270 can receive a source line control signal CTRL_SL from the control logic 300 and control a source line voltage applied to the source line SL based on the source line control signal CTRL_SL.

[0068] The control logic 300 can output operation signals OP_CMD, row decoder control signals AD_signal, page buffer control signals PBSIGNAL, and enable bits VRY_BIT<#> in response to the command CMD and the address ADD, and control the peripheral circuit 200. The control logic 300 can check whether the verification operation is passed or failed in response to a pass signal PASS or a fail signal FAIL.

[0069] Figure 3 is a diagram illustrating an example of a memory block according to an embodiment of the present application. Figure 2

[0070] Figure 3 is a diagram illustrating an example of a memory block according to an embodiment of the present application. Figure 2 is a diagram illustrating an example of a memory block according to an embodiment of the present application.

[0071] In particular, the memory block 152 can include a plurality of word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> arranged in parallel between a first selection line and a second selection line, where J is a natural number equal to or greater than 1. The first selection line can be a source selection line SSL, and the second selection line can be a drain selection line DSL. In the following description, the first selection line will be denoted by "SSL", and the second selection line will be denoted by "DSL". The plurality of word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> can include normal word lines WL<1:2J> and dummy word lines SPWL<1:2>, CPWL<1:2>, and DPWL<1:2>. Among the plurality of word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2>, one or more word lines adjacent to the source selection line SSL can function as a first dummy word line SPWL<1:2>. Further, among the plurality of word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2>, one or more word lines adjacent to the drain selection line DSL can function as a second dummy word line DPWL<1:2>. Further, among the plurality of word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2>, one or more word lines located at the center can function as a third dummy word line CPWL<1:2>.

[0072] ​More specifically, the memory block 152 can include a plurality of strings ST coupled between bit lines BL1 to BLn and a source line SL. The bit lines BL1 to BLn can be coupled to respective strings ST, and the source line SL can be commonly coupled to the strings ST. Since the strings ST can be configured in the same manner as each other, a string ST coupled to the first bit line BL1 is described as an example.

[0073] The string ST can include a source select transistor SST, a plurality of memory cells, and a drain select transistor DST coupled in series between the source line SL and the first bit line BL1. One string ST can include one or more source select transistors SST and one or more drain select transistors DST.

[0074] The source of the source select transistor SST can be coupled to the source line SL, and the drain of the drain select transistor DST can be coupled to the first bit line BL1. The memory cells can be coupled in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different strings ST can be coupled to a source select line SSL, the gates of the drain select transistors DST included in different strings ST can be coupled to a drain select line DSL, and the gates of the memory cells included in different strings ST can be coupled to a plurality of word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2>. Among the memory cells included in different strings ST, a group of memory cells coupled to the same word line can be referred to as a physical page PPG. Accordingly, the number of physical pages PPG can correspond to the number of normal word lines WL<1:2J> among the plurality of word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> included in the memory block 152.

[0075] One memory cell can store 1-bit data therein. Such a cell is commonly referred to as a single-level cell (SLC).

[0076] In this case, one physical page PPG can store data of one logical page LPG. Data of one logical page LPG can include a plurality of data bits corresponding to the number of cells included in one physical page PPG. In addition, one memory cell can store 2-bit or more data therein. Such a cell is commonly referred to as a multi-level cell (MLC).

[0077] In this case, one physical page PPG can store data of two or more logical pages LPG.

[0078] Figure 4 is a diagram illustrating another example of a memory block according to an embodiment of the present application. Figure 2 is a diagram illustrating another example of a memory block according to an embodiment of the present application.

[0079] Figure 4 An example of a case where the storage blocks are configured in a 3D manner is shown. Figure 2 The storage blocks shown are an example of a case where the storage blocks are configured in a 3D manner.

[0080] Specifically, the storage block 152 can include a plurality of cell strings CS11 to CS1m and CS21 to CS2m. In an embodiment, each of the cell strings CS11 to CS1m and CS21 to CS2m can be formed in a U shape. The storage block 152 can include m cell strings arranged in a row direction (i.e., +X direction). Figure 4 Two cell strings are shown arranged in a column direction (i.e., +Y direction). However, this is merely an example for ease of description, and it can be understood that three or more cell strings can be arranged in the column direction.

[0081] Each of the cell strings CS11 to CS1m and CS21 to CS2m can include one or more source select transistors SST, one or more source side dummy storage units SDC1 and SDC2, first to 2J normal storage units MC1 to MC2J, one or more center dummy storage units CDC1 and CDC2 located at the center of the 2J normal storage unit, a pipe transistor PT, one or more drain side dummy storage units DDC1 and DDC2, and one or more drain select transistors DST.

[0082] The select transistors SST and DST, the dummy storage units SDC1, SDC2, CDC1, CDC2, DDC1, and DDC2, and the normal storage units MC1 to MC2J can have similar structures to each other. In an embodiment, each of the select transistors SST and DST, the dummy storage units SDC1, SDC2, CDC1, CDC2, DDC1, and DDC2, and the normal storage units MC1 to MC2J can include a channel layer, a tunneling dielectric layer, a charge storage layer, and a blocking dielectric layer.

[0083] The source select transistors SST of each cell string can be coupled between a common source line CSL and the source side dummy storage units SDC1 and SDC2.

[0084] In an embodiment, the source select transistors of the cell strings arranged in the same row can be coupled to a source select line extending in the row direction. The source select transistors of the cell strings arranged in different rows can be coupled to different source select lines, respectively. In Figure 4 In the embodiment, the source select transistors of the cell strings CS11 to CS1m of the first row can be coupled to a first source select line SSL1. The source select transistors of the cell strings CS21 to CS2m of the second row can be coupled to a second source select line SSL2.

[0085] Each cell string can include two source side dummy storage cells SDC1 and SDC2. However, this is merely an example, and it can be appreciated that each cell string can include three or more source side dummy storage cells. The source side dummy storage cells SDC1 and SDC2 of each cell string can be serially coupled between a source select transistor SST and normal storage cells MC1 to MCJ. The gate of the first source side dummy storage cell SDC1 of each cell string can be coupled to a first source side dummy word line SPWL1. The gate of the second source side dummy storage cell SDC2 can be coupled to a second source side dummy word line SPWL2.

[0086] Among the first normal storage cell MC1 to the 2Jth normal storage cell MC2J of each cell string, J normal storage cells MC1 to MCJ can be coupled between the source side dummy storage cells SDC1 and SDC2 and the center dummy storage cells CDC1 and CDC2, and the other J normal storage cells MCJ+1 to MC2J can be coupled between the center dummy storage cells CDC1 and CDC2 and the drain side dummy storage cells DDC1 and DDC2.

[0087] The first normal storage cell MC1 to the 2Jth normal storage cell MC2J can be divided into the first normal storage cell MC1 to the Jth normal storage cell MCJ and the (J+1)th normal storage cell MCJ+1 to the 2Jth normal storage cell MC2J. The first normal storage cell MC1 to the Jth normal storage cell MCJ can be sequentially arranged in the opposite direction of the +Z direction and serially coupled between the center dummy storage cells CDC1 and CDC2 and the source side dummy storage cells SDC1 and SDC2. The (J+1)th normal storage cell MCJ+1 to the 2Jth normal storage cell MC2J can be sequentially arranged along the Z direction and serially coupled between the center dummy storage cells CDC1 and CDC2 and the drain side dummy storage cells DDC1 and DDC2. The first normal storage cell MC1 to the Jth normal storage cell MCJ and the (J+1)th normal storage cell MCJ+1 to the 2Jth normal storage cell MC2J can be coupled by a pipe transistor PT. That is, the center dummy storage cells CDC1 and CDC2 can be located at the center of the first normal storage cell MC1 to the 2Jth normal storage cell MC2J and serially coupled to the pipe transistor PT. The gates of the first normal storage cell MC1 to the 2Jth normal storage cell MC2J of each cell string can be coupled to the first normal word line WL1 to the 2Jth normal word line WL2J, respectively.

[0088] Each cell string can include two center dummy storage cells CDC1 and CDC2. However, this is merely an example, and it can be appreciated that each cell string can include three or more source side dummy storage cells. The gate of the first center dummy storage cell CDC1 of each cell string can be coupled to a first center dummy word line CPWL1. The gate of the second center dummy storage cell CDC2 can be coupled to a second center dummy word line CPWL2.

[0089] Data can be stored in the first normal storage cell MC1 to the 2Jth normal storage cell MC2J through the first bit line BL1 to the mth bit line BLm. Data stored in the first normal storage cell MC1 to the 2Jth normal storage cell MC2J can be read through the first bit line BL1 to the mth bit line BLm.

[0090] The gate of the pipe transistor PT of each cell string can be coupled to a pipe line PL.

[0091] Each cell string can include two drain side dummy storage cells DDC1 and DDC2. However, this is merely an example, and it can be appreciated that each cell string can include three or more drain side dummy storage cells. The drain side dummy storage cells DDC1 and DDC2 of each cell string can be coupled in series between a drain select transistor DST and the normal storage cells MCJ+1 to MC2J. The gate of the first drain side dummy storage cell DDC1 of each cell string can be coupled to a first drain side dummy word line DPWL1. The gate of the second drain side dummy storage cell DDC2 of each cell string can be coupled to a second drain side dummy word line DPWL2.

[0092] The drain select transistor DST of each cell string can be coupled between a corresponding bit line and the drain side dummy storage cells DDC1 and DDC2. Cell strings arranged in a row direction can be coupled to a drain select line extending in the row direction. The drain select transistors of the cell strings CS11 to CS1m of a first row can be coupled to a first drain select line DSL1. The drain select transistors of the cell strings CS21 to CS2m of a second row can be coupled to a second drain select line DSL2.

[0093] Cell strings arranged in a column direction can be coupled to a bit line extending in the column direction. In Figure 4 In particular, the cell strings CS11 and CS21 of a first column can be coupled to a first bit line BL1. The cell strings CS1m and CS2m of an mth column can be coupled to an mth bit line BLm.

[0094] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first bit line BL1 to the mth bit line BLm. Even-numbered cell strings of the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction can be respectively coupled to the even-numbered bit lines, and odd-numbered cell strings of the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction can be respectively coupled to the odd-numbered bit lines.

[0095] Each of the dummy storage units SDC1, SDC2, CDC1, CDC2, DDC1, and DDC2 can be provided to stably control the voltage or current of the corresponding cell string. For example, the source side dummy storage units SDC1 and SDC2 can be provided to reduce the electric field between the source select transistor SST and the normal storage units MC1 to MCJ. For example, the drain side dummy storage units DDC1 and DDC2 can be provided to reduce the electric field between the drain select transistor DST and the normal storage units MCJ+1 to MC2J. For example, the center dummy storage units CDC1 and CDC2 can be provided to divide the normal storage units MC1 to MC2J into two groups, MC1 to MCJ and MCJ+1 to MC2J, and reduce the electric field between the two groups. The more dummy storage units are provided, the higher the operation reliability of the memory block 152 can be improved, but the size of the memory block 152 can increase. The fewer dummy storage units are provided, the smaller the size of the memory block 152 can be reduced, but the operation reliability of the memory block 152 can decrease.

[0096] Figure 5 is a diagram illustrating another example of a memory block according to an embodiment of the present application. Figure 2 is a diagram illustrating another example of a memory block according to an embodiment of the present application.

[0097] Figure 5 is a diagram illustrating another example of a memory block according to an embodiment of the present application. Figure 2 is a diagram illustrating another example of a memory block according to an embodiment of the present application.

[0098] Specifically, the memory block 152 can include a plurality of cell strings CS11 to CS1m and CS21 to CS2m. The plurality of cell strings CS11 to CS1m and CS21 to CS2m can extend in the +Z direction. Each of the cell strings CS11 to CS1m and CS21 to CS2m can include, stacked on a substrate (not shown) under the memory block BLK1: one or more source select transistors SST, one or more source side dummy storage cells SDC1 and SDC2, first to Jth normal storage cells MC1 to MCJ, one or more center dummy storage cells, (J+1)th to 2Jth normal storage cells MCJ+1 to MC2J, one or more drain side dummy storage cells DDC1 to DDC2, and one or more drain select transistors DST. The one or more center dummy storage cells are not shown and are located between the normal storage cells as shown. Figure 3

[0099] The source select transistors SST of each cell string can be coupled between a common source line CSL and the source side dummy storage cells SDC1 and SDC2. The source select transistors of cell strings arranged in the same row (e.g., CS11 to CS1m) can be coupled to the same source select line (e.g., SSL1). The source select transistors of the cell strings CS11 to CS1m arranged in the first row can be coupled to the first source select line SSL1. The source select transistors of the cell strings CS21 to CS2m arranged in the second row can be coupled to the second source select line SSL2.

[0100] The source side dummy storage cells SDC1 and SDC2 of each cell string can be coupled in series between the source select transistor SST and the normal storage cells MC1 to MCJ. Source side dummy storage cells of the same height can be coupled to the same source side dummy word line. The gates of the first source side dummy storage cell SDC1 and the second source side dummy storage cell SDC2 can be coupled to the first source side dummy word line SPWL1 and the second source side dummy word line SPWL2, respectively.

[0101] The first to Jth normal storage cells MC1 to MCJ of each cell string can be coupled in series between the source side dummy storage cells SDC1 and SDC2 and the center dummy storage cells (not shown). The gates of the first to Jth normal storage cells MC1 to MCJ can be coupled to the first to Jth normal word lines WL1 to WLJ, respectively.

[0102] ​A center dummy storage cell (not shown) of each cell string can be serially coupled between the normal storage cells MC1 to MCJ and the normal storage cells MCJ+1 to MC2J. The center dummy storage cells of the same height can be coupled to the same center dummy word line.

[0103] The (J+1)th normal storage cell MCJ+1 to the 2Jth normal storage cell MC2J of each cell string can be serially coupled between the center dummy storage cell (not shown) and the drain side dummy storage cells DDC1 and DDC2. The gates of the (J+1)th normal storage cell MCJ+1 to the 2Jth normal storage cell MC2J can be coupled to the (J+1)th normal word line WLJ+1 to the 2Jth normal word line WL2J, respectively.

[0104] The drain side dummy storage cells DDC1 and DDC2 of each cell string can be serially coupled between the drain select transistor DST and the normal storage cells MC1 to MC2J. The drain side dummy storage cells of the same height can be coupled to the same source side dummy word line. The gates of the first drain side dummy storage cell DDC1 and the second drain side dummy storage cell DDC2 can be coupled to the first drain side dummy word line DPWL1 and the second drain side dummy word line DPWL2, respectively.

[0105] The drain select transistor DST of each cell string can be coupled between the corresponding bit line and the drain side dummy storage cells DDC1 and DDC2. The drain select transistors of the cell strings arranged in the row direction can be coupled to the drain select line extending in the row direction. The drain select transistors of the cell strings CS11 to CS1m of the first row can be coupled to the first drain select line DSL1. The drain select transistors of the cell strings CS21 to CS2m of the second row can be coupled to the second drain select line DSL2.

[0106] As a result, Figure 5 The storage block 152 of FIG. 1 has Figure 4 The equivalent circuit of the storage block 152 of FIG. 1, except that the pipe transistor PT is excluded from each cell string.

[0107] Figure 6 FIG. 10 is a flowchart describing an example of an erase operation performed by the storage device 150 according to the embodiment of the present application.

[0108] Referring to Figures 1 to 6 An example of an erase operation performed by the storage device 150 according to the embodiment of the present application will be described as follows.

[0109] As described with reference to Figure 2 The storage device 150 can include the storage cell array 151, the peripheral circuit 200, and the control logic 300.

[0110] The memory cell array 151 can include a plurality of memory blocks 152 each including a plurality of memory cells and a plurality of word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> arranged between the first selection line SSL and the second selection line DSL. It has been described above with reference to FIG. 1 that the plurality of memory blocks 152 each include a plurality of memory cells and a plurality of word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> arranged between the first selection line SSL and the second selection line DSL. Figures 3 to 5 A detailed embodiment of the plurality of memory blocks 152 is described.

[0111] The peripheral circuit 200 can apply an erase voltage to the source line or the drain line of the memory block selected from the plurality of memory blocks 152 to perform an erase operation.

[0112] For reference, an operation of erasing a memory cell in a programmed state by raising a potential level of a channel of a selected memory block by applying an erase voltage to a source line or a drain line of the selected memory block can be defined as a gate-induced drain leakage (GIDL)-based erase operation. That is, during the GIDL-based erase operation, electrons stored in a charge storage layer of a memory cell in a programmed state among a plurality of memory cells included in a selected memory block can be untrapped by a high potential level of a channel and a low potential level of a word line WL. Accordingly, the memory cell in the programmed state can be converted to an erased state.

[0113] In a period in which the erase operation is performed (hereinafter, an erase operation period), the control logic 300 can control the peripheral circuit 200 to sequentially select at least one by one the plurality of word lines included in the selected memory block from the word line closest to the first selection line SSL and the second selection line DSL to the word line farthest from the first selection line SSL and the second selection line DSL and apply a first erase enable voltage to the selected word line. Also, in the erase operation period, the control logic 300 can control the peripheral circuit 200 to apply a second erase enable voltage to the remaining word lines among the plurality of word lines included in the selected memory block except for the word line selected to apply the first erase enable voltage.

[0114] At this time, the first erase enable voltage can have a lower potential level than the second erase enable voltage. For example, when the second erase enable voltage has a ground voltage level VSS, the first erase enable voltage can have a negative level lower than the ground voltage level VSS. For example, the first erase enable voltage can have a level of -2V.

[0115] More specifically, in S10, the memory device 150 can receive an erase command from the controller 130. At this time, the controller 130 can generate the erase command and transmit the generated erase command to the memory device 150 according to a request of the host 102. Also, the controller 130 can generate the erase command and transmit the generated erase command to the memory device 150 according to an internal operation (for example, a background operation such as garbage collection).

[0116] In the erase operation period S20, the storage device 150 can perform an erase operation in response to an erase command.

[0117] As described above, the control logic 300 included in the storage device 150 can control the operation of the peripheral circuit 200 in response to an erase command transmitted from the controller 130 to perform an erase operation.

[0118] For example, the control logic 300 can control the peripheral circuit 200 to select a storage block among the plurality of storage blocks 152 and perform an erase operation in response to an erase command.

[0119] Further, in the erase operation period S20, the control logic 300 can control the source line driver 270 included in the peripheral circuit 200 to apply an erase voltage to the source line of the storage block selected from the plurality of storage blocks 152 in S21. At this time, under the control of the control logic 300, the voltage generating circuit 210 included in the peripheral circuit 200 can generate an erase voltage, and supply the generated erase voltage to the source line driver 270 in the erase operation period.

[0120] Further, in the erase operation period S20, the control logic 300 can control the source line driver 270 included in the peripheral circuit 200 to select one or more word lines from among the plurality of word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> included in the selected storage block in S22 and S23, and apply a first erase enable voltage to the selected one or more word lines.

[0121] Further, in the erase operation period S20, the control logic 300 can control the source line driver 270 included in the peripheral circuit 200 to apply a second erase enable voltage to the remaining word lines other than the selected word lines among the plurality of word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> included in the selected storage block in S22 and S24.

[0122] Further, in the erase operation period S20, the control logic 300 can control the source line driver 270 included in the peripheral circuit 200 to float the first selection line SSL and the second selection line DSL in the local line of the selected storage block. Further, in the erase operation period S20, the control logic 300 can control the page buffer group 230 included in the peripheral circuit 200 to float the bit line of the selected storage block.

[0123] Further, in the erase operation period S20, the control logic 300 can check in S25 whether each of the plurality of word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> included in the selected memory block has been selected once as the selected word line and has received the first erase enable voltage. When the check result indicates that each of the word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> has been selected once (YES in S25), the control logic 300 can control the source line driver 270 included in the peripheral circuit 200 to apply the second erase enable voltage to all of the word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> in S26 until the erase operation period S20 ends after a predetermined time has elapsed. When the check result indicates that there is an unselected word line among the plurality of word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> (NO in S25), the control logic 300 can select the unselected word line and apply the first erase enable voltage to the selected word line in S22 and S23.

[0124] Figures 8A to 8C The peripheral circuit 200 of the storage device 150 according to the embodiment of the present application is shown to select the plurality of word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> in the erase operation period S20 and to apply which erase enable voltage to the selected word line.

[0125] First, Figures 8A to 8C The plurality of word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> can include, for example, as shown in Figures 3 to 5 the source side dummy word lines SPWL1 and SPWL2, the center dummy word lines CPWL1 and CPWL2, and the drain side dummy word lines DPWL1 and DPWL2. The configuration including the dummy word lines is only an embodiment, and some dummy word lines can be provided or no dummy word line can be provided according to the designer's choice.

[0126] Figure 8AThe operation (A) of the peripheral circuit 200 shows a state immediately after the erase operation period S20 is started. That is, the peripheral circuit 200 can apply the erase voltage to the source line SL of the selected memory block, and float the first selection line SSL and the second selection line DSL. The peripheral circuit 200 can select, as the selected word line, the word line closest to the respective first selection line SSL and second selection line DSL from among the plurality of word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> included in the selected memory block (i.e., the second source side dummy word line SPWL2 and the first drain side dummy word line DPWL1), and apply the first erase enable voltage to the selected word line. In addition, the peripheral circuit 200 can apply the second erase enable voltage to the remaining word lines SPWL<1>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<2> other than the selected word line (i.e., the second source side dummy word line SPWL2 and the first drain side dummy word line DPWL1) from among the plurality of word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> included in the selected memory block.

[0127] Figure 8A The operation (B) of the peripheral circuit 200 shows a state during the erase operation period S20 after the operation (A). Figure 8A The operation (A) of the peripheral circuit 200 shows a state immediately after the erase operation period S20 is started. That is, the peripheral circuit 200 can apply the erase voltage to the source line SL of the selected memory block, and float the first selection line SSL and the second selection line DSL. The peripheral circuit 200 can select, as the selected word line, the word line closest to the respective first selection line SSL and second selection line DSL from among the plurality of word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> included in the selected memory block (i.e., the second source side dummy word line SPWL2 and the first drain side dummy word line DPWL1), and apply the first erase enable voltage to the selected word line. In addition, the peripheral circuit 200 can apply the second erase enable voltage to the remaining word lines SPWL<1>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<2> other than the selected word line (i.e., the second source side dummy word line SPWL2 and the first drain side dummy word line DPWL1) from among the plurality of word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> included in the selected memory block.

[0128] Figure 8B The operation (A) of the peripheral circuit 200 shows a state immediately after the erase operation period S20 is started. That is, the peripheral circuit 200 can apply the erase voltage to the source line SL of the selected memory block, and float the first selection line SSL and the second selection line DSL. The peripheral circuit 200 can select, as the selected word line, the word line closest to the respective first selection line SSL and second selection line DSL from among the plurality of word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> included in the selected memory block (i.e., the second source side dummy word line SPWL2 and the first drain side dummy word line DPWL1), and apply the first erase enable voltage to the selected word line. In addition, the peripheral circuit 200 can apply the second erase enable voltage to the remaining word lines SPWL<1>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<2> other than the selected word line (i.e., the second source side dummy word line SPWL2 and the first drain side dummy word line DPWL1) from among the plurality of word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> included in the selected memory block. Figure 8Athe state of the erase operation period S20 after the operation (B) of the peripheral circuit 200. That is, the peripheral circuit 200 can continuously apply the erase voltage to the source line SL of the selected memory block, and float the first selection line SSL and the second selection line DSL. Further, the peripheral circuit 200 can select, as the selected word lines, two word lines of the plurality of word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> that are located at the center (i.e., the first center dummy word line CPWL1 and the second center dummy word line CPWL2) from the first selection line SSL and the second selection line DSL, and apply the first erase enable voltage to the selected word lines. Further, the peripheral circuit 200 can apply the second erase enable voltage to the remaining word lines SPWL<1:2>, WL<1:J>, WL<J+1:2J>, and DPWL<1:2> of the plurality of word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> included in the selected memory block other than the selected word lines (i.e., the first center dummy word line CPWL1 and the second center dummy word line CPWL2).

[0129] Figure 8B The operation (B) of the peripheral circuit 200 shows a state in which, after the operation (A), the operation of selecting two word lines of the plurality of word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> as the selected word lines has been repeated (J+3) times as the erase operation period S20 has continued. Figure 8B The operation (B) of the peripheral circuit 200 shows a state in which, after the operation (A), the operation of selecting two word lines of the plurality of word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> as the selected word lines has been repeated (J+3) times as the erase operation period S20 has continued.

[0130] Figure 8BThe state after the operation (B) of the peripheral circuit 200 can correspond to a state in which the erase operation period S20 has not ended yet, and each of the word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> included in the selected memory block has been selected as the selected word line once and has received the first erase enable voltage (an example of S25). Therefore, as shown in Figure 8C FIG. 9, the peripheral circuit 200 can apply the second erase enable voltage to all of the word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> included in the selected memory block until the erase operation period S20 ends after the operation (B) of the peripheral circuit 200. Figure 8B That is, the peripheral circuit 200 can no longer apply the first erase enable voltage.

[0131] As described above, in the erase operation period S20, the peripheral circuit 200 can sequentially select the plurality of word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> included in the selected memory block as the selected word line at least one by one from the word lines SPWL<2> and DPWL<1> closest to the first selection line SSL and the second selection line DSL to the word lines CPWL<1:2> farthest from the first selection line SSL and the second selection line DSL. For example, as shown in Figures 8A to 8C FIG. 10, the peripheral circuit 200 can select two word lines as the selected word line at a time, and apply the first erase enable voltage to the selected word line.

[0132] Further, in the erase operation period S20, the peripheral circuit 200 can apply the second erase enable voltage to the remaining word lines other than the word line selected to apply the first erase enable voltage among the plurality of word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> included in the selected memory block. At this time, the second erase enable voltage can be set to a ground voltage level VSS, and the first erase enable voltage can be set to a negative level lower than the ground voltage level VSS. Accordingly, the erase operation of the peripheral circuit 200 sequentially selects the plurality of word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> at least one by one from the word lines SPWL<2> and DPWL<1> closest to the first selection line SSL and the second selection line DSL and located at both ends of the cell string to the word lines CPWL<1:2> farthest from the first selection line SSL and the second selection line DSL and located in the middle of the cell string, applies the first erase enable voltage to the selected word line, and applies the second erase enable voltage to the remaining word line, which can significantly improve the hole mobility, so that the stored electrons in the charge storage layer of the memory cell can be untrapped faster in the program state.

[0133] After the erase operation period S20 ends in which the erase operation is performed for a predetermined time, the storage device 150 can perform an erase verification operation in S30 to check whether the erase operation of the selected memory block has been normally completed. For example, the storage device 150 can check whether the threshold voltage of the memory cell included in the selected memory block is equal to or lower than the target erase threshold voltage.

[0134] When the result S40 of the erase verification operation S30 indicates that the threshold voltage of all memory cells or the first number or more of memory cells is equal to or lower than the target erase threshold voltage, the storage device 150 can determine that the erase operation passes, and when the threshold voltage of the second number or more of memory cells is higher than the target erase threshold voltage, the storage device 150 can determine that the erase operation fails. That is, when the result S40 of the erase verification operation S30 indicates that the erase operation passes (success in S40), the storage device 150 can end the erase operation. When the result S40 of the erase verification operation S30 indicates that the erase operation fails, the storage device 150 can raise the potential level of the erase voltage in S50 and then perform the erase operation S20 again using the erase voltage with the raised potential level.

[0135] For example, the control logic 300 included in the storage device 150 can control the peripheral circuit 200 to perform the erase verification operation S30 after performing the predetermined-time erase operation S20. Also, when the result S40 of the erase verification operation S30 indicates that the erase operation has failed, the control logic 300 can set the erase voltage by raising a potential level of the erase voltage according to an incremental step pulse erase (ISPE) method in S50, and control the peripheral circuit 200 to perform the erase operation S20 again by applying the set erase voltage.

[0136] Figure 7 is a flowchart describing another example of an erase operation performed by the storage device according to an embodiment of the present application.

[0137] Referring to Figures 1 to 5 and Figure 7 Another example of an erase operation performed by the storage device 150 according to an embodiment of the present application will be described as follows.

[0138] As described with reference to Figure 2 , the storage device 150 can include a storage cell array 151, a peripheral circuit 200, and a control logic 300.

[0139] The storage cell array 151 can include a plurality of storage blocks 152 each including a plurality of storage cells and a plurality of word lines LPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> arranged between a first selection line SSL and a second selection line DSL. A specific embodiment of the plurality of storage blocks 152 has been described with reference to Figures 3 to 5 .

[0140] The peripheral circuit 200 can perform an erase operation by applying an erase voltage to a source line or a drain line of a storage block selected from the plurality of storage blocks 152.

[0141] In an erase operation period, the control logic 300 can control the peripheral circuit 200 to sequentially select, at least one by one, the plurality of word lines included in the selected storage block from the word line closest to the first selection line SSL and the second selection line DSL to the word line farthest from the first selection line SSL and the second selection line DSL, and apply a first erase enable voltage to the selected word line. Also, in the erase operation period, the control logic 300 can control the peripheral circuit 200 to apply a second erase enable voltage to the remaining word lines included in the selected storage block except for the word line selected to apply the first erase enable voltage.

[0142] At this time, the first erase enable voltage can have a potential level lower than the second erase enable voltage. For example, when the second erase enable voltage has a ground voltage level VSS, the first erase enable voltage can have a negative level lower than the ground voltage level VSS. For example, the first erase enable voltage can have a level of -2V.

[0143] More specifically, in L10, the storage device 150 can receive an erase command from the controller 130. At this time, according to a request of the host 102, the controller 130 can generate an erase command and transmit the generated erase command to the storage device 150. In addition, according to an internal operation (e.g., a background operation such as garbage collection), the controller 130 can generate an erase command and transmit the generated erase command to the storage device 150.

[0144] In the erase operation period L20, the storage device 150 can perform an erase operation in response to the erase command.

[0145] As described above, the control logic 300 included in the storage device 150 can control the operation of the peripheral circuit 200 in response to the erase command transmitted from the controller 130 to perform an erase operation.

[0146] For example, the control logic 300 can control the peripheral circuit 200 to select a storage block from among the plurality of storage blocks 152 and perform an erase operation in response to the erase command.

[0147] In addition, in the erase operation period L20, in L21, the control logic 300 can control the source line driver 270 included in the peripheral circuit 200 to apply an erase voltage to the source line of the storage block selected from among the plurality of storage blocks 152. At this time, under the control of the control logic 300, the voltage generation circuit 210 included in the peripheral circuit 200 can generate an erase voltage, and provide the generated erase voltage to the source line driver 270 in the erase operation period.

[0148] In addition, in the erase operation period L20, in L22 and L23, the control logic 300 can control the source line driver 270 included in the peripheral circuit 200 to select one or more word lines from among the plurality of word lines LPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> included in the selected storage block, and apply a first erase enable voltage to the selected word line.

[0149] Further, in the erase operation period L20, in steps L22 and L24, the control logic 300 can control the source line driver 270 included in the peripheral circuit 200 to apply the second erase enable voltage to the remaining word lines, except for the selected word line, included in the plurality of word lines LPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> included in the selected memory block.

[0150] Further, in the erase operation period L20, the control logic 300 can control the source line driver 270 included in the peripheral circuit 200 to float the first selection line SSL and the second selection line DSL in the local lines of the selected memory block. Further, in the erase operation period L20, the control logic 300 can control the page buffer group 230 included in the peripheral circuit 200 to float the bit lines of the selected memory block.

[0151] Further, in the erase operation period L20, the control logic 300 can check in L25 whether each of the plurality of word lines LPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> included in the selected memory block has been selected once as the selected word line and has received the first erase enable voltage. When the check result indicates that each of the word lines LPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> has been selected once (YES in L25), the control logic 300 can reset the information for distinguishing the selected word line and the unselected word line among the word lines LPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> in L26. Thus, when each of the word lines LPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> has been selected once (YES in L25), the control logic 300 can reset each of the word lines LPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> to a state where each of the word lines LPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> has never been selected. Then, the control logic 300 can repeat the following operations L22, L23, L24, and L25: selecting the word lines LPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> in turn, applying the first erase enable voltage to the selected word line, and applying the second erase enable voltage to the remaining word lines, until the erase operation period L20 ends after a predetermined time of the erase operation has been performed. When the check result indicates that there is an unselected word line among the plurality of word lines LPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> (NO in L25), the control logic 300 can select the unselected word line and apply the first erase enable voltage to the selected word line in L22 and L23.

[0152] Figure 8A and Figure 8B FIG. 14 shows how the peripheral circuit 200 of the storage device 150 according to the present embodiment selects the plurality of word lines SPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> in the erase operation period L20 and which erase enable voltage the peripheral circuit 200 applies to the selected word line. At this time, since Figure 8A and Figure 8B the description of the erase operation of FIG. 14 is made with reference toFigure 6 The description of the example of the erase operation is disclosed in detail in the description of the example of the erase operation described with reference to Figure 6 Figure 8B After the operation (B) of the example of the erase operation described with reference to Figure 8C However, in another example of the erase operation described with reference to Figure 7 After the operation (B) of the example of the erase operation described with reference to Figure 8B the operation (A) of the example of the erase operation described with reference to Figure 8A That is, in another example of the erase operation described with reference to Figure 7 the operation (A) and (B) of the example of the erase operation described with reference to Figure 8A the operation (A) and (B) of the example of the erase operation described with reference to Figure 8B The storage device 150 can perform the erase verification operation L30 after the erase operation period L20 of a predetermined time is ended, and check whether the erase operation of the selected storage block has been normally completed. For example, the storage device 150 can check whether the threshold voltages of the memory cells included in the selected storage block are equal to or lower than the target erase threshold voltage.

[0153] When the result L40 of the erase verification operation L30 indicates that the threshold voltages of all the memory cells or the first number or more of the memory cells are equal to or lower than the target erase threshold voltage, the storage device 150 can determine that the erase operation is passed, and when the threshold voltages of the second number or more of the memory cells are higher than the target erase threshold voltage, the storage device 150 can determine that the erase operation is failed. That is, when the result L40 of the erase verification operation L30 indicates that the erase operation is passed (success in L40), the storage device 150 can end the erase operation. When the result L40 of the erase verification operation L30 indicates that the erase operation is failed, the storage device 150 can raise the potential level of the erase voltage in L50, and then perform the erase operation L20 again using the erase voltage of which the potential level is raised.

[0154] For example, the control logic 300 included in the storage device 150 can control the peripheral circuit 200 to perform the erase verification operation L30 after the erase operation L20 of a predetermined time is performed. Further, when the result L40 of the erase verification operation L30 indicates that the erase operation is failed, the control logic 300 can set the erase voltage by raising the potential level of the erase voltage according to an incremental step pulse erase (ISPE) method in L50, and control the peripheral circuit 200 to perform the erase operation L20 again by applying the set erase voltage.

[0155]

[0156] ​​As described above, in the erase operation period L20, the peripheral circuit 200 can sequentially select at least one by one, as selected word lines, the plurality of word lines LPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> included in the selected memory block from the word line LPWL<2> and DPWL<1> closest to the first selection line SSL and the second selection line DSL to the word line CPWL<1:2> farthest from the first selection line SSL and the second selection line DSL. For example, as shown in FIGS. 3A and 3B, the peripheral circuit 200 can select two word lines as selected word lines at a time, and apply the first erase enable voltage to the selected word lines. Figure 8A and Figure 8B As shown in FIGS. 3A and 3B, the peripheral circuit 200 can select two word lines as selected word lines at a time, and apply the first erase enable voltage to the selected word lines.

[0157] Further, in the erase operation period L20, the peripheral circuit 200 can apply the second erase enable voltage to the remaining word lines among the plurality of word lines LPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2> included in the selected memory block except for the word lines selected to apply the first erase enable voltage. At this time, the second erase enable voltage can be set to the ground voltage level VSS, and the first erase enable voltage can be set to a negative level lower than the ground voltage level VSS. Thus, the erase operation of the peripheral circuit 200 sequentially selects at least one by one, from the word line LPWL<2> and DPWL<1> closest to the first selection line SSL and the second selection line DSL and located at both ends of the cell string to the word line CPWL<1:2> farthest from the first selection line SSL and the second selection line DSL and located in the middle of the cell string, the plurality of word lines LPWL<1:2>, WL<1:J>, CPWL<1:2>, WL<J+1:2J>, and DPWL<1:2>, applies the first erase enable voltage to the selected word lines, and applies the second erase enable voltage to the remaining word lines, which can significantly improve the hole mobility, so that the stored electrons in the charge storage layer of the memory cell can be untrapped faster in the program state.

[0158] Although various embodiments have been described for illustrative purposes with reference to the accompanying drawings, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the application as defined in the following claims. In addition, the embodiments can be combined to form additional embodiments.

[0159] Cross Reference to Related Applications

[0160] This application claims priority to Korean Patent Application No. 10-2021-0030290, filed on March 8, 2021, the entire contents of which are incorporated herein by reference.

Claims

1. A storage device, the storage device comprising: A storage cell array, the storage cell array comprising a plurality of storage blocks, each of the plurality of storage blocks comprising a plurality of storage cells and a plurality of word lines arranged between a first select line and a second select line; The peripheral circuitry performs the erase operation by applying an erase voltage to the source or drain line of a memory block selected from the plurality of memory blocks. as well as Control logic, which controls the peripheral circuitry to perform the following operations during the period in which the erase operation is executed: From the word line closest to the first selection line to the word line furthest from both the first and second selection lines, select one of multiple word lines sequentially. Simultaneously, from the word line closest to the second selection line to the word line furthest from both the first and second selection lines, select one of multiple word lines sequentially. Apply the first erase enable voltage to the selected word line, and Apply the second erase enable voltage to the remaining word lines except for the selected word line. Wherein, the first erase allow voltage has a lower potential level than the second erase allow voltage.

2. The storage device according to claim 1, wherein, The control logic also controls the peripheral circuit to apply the second erase enable voltage to all word lines after the sequentially selected operation and the first erase enable voltage is applied to all word lines, until the predetermined time period ends.

3. The storage device according to claim 1, wherein, The control logic also controls the peripheral circuit to repeat the sequentially selected operation, the operation of applying the first erase enable voltage, and the operation of applying the second erase enable voltage until the predetermined time period ends.

4. The storage device according to claim 1, wherein, The second erase enable voltage has a ground voltage level, and the first erase enable voltage has a negative level that is lower than the ground voltage level.

5. The storage device according to claim 1, wherein, The multiple word lines include a first dummy word line that is closest to the first selection line, a second dummy word line that is closest to the second selection line, and a third dummy word line that is furthest from both the first and second selection lines.

6. The storage device according to claim 1, wherein, The peripheral circuit includes: A source line driver that applies the erase voltage to the source line; Page buffer groups, the page buffer groups being coupled to the bit lines of each of the plurality of memory blocks, and controlling the bit lines of selected memory blocks to float during the time period; and A line decoder, connected to the local lines of the plurality of memory blocks, and during the time period, floats the first select line and the second select line of the local lines of the selected memory block, applies the first erase enable voltage to the selected word line, and applies the second erase enable voltage to the remaining word lines.

7. The storage device according to claim 1, in, The control logic also controls the peripheral circuit to perform an erase verification operation after the predetermined time period. When the result of the erase verification operation indicates that the erase operation has failed, the control logic also controls the peripheral circuit to increase the potential level of the erase voltage according to the incremental step pulse erase method, and also controls the peripheral circuit to perform the erase operation again with the increased erase voltage.

8. A storage device, the storage device comprising: A storage cell array, the storage cell array comprising a plurality of storage blocks, each of the plurality of storage blocks comprising a plurality of storage cells and a plurality of word lines arranged between a first select line and a second select line; as well as The peripheral circuitry performs the erase operation by applying an erase voltage to the source or drain line of a memory block selected from the plurality of memory blocks. During the period when the erasure operation is performed, the peripheral circuit also performs the following operations: From the word line closest to the first selection line to the word line furthest from both the first and second selection lines, select one of multiple word lines sequentially. Simultaneously, from the word line closest to the second selection line to the word line furthest from both the first and second selection lines, select one of multiple word lines sequentially. Apply the first erase enable voltage to the selected word line, and Apply the second erase enable voltage to the remaining word lines except for the selected word line. Wherein, the first erase allow voltage has a lower potential level than the second erase allow voltage.

9. The storage device according to claim 8, wherein, The peripheral circuit also applies the second erase enable voltage to all word lines after the sequential selection operation and after applying the first erase enable voltage to all word lines, until the predetermined time period ends.

10. The storage device according to claim 8, wherein, The peripheral circuit also repeats the sequential selection operation, the operation of applying the first erase enable voltage, and the operation of applying the second erase enable voltage until the predetermined time period ends.

11. The storage device according to claim 8, wherein, The second erase allow voltage has a ground voltage level, and the first erase allow voltage has a negative level lower than the ground voltage level.

12. The storage device according to claim 8, wherein, The multiple word lines include a first dummy word line that is closest to the first selection line, a second dummy word line that is closest to the second selection line, and a third dummy word line that is furthest from both the first and second selection lines.

13. The storage device according to claim 8, wherein, The peripheral circuit includes: A source line driver that applies the erase voltage to the source line; Page buffer groups, the page buffer groups being coupled to the bit lines of each of the plurality of memory blocks, and controlling the bit lines of selected memory blocks to float during the time period; and A line decoder, connected to the local lines of the plurality of memory blocks, and during the time period, floats the first select line and the second select line among the local lines of the selected memory block, applies the first erase enable voltage to the selected word line, and applies the second erase enable voltage to the remaining word lines.

14. A method of operating a storage device, the storage device comprising: A memory cell array comprising multiple memory blocks, each memory block having multiple memory cells and multiple word lines arranged between a first select line and a second select line, the operation method comprising an erase step, the erase step performing an erase operation by applying an erase voltage to the source or drain line of a memory block selected from the multiple memory blocks, such that the multiple memory cells included in the selected memory block have a threshold voltage equal to or less than a target erase voltage. The erasure step includes the following steps: From the word line closest to the first selection line to the word line furthest from both the first and second selection lines, select one of multiple word lines sequentially. Simultaneously, from the word line closest to the second selection line to the word line furthest from both the first and second selection lines, select one of multiple word lines sequentially. Apply the first erase enable voltage to the selected word line, and The second erase enable voltage is applied to the remaining word lines except for the selected word line, and Wherein, the first erase allow voltage has a lower potential level than the second erase allow voltage.

15. The method of operation according to claim 14, further comprising applying a second erase-allowed voltage to all word lines after the sequentially selected steps and after applying the first erase-allowed voltage to all word lines, until the erase step, which has been performed for a predetermined time, is completed.

16. The operating method of claim 14, further comprising repeating the sequentially selected steps, the step of applying the first erase-allowed voltage, and the step of applying the second erase-allowed voltage, until the erasure step, which has been performed for a predetermined time, is completed.

17. The operating method according to claim 14, wherein, The second erase allow voltage has a ground voltage level, and the first erase allow voltage has a negative level lower than the ground voltage level.

18. The operating method according to claim 14, wherein, The multiple word lines include a first dummy word line that is closest to the first selection line, a second dummy word line that is closest to the second selection line, and a third dummy word line that is furthest from both the first and second selection lines.

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