A method for improving wafer edge damage
By using chemical vapor deposition (CVD) to thicken the oxide hard mask layer in the wafer edge region, the problem of silicon needle or silicon spike damage during deep reactive ion etching is solved, achieving higher process stability and lower production costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2021-03-05
- Publication Date
- 2026-05-22
AI Technical Summary
In the current technology, during the deep reactive ion etching process, silicon needles or spikes are damaged in the wafer edge area due to the thinning of photoresist thickness and the slope, which affects product yield and contaminates the cleaning equipment.
Chemical vapor deposition (CVD) is used to deposit an oxide hard mask layer with a thickness greater than that in other areas at the wafer edge. The thickness of the hard mask layer is controlled by adjusting the gas flow rate to form a second hard mask layer to protect the edge area and avoid damage during deep reactive ion etching.
It effectively protects the wafer edge area, avoids damage from silicon needles or spikes, improves process stability and production efficiency, and reduces production costs.
Smart Images
Figure CN115036217B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for improving wafer edge damage. Background Technology
[0002] Currently, to achieve special performance in semiconductor devices, process technologies such as Deep Reactive Ion Etching (DRIE), Deep Trench Isolation, and Super Junction have been widely used in the fabrication of high-voltage device processors. Because these processors typically require non-isotropic etching of tens of micrometers, damage such as silicon grass or black silicon spikes generated by plasma etching in the exposed wafer edge areas during this deep reactive ion etching process is becoming increasingly difficult to control. This damage generates numerous particles in subsequent wet cleaning processes, severely impacting product yield and contaminating cleaning equipment.
[0003] Generally, edge beed removal (EBR) is used in STI lithography to remove edges and prevent defects caused by peeling. EBR typically includes chemical and optical methods. The chemical method uses a nozzle mounted on the equipment to spray a small amount of solvent onto the bottom of the spin-coated silicon wafer, with the solvent flowing from the angled edge to the top edge. The optical method, also known as wafer edge exposure (WEE), involves exposing the wafer edges with a laser after wafer exposure, followed by removal of residues in the development step or with a special solvent sprayed from a specially designed nozzle.
[0004] However, in shallow trench isolation (STI) lithography, edge removal using EBR (Extended Batch Removal) results in thinner photoresist at the wafer edge and edge slopes. During deep reactive ion etching (DRIE), the insufficient photoresist thickness at the wafer edge fails to prevent strong ion bombardment from damaging the underlying material. Subsequent removal of the hard mask layer using Chemical Mechanical Polishing (CMP) leads to damage such as silicon grains or black silicon spikes at the wafer edge.
[0005] Existing technologies employ optimized trench lithography processes such as "inverted trapezoidal" and "negative photoresist" to address this damage. The "inverted trapezoidal" process forms an inverted trapezoidal positive photoresist at the edge, while the "negative photoresist" process forms a negative photoresist in the edge region. During deep reactive ion etching (DRIE), the thickness of the photoresist in the edge region is greater than the thickness of the photoresist outside the edge region to protect the edge silicon substrate, thus solving the problem of silicon needle or silicon spike damage at the wafer edge during DIE. Summary of the Invention
[0006] Based on the above analysis, the present invention aims to provide a method for improving wafer edge damage, thereby solving the problem of substrate silicon (Si) exposure caused by thinning of photoresist thickness and edge slopes at the wafer edge due to edge removal processes (EBR) in the prior art. During deep reactive ion etching, strong ion bombardment damages the underlying material, resulting in damage such as silicon blades or black silicon at the edges.
[0007] This invention provides a method for improving wafer edge damage, comprising:
[0008] Provide semiconductor substrates;
[0009] A stop layer and a first hard mask layer are formed sequentially from bottom to top on the semiconductor substrate, and photoresist is applied on the first hard mask layer.
[0010] Remove the photoresist in the edge region and the first hard mask layer directly below the edge region to expose the stop layer in the edge region, forming a blank area above the edge stop layer;
[0011] Remove the photoresist above the retained first hard mask layer to expose the top surface of the retained first hard mask layer;
[0012] A second hard mask layer is formed in the area enclosed by the stop layer above the exposed edge region and the side of the first hard mask layer.
[0013] Further, the removal of the photoresist in the edge region and the first hard mask layer directly below the edge region exposes the stop layer in the edge region, forming a blank area above the edge stop layer, including:
[0014] Remove the photoresist from the edge area to expose the edge area of the first hard mask layer;
[0015] Remove the exposed edge region of the first hard mask layer to expose the edge region of the stop layer;
[0016] The side of the first hard mask layer after removing the edge region is flush with the side of the photoresist after removing the edge region.
[0017] Furthermore, it also includes performing a deep reactive ion etching process after forming the second hard mask layer, and removing the first hard mask layer and the second hard mask layer after the deep reactive ion etching process is completed.
[0018] Furthermore, from the side of the first hard mask layer to the side of the wafer, the thickness of the second hard mask layer in the direction perpendicular to the wafer surface is greater than the thickness of the first hard mask layer.
[0019] Furthermore, both the first hard mask layer and the second hard mask layer are made of oxide materials.
[0020] Furthermore, the method for forming the first hard mask layer, the second hard mask layer, and the stop layer is a chemical vapor deposition (CVD) process.
[0021] Furthermore, the material of the stop layer is a nitride.
[0022] Furthermore, the method for removing photoresist from the edge region is an edge removal process (EBR).
[0023] Furthermore, the first hard mask layer is removed using either dry etching or wet etching processes.
[0024] Furthermore, the thickness of the second hard mask layer is adjusted by regulating the gas flow rate in the chemical vapor deposition (CVD) process.
[0025] Further, after forming the second hard mask layer, deep reactive ion etching (DRIE) is performed.
[0026] Furthermore, the method for removing the first hard mask layer and the second hard mask layer is chemical mechanical polishing (CMP).
[0027] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:
[0028] (1) Existing technologies use EBR for edge removal, resulting in thinner photoresist at the wafer edge and exposure of the substrate silicon (Si) due to slope. This invention uses chemical vapor deposition (CVD) process, and by adjusting the gas flow rate, the thickness of the oxide hard mask layer deposited in the wafer edge region is greater than the thickness of the oxide hard mask layer in the region outside the edge.
[0029] (2) During deep reactive ion etching (DRIE), the wafer edge area is protected by a thick oxide hard mask layer, and the wafer edge area is not etched, thus avoiding the generation of silicon needles or silicon spikes.
[0030] (3) Existing technologies utilize optimized trench lithography processes, employing either "inverted trapezoidal" or "negative photoresist" processes to address this type of damage. The "inverted trapezoidal" process forms an inverted trapezoidal photoresist at the wafer edge, making it difficult to control the trench linewidth and unsuitable for mass production; the "negative photoresist" process requires forming negative photoresist in the wafer edge region. Compared to optimized trench lithography, the chemical vapor deposition (CVD) process used in this invention offers higher process stability, shorter processing time, and higher production efficiency. Furthermore, the equipment used is cheaper than lithography machines and photomasks, and the required material, tetraethyl orthosilicate (TEOS), is cheaper than photoresist, thus reducing production costs.
[0031] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description
[0032] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.
[0033] Figure 1 This is a flowchart of a method for improving wafer edge damage according to the present invention;
[0034] Figure 2a This is a schematic diagram showing a stop layer, a first hard mask layer, a photoresist coating, and the removal of photoresist from the edge areas on a semiconductor substrate, formed sequentially from bottom to top.
[0035] Figure 2b A schematic diagram showing the removal of the edge region of the first hard mask layer;
[0036] Figure 2c A schematic diagram showing the removal of photoresist in the area above the retained first hard mask layer;
[0037] Figure 2d This is a schematic diagram of the formation of a second hard mask layer after chemical vapor deposition (CVD).
[0038] Figure 2e This is a schematic diagram of deep reactive ion etching.
[0039] Figure label:
[0040] 101-Semiconductor substrate; 102-Stop layer; 103-First hard mask layer; 104-Photoresist; 105-Second hard mask layer. Detailed Implementation
[0041] Removing photoresist at the wafer edge using the EBR process results in thinner photoresist thickness and edge slope. During deep reactive ion etching (DRIE), the photoresist thickness at the wafer edge is insufficient to withstand strong ion bombardment, damaging the underlying substrate. Subsequent removal of the hard mask layer using Chemical Mechanical Planarization (CMP) will result in damage such as silicon grass or black silicon spikes at the wafer edge.
[0042] This invention provides a method for improving wafer edge damage, comprising:
[0043] Provide semiconductor substrates;
[0044] A stop layer and a first hard mask layer are formed sequentially from bottom to top on the semiconductor substrate, and photoresist is applied on the first hard mask layer.
[0045] Remove the photoresist in the edge region and the first hard mask layer directly below the edge region to expose the stop layer in the edge region, forming a blank area above the edge stop layer;
[0046] The photoresist above the retained first hard mask layer is removed by etching, exposing the top surface of the retained first hard mask layer;
[0047] A second hard mask layer is formed in the area enclosed by the stop layer above the exposed edge region and the side of the first hard mask layer.
[0048] After the second hard mask layer is formed, a deep reactive ion etching process can be performed. After the deep reactive ion etching process is completed, the first hard mask layer and the second hard mask layer are removed.
[0049] Existing technologies protect wafer edges by optimizing trench lithography processes, employing "inverted trapezoidal" and "negative photoresist" techniques. The "inverted trapezoidal" process involves coating a layer of photoresist onto the wafer and exposing it without development; then, another layer of photoresist is coated, exposed, and developed. The second layer develops at a slower rate than the first, and the exposure focus and development coagulation time are adjusted during the second layer application, ultimately forming an inverted trapezoidal positive photoresist at the wafer edge. However, the "inverted trapezoidal" process requires two photoresist coatings, resulting in high lithography costs, difficulty in controlling trench linewidth, and poor process stability, making it unsuitable for mass production. While the "negative photoresist" process involves coating only a single layer of negative photoresist onto the wafer, which remains after exposure and development to form an edge protection ring, it still utilizes the same lithography process and remains very expensive.
[0050] Considering the complexity and high production cost of the photolithography process used for "negative photoresist," this invention employs chemical vapor deposition (CVD) to thicken the hard mask oxide layer at the wafer edge to address edge damage. After the hard mask oxide layer edges are etched during the edge removal process, a thick oxide hard mask layer is rapidly deposited at the wafer edge using CVD. Thus, during deep reactive ion etching (DRIE), the silicon substrate (Si) at the wafer edge is protected by the thickened oxide hard mask layer, preventing damage such as silicon spikes or punctures during hard mask layer removal.
[0051] Compared with existing technologies, this invention uses chemical vapor deposition (CVD) to thicken the hard mask oxide layer in the wafer edge region to solve the edge damage problem. Simultaneously, by adjusting the gas flow rate, the thickness of the oxide hard mask layer deposited in the wafer edge region can be made greater than the thickness of the oxide hard mask layer outside the edge region. During deep reactive ion etching (DRIE), the wafer edge region is protected by the thick oxide hard mask layer, preventing etching of the wafer edge region and avoiding silicon spike or burr damage. Compared with optimized trench lithography, this invention offers higher process stability, shorter processing time, higher production efficiency, and lower production cost.
[0052] In order to increase the thickness of the hard mask oxide in the wafer edge region and effectively control the thickness of the hard mask oxide in the edge region, the present invention adopts a separate forming of the second hard mask layer, instead of directly forming the second hard mask layer on the basis of the first hard mask layer.
[0053] First, a stop layer and a first hard mask layer are formed sequentially from bottom to top on a semiconductor substrate, and photoresist is coated on the first hard mask layer.
[0054] It should be noted that the aforementioned semiconductor substrate can be Si, Ge, SiGe, or SOI, etc.; the stop layer is a nitride, which can include SiN, SiON, TiN, or WN; the hard mask layer is an oxide, which can be silicon oxide; the photoresist can include G-line photoresist, I-line photoresist, KrF photoresist, and ArF photoresist. Photoresists are classified according to the applicable exposure wavelength into G-line photoresist (wavelength 436nm), I-line photoresist (wavelength 365nm), KrF photoresist (wavelength 248nm), and ArF photoresist (wavelength 193nm). G-line and I-line photoresists both use linear phenolic resin as the main resin and diazonaphthoquinone (DQN) as the photosensitizer. KrF photoresists use poly(p-hydroxystyrene) and its derivatives as the film-forming resin and iodonium sulfonate and thiodonium sulfonate as photosensitizers. ArF photoresists mostly use polymethyl methacrylate derivatives, cyclic olefin-maleic anhydride copolymers, and cyclic polymers as film-forming resins. Due to their chemical structure, KrF photoresists require more sensitive photoresists than KrF photoresists. As pattern linewidths become increasingly smaller, this invention primarily uses the other three types.
[0055] Specifically, a stop layer nitride is formed on a semiconductor substrate using a chemical vapor deposition (CVD) process. For example, low-pressure chemical vapor deposition (LPCVD) can be used. A mixture of silicon dichlorosilane (SiCl2H2) and ammonia (NH3) is introduced into an oxidation furnace, and a silicon nitride stop layer with a thickness of 100 Å to 5000 Å is formed on the substrate under conditions of a pressure of 0.1 Torr to 1 Torr and a temperature of 700°C to 800°C.
[0056] Alternatively, silicon nitride films can be prepared using atmospheric pressure chemical vapor deposition (APCVD), but this method produces amorphous films that generally contain a large amount of hydrogen. High ammonia content and low deposition temperature will increase the hydrogen content.
[0057] After the stop layer is formed, a first hard mask layer is formed on top of the stop layer. Using chemical vapor deposition (CVD), a mixture of silicon dichlorosilane (SiCl2H2) and ammonia (N2O) or O2 is introduced into the oxidation furnace. Under conditions of pressure of 0.1 Torr-10 Torr and temperature of 450℃-900℃, a first hard mask layer of silicon oxide with a thickness of 1500 Å-4000 Å is deposited.
[0058] Photoresist is coated over the first hard mask layer, specifically using a spin coating method. The thickness of the photoresist coating is adjusted by changing the spin coating speed, spin coating time, and drop volume at different stages. In the initial stage, the spin coating speed is set to 100rpm-200rpm to ensure uniform coverage of the silicon wafer by the photoresist. The speed is then increased to the final spin coating speed, which can be set to 3000rpm-6000rpm, resulting in a photoresist coating thickness ranging from 100nm to 4800nm.
[0059] Next, the photoresist in the edge region is removed to expose the edge region of the first hard mask layer. For example, an edge removal process (EBR) is used to remove the photoresist in the edge region.
[0060] Specifically, a small amount of solvent is first sprayed onto the bottom of the spin-coated silicon wafer through a nozzle on the equipment. The solvent moves from the inclined edge to the top edge to clean the photoresist on the bottom and edges. Then, the wafer edges are exposed and developed to remove residual photoresist.
[0061] After removing the photoresist from the edge region, a portion of the first hard mask layer is exposed, i.e., the first hard mask layer in the edge region. This edge region's hard mask layer is then removed. Exemplarily, the silicon oxide of the first hard mask layer in the edge region can be removed by etching using dry etching. Dry etching commonly uses CF4 as the primary gas, mixed with N2. Alternatively, the O2 and N2 content can be increased simultaneously to dilute the fluorine group concentration and reduce the etching rate of the underlying nitride layer.
[0062] Alternatively, wet etching can be used in another possible implementation. In wet etching, silicon oxide can be etched with hydrofluoric acid (HF), and often with dilute hydrofluoric acid buffered with ammonium fluoride (called buffered silicon oxide etchant BOE or buffered hydrofluoric acid BHF).
[0063] After sequentially removing the photoresist in the edge regions and the corresponding edge regions of the first hard mask layer, a portion of the stop layer is exposed, i.e., the edge regions of the corresponding stop layer. The side of the first hard mask layer after removing the edge regions is flush with the side of the photoresist after removing the edge regions. Then, the photoresist remaining above the first hard mask layer is removed. For example, the etching removal of the photoresist above the first hard mask layer, i.e., the photoresist in the retained photoresist region, adopts a process of first ashering followed by a full wet strip. Specifically, first, ashering is performed to oxidatively decompose the organic matter in the photoresist at 100℃-200℃, with oxygen (O2) as the main gas. N2 or H2 is usually added to improve the photoresist removal performance and enhance the removal of residual polymers. Next, a full wet strip is performed, first using a mixture of strong sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) to remove residual photoresist. Finally, rinse with deionized water for 20-30 minutes at a temperature of 70℃-80℃ to remove residual particles from the silicon wafer surface.
[0064] After removing the photoresist above the first hard mask layer, the top surface of the first hard mask layer is exposed. At this point, the exposed surface includes the stop layer edge region, the side surface of the first hard mask layer, and the top surface region of the first hard mask layer. In other words, the top surface of the stop layer edge region and the side surface of the first hard mask layer form a stepped blank area. To address the edge damage problem, this invention pre-thickens the hard mask layer in the wafer edge region. Therefore, a second hard mask layer with adjustable and controllable thickness is formed in the stepped blank area. One side of the second hard mask layer connects to the side surface of the first hard mask layer to form a complete hard mask layer, providing effective protection during subsequent deep reactive ion etching (DRIE).
[0065] Specifically, a second hard mask layer is formed in the area enclosed above the edge stop layer and on the side of the first hard mask layer. When the thickness of the second hard mask layer is less than that of the first hard mask layer, during deep reactive ion etching (DRIE), the thinner second hard mask layer cannot prevent strong ion bombardment from damaging the underlying material. After the hard mask layer is removed by chemical mechanical polishing (CMP), silicon grass or black silicon spikes will still appear at the wafer edge.
[0066] Therefore, from the side of the first hard mask layer to the side of the wafer, the thickness of the second hard mask layer in the direction perpendicular to the wafer surface is greater than the thickness of the first hard mask layer. Preferably, the thickness of the second hard mask layer increases in the direction perpendicular to the wafer surface, and the size of the second hard mask layer is less than 1 cm along the wafer radial direction. Exemplarily, a silicon oxide second hard mask layer is prepared using a chemical vapor deposition (CVD) process. Specifically, a low-pressure chemical vapor deposition (LPCVD) process can be used. First, liquid TEOS is heated by an independent temperature source and carried into the reactor by a bubbling carrier gas O2. The TEOS concentration is controlled by the carrier gas rate and the temperature of the heating source; the carrier gas can be N2 or He. Next, under conditions of 0.1 Torr-1 Torr pressure and 650℃-750℃, TEOS undergoes thermal decomposition. By adjusting the gas flow rate, a silicon oxide film is formed above the edge stop layer. The growth rate of the silicon oxide film is 100 Å / min-150 Å / min, resulting in a second silicon oxide hard mask layer with a thickness of 4500 Å-6200 Å. Due to the rapid diffusion of gas on the surface, the deposition rate of the silicon oxide film in the edge region is very fast, allowing for the fabrication of a silicon oxide hard mask layer with excellent uniformity. This method is also known as the LPTEOS method.
[0067] Silica films can also be prepared using atmospheric pressure chemical vapor deposition (APCVD) with silanes or TEOS and ozone as raw materials. However, silica prepared with silanes has poor step coverage, while silica prepared with TEOS and ozone is porous. These methods are not suitable for depositing silica above the edge stop layer.
[0068] Specifically, for deep reactive ion etching (DRIE) of wafers, the frequency of the excitation source varies depending on the type of reactor selected, under a pressure of 1 mTorr to 10 mTorr. High-density plasma is generated in the reactor, which can be generated by reactors such as inductively coupled plasma (ICP) and electron cyclotron acceleration (ECR).
[0069] Specifically, after subsequent processes are completed, such as deep reactive ion etching, CMP process is used to remove the first hard mask layer and the second hard mask layer. The nitride stop layer is used as a polishing barrier layer in the CMP process. In order to enable rapid polishing and also to protect the substrate, the polishing ratio of hard mask layer oxide to stop layer nitride is selected to be 5:1-10:1.
[0070] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.
[0071] The accompanying drawings illustrate various structural diagrams related to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, while others may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from actual forms due to manufacturing tolerances or technical limitations. However, those skilled in the art should understand that layers, regions, etc., of desired shapes can be formed using various technical means. Furthermore, those skilled in the art can design methods that are not entirely identical to those described above to form the same structure.
[0072] Throughout the text, the terms “top,” “bottom,” “above,” “on,” “above,” “upper,” and “lower” refer to the relative positions of components within the device, such as the relative positions of the top and bottom substrates inside the device. It is understood that the device is multifunctional, regardless of its orientation in space.
[0073] The working surface of this invention can be a plane or a curved surface, and can be inclined or horizontal. For ease of explanation, the embodiments of this invention are placed on a horizontal surface and used on a horizontal surface, thereby defining "height" and "vertical".
[0074] Example 1
[0075] A specific embodiment of the present invention discloses a method for improving wafer edge damage, the specific process of which is described in the following reference. Figure 1 ;
[0076] Step 01: Provide a semiconductor substrate, and form a stop layer and a first hard mask layer sequentially from bottom to top on the substrate; then, apply photoresist on the hard mask layer; subsequently, remove the photoresist above the edge of the hard mask layer by an edge removal process (EBR) to expose the first hard mask layer in the edge region.
[0077] refer to Figure 2a First, a conductor substrate 101 is provided, and a stop layer silicon nitride 102 is prepared using low-pressure chemical vapor deposition (LPCVD). When the semiconductor substrate 101 reaches the thin film region, a mixture of silicon dichlorosilane (SiCl2H2) and ammonia (NH3) gas is introduced into an oxidation furnace. Under conditions of 0.2 Torr and 760°C, a silicon nitride stop layer 102 with a thickness of 1500 Å is formed above the substrate.
[0078] Next, using the same low-pressure chemical vapor deposition (LPCVD) process, a mixture of silicon dichlorosilane (SiCl2H2) and ammonia (N2O) gas is introduced into the oxidation furnace. Under the conditions of a pressure of 0.4 Torr and a temperature of 600°C, a first hard mask layer 103 with a thickness of 4560 Å is formed above the silicon nitride stop layer 102.
[0079] Next, hexamethylsilane (HMDS) was coated onto the surface of the hard mask layer 103 and placed in a vacuum oven at 200°C for 30 seconds to form the base film and bake. Then, photoresist was coated onto the hard mask 103 using a spin coater. The spin speed was set to 150 rpm and the spin coat time to 10 seconds; subsequently, the speed was increased to a final spin speed of 4500 rpm and the spin coat time was set to 30 seconds, at which point 2000 Å photoresist 104 was coated onto the first hard mask layer 103.
[0080] Finally, an edge removal process (EBR) is used to remove the photoresist 104 in the edge region. A small amount of solvent is sprayed from the bottom of the spin-coated silicon wafer, and the solvent moves from the inclined edge to the top edge to remove the photoresist 104 at the edge and bottom. Then, the edge is exposed and developed to remove the residual photoresist 104 at the edge, exposing the edge region of the first hard mask layer 103.
[0081] Step 02: Use an etching process to remove the exposed edge region of the first hard mask layer, that is, the first hard mask layer above the edge stop layer, to expose the edge region of the stop layer. Then, remove the photoresist above the remaining first hard mask layer to expose the area of the first hard mask layer 103 outside the edge.
[0082] refer to Figure 2b When the wafer reaches the etching area, CF4 gas is introduced into the etching chamber, mixed with O2 and N2, and the first hard mask layer 103 of the edge area is removed by dry etching.
[0083] refer to Figure 2c The photoresist 104 in the reserved area above the first hard mask layer 103 is etched away. First, at a temperature of 150°C, an ashing treatment is performed by introducing a mixture of oxygen (O2) and nitrogen (N2) to remove organic matter from the surface of the first hard mask layer 103. Next, a mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) is used to remove any remaining residue. Finally, the surface of the first hard mask layer 103 is rinsed with deionized water for 25 minutes at a temperature of 75°C to remove residual particles.
[0084] Step 03: Deposit a second hard mask layer in the area enclosed by the top surface of the exposed edge stop layer and the side surface of the first hard mask layer using chemical vapor deposition (CVD).
[0085] refer to Figure 2d A silicon oxide hard mask layer 105 was prepared using low-pressure chemical vapor deposition (LPCVD). Under conditions of 0.5 Torr, 725 °C, and O2 as the bubbling carrier gas, TEOS thermally decomposed to form a 5000 Å thick silicon oxide hard mask layer 105 above the edge stop layer 102, with a growth rate of 125 Å / min.
[0086] Step 04: First, perform deep reactive ion etching (DRIE) on the wafer; then, remove the first and second hard mask layers by mechanical chemical polishing (CMP).
[0087] refer to Figure 2e The wafer is transferred to the etching area and deep reactive plasma etching is performed in an inductively coupled plasma reactor (ICP) under conditions of 5 mTorr pressure and 13.8 MHz radio frequency (RF) receiving frequency.
[0088] Finally, the first hard mask layer 103 and the second hard mask layer 105 are removed by mechanical chemical polishing (CMP) process, and the polishing ratio of silicon oxide in the hard mask layer to silicon nitride in the stop layer 102 is selected to be 10:1.
[0089] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.
Claims
1. A method for improving wafer edge damage in a deep reactive ion etching process, characterized in that, include: Provide semiconductor substrates; A stop layer and a first hard mask layer are formed sequentially from bottom to top on the semiconductor substrate, and photoresist is coated on the first hard mask layer; wherein, the material of the stop layer is nitride, the thickness of the stop layer is 1500Å-5000Å, and the material of the first hard mask layer is oxide; both the first hard mask layer and the stop layer are formed by chemical vapor deposition process. The photoresist in the edge region is removed by first ashing and then wet cleaning to expose the edge region of the first hard mask layer; the first hard mask layer directly below the edge region is removed to expose the stop layer of the edge region, forming a blank area above the edge stop layer. The side of the first hard mask layer after removing the edge region is flush with the side of the photoresist after removing the edge region. Remove the photoresist above the retained first hard mask layer to expose the top surface of the retained first hard mask layer. The top surface of the stop layer edge region and the side surface of the first hard mask layer form a stepped blank area. A second hard mask layer is formed above the stop layer of the exposed edge region and in the area enclosed by the side of the first hard mask layer, with one side of the second hard mask layer adhering to the side of the first hard mask layer; wherein, the method for forming the second hard mask layer is a low-pressure chemical vapor deposition process; the material of the second hard mask layer is an oxide; from the side of the first hard mask layer to the wafer side, the thickness of the second hard mask layer increases in the direction perpendicular to the wafer surface, and the size of the second hard mask layer is less than 1 cm along the wafer radial direction; After the second hard mask layer is formed, a deep reactive ion etching process is performed. After the deep reactive ion etching process is completed, the first hard mask layer and the second hard mask layer are removed. The method for removing the first hard mask layer and the second hard mask layer is chemical mechanical polishing. In the chemical mechanical polishing process, the stop layer serves as a polishing barrier layer, and the polishing ratio of the hard mask layer oxide to the stop layer nitride is 5:1-10:
1.
2. The method for improving wafer edge damage in a deep reactive ion etching process according to claim 1, characterized in that, The method for removing photoresist from the edge region is an edge removal process.
3. The method for improving wafer edge damage in a deep reactive ion etching process according to claim 1, characterized in that, The first hard mask layer is removed using either dry etching or wet etching processes.
4. The method for improving wafer edge damage in a deep reactive ion etching process according to any one of claims 1-3, characterized in that, The thickness of the second hard mask layer is adjusted by regulating the gas flow rate in the chemical vapor deposition process.