Semiconductor device, method of manufacturing the same, and three-dimensional memory system

Abstract

The application provides a semiconductor device, a preparation method thereof and a three-dimensional memory system. The semiconductor device comprises: a stack structure comprising a channel structure part and a word line part, the channel structure part comprising alternately stacked dielectric layers and gate layers; and a plurality of self-aligned contact structures respectively extending to different predetermined depths in the word line part and respectively electrically contacting corresponding gate layers in the channel structure part; wherein a high dielectric constant material is arranged between the electrically contacting areas and the dielectric layers of the channel structure part. The semiconductor device of the application improves electrical safety and stability of the device structure.

Description

Technical Field

[0001] This application relates to the field of three-dimensional memory, specifically to a semiconductor device, its fabrication method, and a three-dimensional memory system. Background Technology

[0002] To improve the storage density of two-dimensional memories, existing technologies have already mass-produced three-dimensional memories such as three-dimensional (3D) NAND. Three-dimensional memories include a stacked structure on a substrate, the stacked structure including a core region with a memory string channel structure and a stepped region for leading out the gate of the memory string channel structure, wherein the core region includes alternating layers of dielectric and gate layers.

[0003] As the number of stacked layers in 3D memory increases, the etching depth of the contact holes also increases accordingly, which places higher demands on the etching process of the contact holes and the stop layer process in the substrate. To simplify the process and steps, self-aligned contact (SCT) structures have been proposed, in which the bottom of each self-aligned contact structure is electrically contacted with the corresponding gate layer.

[0004] However, fabricating SCT structures in three-dimensional memory still involves many process steps and poses problems such as damage to the device structure and reduced device stability. Summary of the Invention

[0005] This application provides a semiconductor device that can at least partially solve the above-mentioned problems existing in the prior art, comprising:

[0006] A stacked structure, including a channel structure portion and a word line portion, wherein the channel structure portion includes alternately stacked dielectric layers and gate layers; and

[0007] Multiple self-aligned contact structures extend to different predetermined depths in the word line portion and respectively make electrical contact with the corresponding gate layer in the channel structure portion;

[0008] A high dielectric constant material is disposed between the electrical contact area and the dielectric layer of the channel structure.

[0009] In one embodiment of this application, each of the self-aligned contact structures includes:

[0010] A letter line leader extends in the stacking direction of the stacked structure, with one end located on the upper surface of the letter line portion; and

[0011] The word line connector extends in a direction perpendicular to the stacking direction and includes a middle portion that is electrically in contact with the other end of the word line lead and an edge portion that is electrically in contact with the corresponding gate layer.

[0012] Wherein, the edge portion of the word line connector has no interface or metal transition region between the electrical contact area and the corresponding contact portion of the gate layer.

[0013] In one embodiment of this application, a high dielectric constant material is provided on the outer wall of the word line connector and the word line lead-out member.

[0014] In one embodiment of this application, the gate layer and the corresponding word line connector have the same thickness; and the thickness of the high dielectric constant material disposed between the word line connector and the dielectric layer of the channel structure is equal to the thickness of the high dielectric constant material disposed between the gate layer and the dielectric layer of the channel structure.

[0015] In one embodiment of this application, the word line portion includes alternating layers of dielectric layers and gate sacrificial layers. Each dielectric layer of the word line portion is in contact with a corresponding dielectric layer of the channel structure portion and is located in the same layer. Each gate sacrificial layer is in contact with a corresponding word line connector and is located in the same layer.

[0016] In one embodiment of this application, the semiconductor device includes: a gate line gap structure extending through the stacked structure, including a first insulating isolation layer and a first filling portion disposed sequentially from the outside to the inside.

[0017] In one embodiment of this application, the self-aligned contact structure further includes: a second insulating isolation layer disposed on the inner sidewall of the word line lead-out member; and a second filling portion filled on the inner side of the inner sidewall of the second insulating isolation layer; wherein the first insulating isolation layer and the second insulating isolation layer are made of the same material, and the first filling portion and the second filling portion are made of the same material.

[0018] The three-dimensional memory of this application has a complete high-k material between the contact portion of the gate layer and the adjacent dielectric layer, which improves electrical safety and the stability of the device structure.

[0019] This application also provides a method for fabricating a semiconductor device, comprising the following steps:

[0020] A stacked layer is formed, the stacked layer including a core region and a step region;

[0021] A gate line slot is formed that penetrates the stacked layers, and the gate line slot is located in the core region and the step region;

[0022] Multiple self-aligned contact holes are formed in the step region of the stacked layer, and the multiple self-aligned contact holes extend to different predetermined depths to the corresponding gate sacrificial layer in the step region of the stacked layer.

[0023] The gate sacrificial layer is removed via the gate line gap, so that the gate gap formed in the core region communicates with the corresponding self-aligned contact hole; and

[0024] Conductive connections are deposited in the gate line gaps, the gate gaps, and the plurality of self-aligned contact holes.

[0025] In one embodiment of this application, removing the gate sacrificial layer via the gate line gap includes: removing the gate sacrificial layer of the stacked layer located in the core region of the stacked layer via the gate line gap located in the core region of the stacked layer to form the gate gap; and removing a portion of the gate sacrificial layer of the stacked layer located in the stepped region of the stacked layer via the gate line gap located in the stepped region of the stacked layer, such that each of the self-aligned contact holes is connected to the corresponding gate gap.

[0026] In one embodiment of this application, after forming the gate wire gaps through the stacked layer, the method further includes: filling the gate wire gaps with a first sacrificial material; and after forming the plurality of self-aligned contact holes in the step region of the stacked layer, the method further includes: filling the plurality of self-aligned contact holes with a second sacrificial material.

[0027] In one embodiment of this application, before removing the gate sacrificial layer of the stacked layer located in the core region, the first sacrificial material in the gate line gap of the core region of the stacked layer is further removed.

[0028] In one embodiment of this application, after forming the gate gap, the method further includes: removing the first sacrificial material from the gate line gap in the step region of the stacked layer and the second sacrificial material from the plurality of self-aligned contact holes.

[0029] In one embodiment of this application, before removing the first sacrificial material in the gate wire gaps of the core region of the stacked layer, the method further includes: forming a protective layer on the upper surface of the stacked layer, and removing the protective layer on the upper surface of the stacked layer located in the core region; before removing the first sacrificial material in the gate wire gaps of the stepped region of the stacked layer and the second sacrificial material of the plurality of self-aligned contact holes, the method further includes: removing the protective layer on the upper surface of the stacked layer located in the stepped region.

[0030] In one embodiment of this application, after forming the plurality of self-aligned contact holes in the step region of the stacked layer, the method further includes: forming an insulating isolation material on the sidewalls of the plurality of self-aligned contact holes; and causing the insulating isolation material to penetrate to the corresponding gate sacrificial layer.

[0031] In one embodiment of this application, after forming an insulating material on the sidewalls of the plurality of self-aligned contact holes, the method further includes: removing a portion of the gate sacrificial layer of the stepped region of the stacked layer that is connected to the bottom of each of the self-aligned contact holes.

[0032] In one embodiment of this application, depositing conductive connections in the gate line gap, the gate gap, and the self-aligned contact holes includes the following steps: depositing a high dielectric constant material on the inner sidewall and bottom of the gate line gap, the inner sidewall of the gate gap, and the inner sidewall of the plurality of self-aligned contact holes; depositing a metal adhesion layer on the inner sidewall of the high dielectric constant material; and depositing a metal material on the inner sidewall of the metal adhesion layer; wherein the metal material filling the gate gap forms a gate layer.

[0033] In one embodiment of this application, after depositing the metal material on the inner sidewall of the metal adhesion layer, the method further includes: removing the metal material from the inner sidewall and bottom of the grid line slots.

[0034] In one embodiment of this application, removing the metal material from the inner sidewall and bottom of the gate wire slot includes the following steps: forming a mask layer covering the plurality of self-aligned contact holes; and removing the metal material from the inner sidewall and bottom of the gate wire slot and the material not covered by the mask layer from the upper surface of the stacked layer.

[0035] In one embodiment of this application, after removing the metal material from the inner sidewall and bottom of the gate wire slot, the method further includes: removing the mask layer; forming a first insulating isolation layer and a second insulating isolation layer on the inner sidewall of the gate wire slot and the inner sidewall of the plurality of self-aligned contact holes, respectively; and forming a first filling portion and a second filling portion in the gate wire slot and the plurality of self-aligned contact holes, respectively.

[0036] The preparation method of this application only adopts a one-step complete high-K material deposition process and metal material filling process, which saves preparation process and cost.

[0037] Another aspect of this application provides a three-dimensional memory system including a controller; and a semiconductor device as described above, the controller being coupled to the semiconductor device and used to control the semiconductor device to store data. Attached Figure Description

[0038] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0039] Figure 1 This is a cross-sectional view of a three-dimensional memory according to one embodiment of this application.

[0040] Figure 2 yes Figure 1 A partially enlarged schematic diagram of the self-aligned contact structure shown.

[0041] Figure 3 This is a flowchart of a method for preparing a three-dimensional memory according to one embodiment of this application.

[0042] Figures 4 to 16 This is a schematic diagram of the fabrication process of a three-dimensional memory according to one embodiment of this application. Detailed Implementation

[0043] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0044] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the feature.

[0045] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. For example, as used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0046] It should also be understood that the terms "comprising," "including," "having," "containing," and / or "comprising" as used in this specification indicate the presence of the stated features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or combinations thereof. Furthermore, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to an example or illustration.

[0047] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0048] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0049] In this application, for ease of description below, the portion of the stacked structure in which a channel structure is provided is defined as the channel structure portion, and the portion of the stacked structure in which a self-aligned contact structure is provided is defined as the word line portion.

[0050] Figure 1 This is a cross-sectional view of a semiconductor device 1 according to one embodiment of this application. The semiconductor device 1 may be a three-dimensional memory or a portion thereof; therefore, in the specific embodiments of this application, the semiconductor device 1 is also referred to as three-dimensional memory 1. Figure 1 As shown, the three-dimensional memory 1 includes a substrate 11; a stacked structure 12' located on the substrate 11, the stacked structure 12' including a channel structure portion 18 and a word line portion 16, the channel structure portion 18 including a memory string channel structure 141 (see... Figure 9 (as shown) and virtual channel structure 142; gate line slot (GLS) structure 13 penetrating stack structure 12'; and self-aligned contact structure 15 provided in word line portion 16.

[0051] The substrate 11 includes a base 111, a stop layer 112, and a substrate sacrificial layer 113 sequentially disposed therefrom. In an exemplary embodiment, the base 111, the stop layer 112, and the substrate sacrificial layer 113 may be silicon, silicon oxide, and polysilicon, respectively. The stop layer 112 and the substrate sacrificial layer 113 may be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, thermal oxidation, or any combination thereof.

[0052] The three-dimensional memory 1 may further include a silicon oxide layer 114 and a polysilicon layer 115 disposed between the substrate 11 and the stacked structure 12, wherein the silicon oxide layer 114 and the polysilicon layer 115 are sequentially disposed on the substrate 11, and the silicon oxide layer 114 and the polysilicon layer 115 may be formed using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. In other embodiments of this application, the three-dimensional memory 1 may not have a silicon oxide layer 114 and a polysilicon layer 115, that is, the stacked structure 12 may be directly stacked on the substrate 11.

[0053] The channel structure 18 includes a plurality of alternately stacked dielectric layers 181 and a plurality of gate layers 182, and a memory string channel structure 141 penetrating the dielectric layers 181 and the gate layers 182 (see [link]). Figure 9(As shown) and virtual channel structure 142. The number of stacked layers of the plurality of dielectric layers 181 and the plurality of gate layers 182 can be 32 layers, 64 layers, or 128 layers, etc. The more stacked layers of the channel structure portion 18, the higher the integration density of the three-dimensional memory 1. In practical applications, the number of stacked layers can be designed according to requirements, and this application does not limit it. In an exemplary embodiment, the gate layer 182 can be a metal material, such as tungsten, and the dielectric layer 181 can be silicon oxide.

[0054] The storage serial channel structure 141 and the virtual channel structure 142 are formed simultaneously in the stacked structure 12' and have the same structure. The following only uses... Figure 1 The virtual channel structure 142 shown is used as an example for explanation. Virtual channel structure 142 ( Figure 1 (Only two of them are shown) extend into the substrate 11, for example, into the substrate sacrificial layer 113. The virtual channel structure 142 includes a charge blocking layer, a charge trapping layer, a tunneling layer, a channel layer, and a channel oxide disposed sequentially from the outside in. The channel oxide is used to fill the channel holes to support the channel holes and improve the stability and reliability of the structure of the three-dimensional memory 1. The material of the charge blocking layer may include silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant (high K) material such as aluminum oxide or hafnium oxide. In this application, the dielectric constant of the high K material is greater than 3, preferably greater than 4. The material of the charge trapping layer may include polycrystalline silicon, silicon nitride, silicon oxynitride, or nanocrystalline silicon. The material of the tunneling layer may include silicon oxide, silicon nitride, silicon oxynitride, or a high K material such as aluminum oxide or hafnium oxide. The material of the channel layer may include silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. In an exemplary embodiment, the materials of the charge blocking layer, charge trapping layer, tunneling layer, channel layer, and channel oxide may be silicon oxide, silicon nitride, silicon oxide, P-type doped polysilicon, and silicon oxide, respectively.

[0055] Word line portion 16 has a structure similar to channel structure portion 18 and has the same number of stacked layers. Word line portion 16 may include a plurality of alternately stacked dielectric layers 161 and a plurality of gate sacrificial layers 162. Each dielectric layer 161 is in contact with a corresponding dielectric layer 181 and is located in the same layer, and each gate sacrificial layer 162 is located in the same layer as a corresponding gate layer 182. The ratio of the etching rate of the gate sacrificial layer 162 to the etching rate of the dielectric layer 161 (i.e., the etching selectivity) is much greater than 1, for example, the etching selectivity is greater than 100. Thus, under the same etching conditions, the gate sacrificial layer 162 can be etched away while the dielectric layer 161 is retained. In an exemplary embodiment, the dielectric layer 161 is made of the same material as the dielectric layer 181, for example, silicon oxide, and the gate sacrificial layer 162 is made of silicon nitride.

[0056] The gate gap structure 13 penetrates the stacked structure 12 and extends into the substrate 11, for example, into the substrate sacrificial layer 113. The gate gap structure 13 includes an insulating isolation layer 131 and a filling portion 132 disposed sequentially from the outside to the inside. The insulating isolation layer 131 may be made of materials such as silicon oxide, silicon nitride, or silicon oxynitride, and the filling portion 132 may be made of materials such as polysilicon or conductive materials.

[0057] The self-aligned contact structure 15 includes a word line lead-out 151 and a word line connector 152 connected together. The word line lead-out 151 extends in the stacking direction of the stacked structure 12', that is, it extends to different predetermined depths along a direction perpendicular to the substrate 11, with one end located on the upper surface of the word line portion 16 and configured to connect with the peripheral circuitry ( Figure 1 Electrical connection (not shown). The word line connector 152 is embedded in the word line portion 16 and is located in the same layer as the corresponding gate sacrificial layer 162 of the word line portion 16. The word line connector 152 extends in a direction perpendicular to the stacking direction of the stacked structure 12', that is, along a direction parallel to the substrate 11, and is configured as a contact portion of the gate layer 182 corresponding to the channel structure portion 18 (hereinafter referred to as the contact portion). Figure 2 (For explanation) Electrical contact. The word line connector 152 includes a middle portion 1521 that is electrically in contact with the word line lead 151 and an edge portion 1522 that is electrically in contact with the corresponding gate layer 182. In one specific embodiment, the middle portion 1521 and the edge portion 1522 are an integral structure. Thus, the gate of the storage string channel structure 141 is electrically connected to the peripheral circuitry through the corresponding word line connector 152 and word line lead 151.

[0058] The self-aligned contact structure 15 may further include an insulating isolator 153 disposed on the outer side wall of the word line lead-out member 151, an insulating isolator layer 154 disposed on the inner side wall of the word line lead-out member 151, and a filler portion 155 filled in the inner side wall of the insulating isolator layer 154. The insulating isolator 153 may be made of materials such as silicon oxide, silicon nitride, or silicon oxynitride. The insulating isolator layer 154 may be made of the same material as the insulating isolator layer 131 of the gate line slot structure 13, and the filler portion 155 may be made of the same material as the filler portion 132 in the gate line slot structure 13.

[0059] Figure 2 yes Figure 1 The diagram shows a partially enlarged view of the self-aligned contact structure 15, where the high-K material and metallic material deposited at the edge 1522 are clearly shown, and other components of the self-aligned contact structure 15 are not shown. This is achieved through a one-step process in the gate gap 1222 and the self-aligned contact hole 150 (see [link to diagram]). Figure 12 (As shown) forms high-k materials and metallic materials, such as Figure 2As shown, the edge portion 1522 of the word line connector 152 is in electrical contact with the corresponding contact portion 1821 of the gate layer 182, and there is a gap between the contact portion 1821 of the gate layer 182 and the edge portion 1522 of the word line connector 152 (i.e., at...). Figure 2 There is no interface or metal transition region (as shown in the dashed box in the image). High-K materials 1571 and 1572 are formed on the outer walls of the word line lead-out member 151 and the word line connector 152, respectively. Furthermore, the contact portion 1821 of the gate layer 182 and the edge portion 1522 of the word line connector 152 have complete (i.e., undamaged or missing) high-K material 183 between them and the two adjacent dielectric layers 181, thereby improving the structural stability and electrical performance of the three-dimensional memory 1. Additionally, the gate layer 182 and the corresponding word line connector 152 have the same thickness, and the thickness of the high-K material 183 between the gate layer 182 and the two adjacent dielectric layers 181 is equal to the thickness of the high-K material 1572 between the word line connector 152 and the two adjacent dielectric layers 181.

[0060] Figure 3 This is a flowchart illustrating a method for fabricating a three-dimensional memory 1 according to one embodiment of this application. (See attached flowchart.) Figure 3 As shown, it includes the following steps:

[0061] Step S11: Form a stacked layer, the stacked layer including a core area and a step area;

[0062] Step S12, forming a gate wire gap that penetrates the stacked layers, the gate wire gap being located in the core region and the step region;

[0063] Step S13: A plurality of self-aligned contact holes are formed in the step region of the stacked layer, and the plurality of self-aligned contact holes extend to different predetermined depths to the corresponding gate sacrificial layer in the step region of the stacked layer.

[0064] Step S14: Remove the gate sacrificial layer via the gate line gap, so that the gate gap formed in the core region is connected to the corresponding self-aligned contact hole; and

[0065] Step S15: Deposit conductive connections in the gate line gaps, the gate gaps, and the plurality of self-aligned contact holes.

[0066] The following will describe in detail the fabrication method of the three-dimensional memory 1 using a structural diagram of the fabrication process.

[0067] Figures 4 to 16 This is a schematic diagram of the structure of a three-dimensional memory 1 according to one embodiment of the present application during the fabrication process.

[0068] Figure 4This is a top view after the channel structure, gate line gaps, and self-aligned contact holes have been formed on the substrate. Figure 5 It is along Figure 4 A cross-sectional view of the stepped area SA cut by line A1-A1'.

[0069] like Figure 4 and Figure 5 As shown, a stacked layer 12 is formed on a substrate 11; a channel structure 14 is fabricated in the stacked layer 12, which includes a memory string channel structure 141 disposed in the core region CA and a virtual channel structure 142 disposed in the step region SA; a gate line gap 13' is fabricated; and a self-aligned contact hole 150 is fabricated in the step region SA of the stacked layer 12. The channel structure 14 is disposed in the channel structure portion 18, and the self-aligned contact hole 150 is disposed in the word line portion 16.

[0070] In an exemplary embodiment, the specific process steps are as follows:

[0071] A stacked layer 12 is formed on the substrate. A stop layer 112 and a substrate sacrificial layer 113 are sequentially formed on the substrate 111 using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, thermal oxidation, or any combination thereof to form the substrate 11. In an exemplary embodiment, the substrate 111, the stop layer 112, and the substrate sacrificial layer 113 may be silicon, silicon oxide, and polycrystalline silicon, respectively.

[0072] Subsequently, a silicon oxide layer 114 and a polysilicon layer 115 are sequentially formed on the substrate 11 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. In other embodiments of this application, the process steps of forming the silicon oxide layer 114 and the polysilicon layer 115 on the substrate 11 may be omitted.

[0073] Next, a stacked layer 12 is fabricated on the substrate 11. Multiple alternating dielectric layers 121 and multiple gate sacrificial layers 122 are fabricated on the substrate 11 using thin-film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The stacked layer 12 includes a core region CA and a step region SA. The number of stacked dielectric layers 121 and gate sacrificial layers 122 can be 32, 64, or 128 layers, etc., and is not intended to be limited thereto. In an exemplary embodiment, the dielectric layer 121 can be made of insulating oxide materials such as silicon oxide, aluminum oxide, hafnium oxide, or tantalum oxide, and the gate sacrificial layer 122 can be made of silicon nitride, which is used to replace a conductive layer (e.g., a tungsten metal layer) in subsequent processes to serve as the gate layer of the memory cell.

[0074] Fabricate the channel structure 14. Etch a portion of the core region CA and step region SA of the stacked layer 12 via a mask pattern to form a channel hole penetrating the stacked layer 12 within the core region CA and step region SA of the stacked layer 12. Figure 5 (Only two of the step regions SA are shown). In other embodiments of this application, the vias may also be formed only in the core region CA of the stacked layer 12. A channel structure 14 is formed in the via, wherein the channel structure 14 formed in the core region CA is a storage string channel structure 141 to realize storage functionality, and the channel structure 14 formed in the step region SA is a virtual channel structure 142 to support the step region SA. The channel structure 14 is generally cylindrical, elliptical cylindrical, frustum-shaped, or cuboid in shape. The channel structure 14 includes, from the outside to the inside, a charge blocking layer, a charge trapping layer, a tunneling layer, a channel layer, and a channel oxide. The material of the charge blocking layer may include silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant (high K) material such as aluminum oxide or hafnium oxide. The material of the charge trapping layer may include polycrystalline silicon, silicon nitride, silicon oxynitride, or nanocrystalline silicon. The material of the tunneling layer may include silicon oxide, silicon nitride, silicon oxynitride, or a high K material such as aluminum oxide or hafnium oxide. The channel layer material may include silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. In an exemplary embodiment, the materials of the charge blocking layer, charge trapping layer, tunneling layer, channel layer, and channel oxide may be silicon oxide, silicon nitride, silicon oxide, p-type doped polycrystalline silicon, and silicon oxide, respectively.

[0075] The gate gap 13' is fabricated. The stacked layer 12 is etched via a mask pattern to form the gate gap 13' in the stacked layer 12. Figure 5 (Only one is shown schematically), wherein the gate gap 13' is located in the core region CA and the step region SA, penetrates the stacked layer 12, and extends into the substrate 11, for example, into the substrate sacrificial layer 113. A first sacrificial material 131' is filled in the gate gap 13' using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The first sacrificial material 131' is removed from the upper surface of the stacked layer 12 by a planarization process such as chemical mechanical polishing (CMP), thereby obtaining a planarized surface. In an exemplary embodiment, the first sacrificial material 131' may be polycrystalline silicon.

[0076] A self-aligned contact hole 150 is formed in the step region SA of the stacked layer 12. A mask layer is formed on the upper surface of the stacked layer 12, and the step region SA of the stacked layer 12 is etched through the mask layer to form the self-aligned contact hole 150 in the step region SA of the stacked layer 12. Figure 4 and Figure 5(Only one is shown schematically). An insulating material is filled into the self-aligned contact hole 150 using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In an exemplary embodiment of this application, the insulating material may be silicon oxide, silicon nitride, or silicon oxynitride, etc. In a specific embodiment of this application, the insulating material on the upper surface of the stacked layer 12 is removed by a planarization process such as chemical mechanical polishing (CMP). A mask layer is formed again on the upper surface of the stacked layer 12, and the intermediate region of the insulating material filled in the self-aligned contact hole 150 is etched via a mask pattern aligned with each of the self-aligned contact holes 150, forming an insulating spacer 153 disposed on the inner sidewall of the self-aligned contact hole 150, wherein the bottom 156 of the self-aligned contact hole 150 contacts the corresponding gate sacrificial layer 122 in the step region SA of the stacked layer 12.

[0077] Figure 6 A three-dimensional schematic diagram of a plurality of self-aligned contact holes 150 formed in the stepped region SA of the stacked layer 12 is shown. Figure 6 The diagram schematically shows fifteen of the self-aligned contact holes 150, in Figure 6 In the schematic diagram shown, the stacked layer 12 does not show its stacked structure and number of layers; it is only used to illustrate that each self-aligned contact hole 150 extends to a different predetermined depth. The number of self-aligned contact holes 150 may be equal to the number of gate sacrificial layers in the stacked layer 12. The bottom of each self-aligned contact hole 150 contacts the corresponding gate sacrificial layer 122 in the stepped region SA of the stacked layer 12, i.e., they are located on the same plane.

[0078] like Figure 7 As shown, a portion of the gate sacrificial layer 122 in the step region SA of the stacked layer 12 that contacts the bottom of the self-aligned contact hole 150 is removed, and a second sacrificial material is filled into the self-aligned contact hole 150. In an exemplary embodiment, by selecting appropriate etching process parameters, a high etching selectivity ratio (e.g., greater than 100) is achieved between the gate sacrificial layer 122 and the dielectric layer 121, thereby removing a portion of the gate sacrificial layer 122 in the step region SA that contacts the bottom 156 of the self-aligned contact hole 150, thus forming a self-aligned contact hole 150 with a generally inverted T-shaped cross-section.

[0079] A second sacrificial material 150' is filled into the self-aligned contact hole 150 using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Then, a planarization process such as chemical mechanical polishing (CMP) is used to remove the second sacrificial material 150' from the upper surface of the stacked layer 12 and planarize it. In an exemplary embodiment, the second sacrificial material 150' filling the self-aligned contact hole 150 may be polycrystalline silicon.

[0080] like Figure 8 As shown, a protective layer 172 is formed on the surface of the stacked layer 12. In embodiments of this application, the specific process is as follows: a protective layer 172 is formed on the upper surface of the stacked layer 12 using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Then, the protective layer 172 is planarized using a planarization process such as chemical mechanical polishing, thereby obtaining a planarized protective layer 172. In an exemplary embodiment, the protective layer 172 may be silicon oxide or silicon oxynitride.

[0081] Figure 9 It is along Figure 4 A cross-sectional view of line B1-B1' in the core area CA, as shown below. Figure 9 As shown, the first sacrificial material 131' in the gate line gap 13' of the core region CA of the stacked layer 12 is removed, and the gate sacrificial layer 122 in the core region CA of the stacked layer 12 is removed. In an exemplary embodiment of this application, the specific process is as follows: a mask layer is formed on the upper surface of the protective layer 172 ( Figure 9 (Not shown), the protective layer 172 on the upper surface of the stacked layer 12 is etched through the mask pattern of the mask layer to remove the protective layer 172 located on the upper surface of the core region CA of the stacked layer 12, thereby exposing the first sacrificial material 131' in the gate line gap 13' of the core region CA of the stacked layer 12. The first sacrificial material 131' in the gate line gap 13' of the core region CA of the stacked layer 12 is removed by the etching process, and then the gate sacrificial layer 122 in the core region CA of the stacked layer 12 is removed, while the dielectric layer 121 in the core region CA is retained. At this time, the dielectric layer 121 in the core region CA is supported by the memory string channel structure 141, and a gate gap 1221 for subsequent filling of metal material is defined between any two adjacent dielectric layers 121, and the gate gap 1221 and the gate line gap 13' are connected.

[0082] Figure 10 The left-side view is along Figure 4 A cross-sectional view taken along line A1-A1' in the stepped area SA of stacked layer 12; the right view is along... Figure 4 A cross-sectional view of line B1-B1' cut in the core region CA of stacked layer 12. (See figure) Figure 10 As shown, the protective layer 172 located on the upper surface of the step region SA of the stacked layer 12 is removed. In an exemplary embodiment, the upper surface of the stacked layer 12 can be planarized by a planarization process such as chemical mechanical polishing, thereby removing the protective layer 172 located on the upper surface of the step region SA of the stacked layer 12.

[0083] like Figure 11 As shown, the first sacrificial material 131' in the gate line slot 13' and the second sacrificial material 150' in the self-aligned contact hole 150 in the step region SA of the stacked layer 12 are removed. In an exemplary embodiment, the first sacrificial material 131' in the gate line slot 13' and the sacrificial material 150' in the self-aligned contact hole 150 are removed by a polysilicon etching process with an ultra-high selectivity.

[0084] like Figure 12 As shown, a portion of the gate sacrificial layer 122 located in the step region SA of the stacked layer 12 is removed. In embodiments of this application, by selecting a suitable etching process, a high etching selectivity ratio (e.g., greater than 100) is achieved between the gate sacrificial layer 122 and the dielectric layer 121, thereby removing a portion of the gate sacrificial layer 122 located in the step region SA to form the gate gap 1222 while retaining the dielectric layer 121 of the step region SA. In an exemplary embodiment, the gate sacrificial layer 122 between the gate line gap 13' and the bottom of each self-aligned contact hole 150 is removed, such that the bottom of the self-aligned contact hole 150 is connected to the corresponding gate gap 1222.

[0085] like Figure 13 As shown, a gate layer and a self-aligned contact structure 15 are simultaneously or in one step fabricated to form electrical contacts. In an exemplary embodiment of this application, the specific process is as follows: a high-k material 183 is deposited on the upper surface of the stacked layer 12, the sidewalls and bottom of the gate line gaps 13', the sidewalls of the gate gaps 1221 and 1222, and the sidewalls of the self-aligned contact hole 150 using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof (see [link to relevant documentation]). Figure 2(As shown), a metal adhesion layer with a thickness of several nanometers is then deposited on the high-K material 183, and finally, metal material 174 is filled on the metal adhesion layer. The metal material 174 filling the gate gaps 1221 and 1222 forms the gate layer 182, and the metal material 174 filling the bottom and sidewalls of the self-aligned contact hole 150 forms the self-aligned contact structure 15 for electrical contact with the gate layer 182, thereby simultaneously forming or one-step depositing metal to ensure good electrical contact between the self-aligned contact structure 15 and the corresponding gate layer 182. At this time, the channel structure portion 18 is formed in the core region CA and part of the step region SA of the stacked layer 12, the word line portion 16 is formed in a part of the step region SA of the stacked layer 12, and the self-aligned contact structure 15 is formed in a part of the step region SA. The channel structure portion 18 includes a plurality of alternately stacked dielectric layers 181 and a plurality of gate layers 182, and the word line portion 16 includes a plurality of alternately stacked dielectric layers 161 and a plurality of gate sacrificial layers 162. The self-aligned contact structure 15 includes an electrically contacted word line lead-out 151 and a word line connector 152. The word line lead-out 151 extends in a direction perpendicular to the substrate 11 and is configured to be electrically connected to peripheral circuitry. The word line connector 152 extends in a direction parallel to the substrate 11 and is configured to correspond to the contact portion 1821 of the gate layer 182 in the channel structure portion 18 (see...). Figure 2 (As shown) Electrical contact.

[0086] Refer again Figure 2 As shown, since the high-K material in the self-aligned contact hole 150 and the gate gap 1222 is deposited simultaneously or in a one-step process, a complete (i.e., undamaged or missing) high-K material 183 can be formed. Furthermore, since the metal material in the self-aligned contact hole 150 and the gate gap 1222 is deposited simultaneously or in a one-step process, there is no interface or transition region between the edge portion 1522 of the word line connector 152 and the contact portion 1821 of the gate layer 182.

[0087] like Figure 14 As shown, a mask layer 175 is formed on the upper surface of the stacked layer 12. In an exemplary embodiment of this application, the specific process is as follows: photoresist is spin-coated onto the upper surface of the stacked layer 12, and after exposure and development, the cured photoresist fills the holes of the self-aligned contact structure 15, forming a mask layer 175 with the desired mask pattern on the upper surface of the stacked layer 12. In other embodiments of this application, a mask layer 175 formed of other materials with the same mask pattern may also be used.

[0088] like Figure 15As shown, the metal material 174 not covered by the mask layer 175 on the sidewalls and bottom of the gate line gap 13' and the upper surface of the stacked layer 12 is removed, and the mask layer 175 is removed. In an exemplary embodiment of this application, the specific process is as follows: the upper surface of the stacked layer 12 is etched using an etching process to remove the metal material 174 on the inner sidewalls and bottom of the gate line gap 13' and the metal material 174 not covered by the mask layer 175 on the upper surface of the stacked layer 12, so that the self-aligned contact structures 15 are electrically isolated from each other, the gate layers 182 are electrically isolated from each other, and the word line connector 152 of each self-aligned contact structure 15 is in electrical contact with the corresponding gate layer 182. Then the mask layer 175 is removed.

[0089] like Figure 16 As shown, an insulating isolation layer is filled in the gate line gap 13' and the self-aligned contact hole 150. In an exemplary embodiment of this application, the specific process is as follows: an insulating isolation material 176 is deposited in the gate line gap 13' and the hole of the self-aligned contact structure 15 using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Then, a planarization process such as chemical mechanical polishing is used to planarize the upper surface of the stacked layer 12. The insulating isolation material 176 deposited in the gate line gap 13' forms an insulating isolation layer 131, and the insulating isolation material 176 deposited in the self-aligned contact hole 150 forms an insulating isolation layer 154. In an exemplary embodiment, the insulating isolation material 176 may be a material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0090] Next, a filler material is deposited on the upper surface of the stacked layer 12 using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Finally, a planarization process such as chemical mechanical polishing is used to planarize the upper surface of the stacked layer 12. The filler material deposited in the gate line gaps 13' forms the filler portion 132, and the filler material deposited in the self-aligned contact holes 150 forms the filler portion 155. The resulting three-dimensional memory 1 can be seen in [reference needed]. Figure 1 As shown. The materials for filling portion 132 and filling portion 155 can be polycrystalline silicon or metal materials, etc.

[0091] In another embodiment of this application, after forming the semiconductor device 1 described above, the following steps may also be included:

[0092] The semiconductor device 1 is bonded to the device layer;

[0093] After bonding, the substrate 11 is removed;

[0094] A semiconductor layer for connecting channel structure 14 is formed on the back side of semiconductor device 1 (i.e., the side where the original substrate 11 is located);

[0095] An insulating layer is formed on the semiconductor layer, and a first through-hole is formed in the semiconductor layer and the insulating layer;

[0096] An insulating medium is formed on the sidewall of the first through hole;

[0097] A second via is formed on the back of semiconductor device 1, an insulating dielectric is formed on the sidewall of the second via, and a pad lead-out point is formed in the second via for signal transmission with external circuitry.

[0098] In the above embodiments of this application, after filling the self-aligned contact hole with sacrificial material, the sacrificial material in the self-aligned contact hole and the gate line gap is removed, and a portion of the gate sacrificial layer between the bottom of the self-aligned contact hole and the gate line gap is further removed, thereby enabling communication between the gate gap defined by adjacent dielectric layers and the corresponding self-aligned contact hole. Furthermore, high-K material can be deposited simultaneously (or in one step) in the gate line gap, gate gap, and self-aligned contact hole, followed by the deposition of a metal material (e.g., tungsten). Therefore, this application employs only one complete high-K material deposition process and metal material filling process, saving on process time and cost. More importantly, it avoids damaging or removing the high-K material on the sidewall of the contact portion 1821 of the gate layer 182 during the removal of the gate sacrificial layer at the bottom of the self-aligned contact hole, ensuring the integrity of the high-K material and improving electrical safety and device structure stability.

[0099] The fabrication method of this application reduces process steps and costs by depositing the same sacrificial material in the self-aligned contact hole 150 and the gate gap 13', and simultaneously removing the sacrificial material in the self-aligned contact hole 150 and the gate gap 13'.

[0100] Furthermore, after the metal material is filled in one step, the mask layer 175 with the desired mask pattern can be obtained using only one mask, so as to remove the metal material 174 that is not covered by the mask pattern on the inner sidewall and bottom of the gate gap 13' and the upper surface of the stacked layer 12. This saves process materials and steps.

[0101] In the above embodiments of this application, before filling the self-aligned contact hole 150 with the second sacrificial material, a portion of the gate sacrificial layer in contact with the bottom of the self-aligned contact hole 150 is removed to form an inverted T-shaped self-aligned contact hole 150. The advantage of this step is that in the subsequent process of removing a portion of the gate sacrificial layer 122 of the stepped region SA of the stacked layer 12 to connect the bottom of the self-aligned contact hole 150 with the corresponding gate gap 1222, only the gate sacrificial layer 122 between the gate line gap of the stepped region SA and the bottom of the self-aligned contact hole 150 near the gate line gap needs to be removed, avoiding excessive removal of the gate sacrificial layer 122 of the stepped region SA which could cause instability in the device structure.

[0102] In another embodiment of this application, after a protective layer 172 is formed on the surface of the stacked layer 12 (see [link to application]), Figure 8 As shown), a mask layer is formed on the upper surface of the protective layer 172. The protective layer 172 located on the upper surface of the step region SA of the stacked layer 12 is removed through this mask layer, exposing the gate line slots 13' and self-aligned contact holes 150 in the step region SA. The first sacrificial material 131' in the gate line slots 13' and the second sacrificial material 150' in the self-aligned contact holes 150 in the step region SA of the stacked layer 12 are removed (see...). Figure 11 As shown), a portion of the gate sacrificial layer 122 located in the step region SA of the stacked layer 12 is removed so that the bottom of the self-aligned contact hole 150 is connected to the corresponding gate gap 1222 (see...). Figure 12 (as shown); remove the protective layer 172 on the surface of the stacked layer 12, remove the first sacrificial material 131' in the gate line gap 13' of the core region CA of the stacked layer 12, and remove the gate sacrificial layer 122 in the core region CA of the stacked layer 12 (see...). Figure 9 (As shown).

[0103] Another aspect of this application provides a three-dimensional memory system, including: a controller; and a three-dimensional memory 1 as described above, the controller being coupled to the three-dimensional memory 1 and used to control the three-dimensional memory 1 to store data.

[0104] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the described technical concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions in this application.

Claims

1. A semiconductor device, characterized in that, include: A stacked structure, including a channel structure portion and a word line portion, wherein the channel structure portion includes alternating layers of dielectric layers and gate layers; as well as Multiple self-aligned contact structures extend to different predetermined depths in the word line portion and respectively make electrical contact with the corresponding gate layer in the channel structure portion; A complete high dielectric constant material is provided between the dielectric layer of the electrical contact area, the channel structure, and the self-aligned contact structure.

2. The semiconductor device according to claim 1, characterized in that, Each of the self-aligned contact structures includes: A letter line leader extends in the stacking direction of the stacked structure, with one end located on the upper surface of the letter line portion; and The word line connector extends in a direction perpendicular to the stacking direction and includes a middle portion that is electrically in contact with the other end of the word line lead and an edge portion that is electrically in contact with the corresponding gate layer. Wherein, the edge portion of the word line connector has no interface or metal transition region between the electrical contact area and the corresponding contact portion of the gate layer.

3. The semiconductor device according to claim 2, characterized in that, The outer walls of the word line connector and the word line lead are provided with a high dielectric constant material.

4. The semiconductor device according to claim 2, characterized in that, The gate layer and the corresponding word line connector have the same thickness; and The thickness of the high-dielectric-constant material disposed between the word line connector and the dielectric layer of the channel structure is equal to the thickness of the high-dielectric-constant material disposed between the gate layer and the dielectric layer of the channel structure.

5. The semiconductor device according to claim 2, characterized in that, The word line portion includes alternating layers of dielectric layers and gate sacrificial layers. Each dielectric layer of the word line portion is in contact with a corresponding dielectric layer of the channel structure portion and is located in the same layer. Each gate sacrificial layer is in contact with a corresponding word line connector and is located in the same layer.

6. The semiconductor device according to any one of claims 2 to 5, characterized in that, The semiconductor device includes: The grid line slot structure extends through the stacked structure and includes a first insulating isolation layer and a first filling portion arranged sequentially from the outside to the inside.

7. The semiconductor device according to claim 6, characterized in that, The self-aligned contact structure also includes: A second insulating layer is disposed on the inner wall of the word line lead-out member; and The second filling portion is filled on the inner side of the inner wall of the second insulating layer; The first insulating layer and the second insulating layer are made of the same material, and the first filling portion and the second filling portion are made of the same material.

8. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A stacked layer is formed, the stacked layer including a core region and a step region; A gate line slot is formed that penetrates the stacked layers, and the gate line slot is located in the core region and the step region; Multiple self-aligned contact holes are formed in the step region of the stacked layer, and the multiple self-aligned contact holes extend to different predetermined depths to the corresponding gate sacrificial layer in the step region of the stacked layer. The gate sacrificial layer is removed through the gate line gap, so that the gate gap formed in the core region is connected to the corresponding self-aligned contact hole; as well as Conductive connections are deposited in the gate line gaps, the gate gaps, and the plurality of self-aligned contact holes; The deposition of conductive connections in the gate line slots, the gate gaps, and the self-aligned contact holes includes: depositing a complete high-dielectric-constant material on the inner sidewalls and bottom of the gate line slots, the inner sidewalls of the gate gaps, and the inner sidewalls of the plurality of self-aligned contact holes.

9. The preparation method according to claim 8, characterized in that, Removing the gate sacrificial layer via the gate line gap includes: The gate sacrificial layer of the stacked layer located in the core region of the stacked layer is removed to form the gate gap via the gate line gap located in the core region of the stacked layer; and A portion of the gate sacrificial layer of the stacked layer located in the stepped region is removed via the gate line gap located in the stepped region, such that each of the self-aligned contact holes is connected to the corresponding gate gap.

10. The preparation method according to claim 9, characterized in that, After forming the gate wire gaps through the stacked layers, the method further includes: A first sacrificial material is filled into the gaps in the grid lines; After forming the plurality of self-aligned contact holes in the stepped region of the stacked layer, the method further includes: A second sacrificial material is filled into the plurality of self-aligned contact holes.

11. The preparation method according to claim 10, characterized in that, Before removing the gate sacrificial layer of the stacked layer located in the core region, the process also includes removing the first sacrificial material in the gate line gaps of the core region of the stacked layer.

12. The preparation method according to claim 10, characterized in that, After forming the gate gap, the method further includes: removing the first sacrificial material from the gate line gap in the step region of the stacked layer and the second sacrificial material from the plurality of self-aligned contact holes.

13. The preparation method according to claim 12, characterized in that, Before removing the first sacrificial material from the gate wire gaps in the core region of the stacked layer, the method further includes: forming a protective layer on the upper surface of the stacked layer, and removing the protective layer located on the upper surface of the stacked layer in the core region; Before removing the first sacrificial material in the grid line gaps of the stepped region of the stacked layer and the second sacrificial material in the plurality of self-aligned contact holes, the method further includes: removing the protective layer on the upper surface of the stacked layer located in the stepped region.

14. The preparation method according to claim 8, characterized in that, After forming the plurality of self-aligned contact holes in the stepped region of the stacked layer, the method further includes: An insulating material is formed on the sidewalls of the plurality of self-aligned contact holes; and This allows the insulating material to penetrate into the corresponding gate sacrificial layer.

15. The preparation method according to claim 14, characterized in that, After forming an insulating material on the sidewalls of the plurality of self-aligned contact holes, the method further includes: removing a portion of the gate sacrificial layer that is connected to the bottom of each of the self-aligned contact holes in the stepped region of the stacked layer.

16. The preparation method according to any one of claims 9 to 15, characterized in that, After depositing a high dielectric constant material, depositing conductive connections in the gate line gaps, the gate gaps, and the self-aligned contact holes further includes the following steps: A metal adhesion layer is deposited on the inner sidewall of the high dielectric constant material; and Deposit metallic material on the inner sidewall of the metal adhesion layer; The metal material filling the gate gap forms a gate layer.

17. The preparation method according to claim 16, characterized in that, After depositing the metal material on the inner sidewall of the metal adhesion layer, the process further includes: Remove the metal material from the inner wall and bottom of the grid line slot.

18. The preparation method according to claim 17, characterized in that, Removing the metal material from the inner wall and bottom of the grid line slots includes the following steps: Forming a mask layer covering the plurality of self-aligned contact holes; and Remove the metal material from the inner sidewalls and bottom of the grid line slots, as well as the material on the upper surface of the stacked layer that is not covered by the mask layer.

19. The preparation method according to claim 18, characterized in that, After removing the metal material from the inner wall and bottom of the grid line slots, the process further includes: Remove the mask layer; A first insulating layer and a second insulating layer are formed on the inner side of the inner wall of the grid wire gap and the inner side of the inner wall of the plurality of self-aligned contact holes, respectively; and A first filling portion and a second filling portion are formed in the grid line gaps and the plurality of self-aligned contact holes, respectively.

20. A three-dimensional memory system, characterized in that, include: Controller; as well as The semiconductor device according to any one of claims 1 to 7, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

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