Analog-to-Digital Conversion Method, Circuit and Electronic Product

Abstract

The present invention provides an analog-to-digital conversion method, circuit and electronic product, including: 1) sampling and holding an analog input signal to obtain a first voltage; 2) integrating the first voltage to obtain a second voltage. If the second voltage is less than a reference voltage, continue to cumulatively integrate the first voltage and update the second voltage until the second voltage is greater than or equal to the reference voltage, and then execute the next step; 3) if the second voltage is greater than the reference voltage, return to step 1), replace the analog input signal with the difference between the second voltage and the reference voltage and update the first voltage, and continuously cycle until the second voltage is equal to the reference voltage, and then execute the next step; if the second voltage is equal to the reference voltage, then execute the next step; 4) obtain a digital output signal based on the number of integration times in each cycle period. The present invention has low transient power consumption, which is beneficial to reducing the overall power consumption of the circuit; and is beneficial to the realization of a lower-cost analog circuit.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and particularly to an analog-to-digital conversion method, circuit, and electronic product. Background Art

[0002] An analog-to-digital converter converts an analog signal that is continuous in time and amplitude in the real world into a signal that is discrete in time and amplitude, so as to facilitate data processing and storage. With the development of world informatization, this functional module has become an essential part of the vast majority of electronic systems.

[0003] Most traditional analog-to-digital converters obtain the output of the final digital signal based on sampling and holding plus the comparison of the analog signal and the reference signal and binary search. This type of method is simple in conversion time and circuit structure and has been widely adopted.

[0004] However, in the context of the development of the deep sub-micron process of integrated circuits, the cost of digital circuits is rapidly decreasing at the same scale, and at the same time, their operating speed is increasing significantly. For analog circuits, although their speed and power consumption have been continuously optimized, their cost is still expensive.

[0005] An analog-to-digital conversion method disclosed in the prior art is to use a binary method to search for the voltage position of the input signal within the entire input range, so as to obtain the final digital signal. Another analog-to-digital conversion method disclosed is to use redundant comparators and a suitable clock design to improve the anti-offset performance of the comparator for operational analog-to-digital converters. However, these analog-to-digital conversion methods generally have problems such as high power consumption and high cost.

[0006] Therefore, designing an analog-to-digital conversion circuit that is more suitable for the deep sub-micron process and making full use of the powerful digital processing capabilities under this process to reduce the cost of its analog functional module has become an urgent design in this industry. Summary of the Invention

[0007] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide an analog-to-digital conversion method, circuit, and electronic product, which are used to solve the problems of complex circuit structure, high power consumption, high cost, etc. in the prior art for analog-to-digital conversion circuits.

[0008] To achieve the above purpose and other related purposes, the present invention provides an analog-to-digital conversion method, which at least includes:

[0009] 1) Sampling and holding the analog input signal to obtain a first voltage;

[0010] 2) Integrate the first voltage to obtain a second voltage. If the second voltage is less than the reference voltage, continue to cumulatively integrate the first voltage and update the second voltage until the second voltage is greater than or equal to the reference voltage, and then execute the next step;

[0011] 3) If the second voltage is greater than the reference voltage, return to step 1) to replace the analog input signal with the difference between the second voltage and the reference voltage and update the first voltage, and continuously loop until the second voltage is equal to the reference voltage, then execute the next step, where the number of loops at the end of the loop is K1, and K1 is a positive integer greater than or equal to 2; if the second voltage is equal to the reference voltage, then execute the next step;

[0012] 4) Obtain a digital output signal based on the number of integration times within each cycle period.

[0013] Optionally, the second voltage satisfies the following relationship:

[0014] Vc = Vs * ni;

[0015] where Vc is the second voltage, Vs is the first voltage, and ni is the current number of integrations within the cycle period.

[0016] Optionally, in step 3), when the second voltage is greater than the reference voltage, set the number of loops to a positive integer less than K1. At the end of the loop, the second voltage is still greater than the reference voltage.

[0017] More optionally, in step 4), the digital output signal satisfies:

[0018]

[0019]

[0020]

[0021] where Dout is the digital output signal; Vin is the analog input signal; V REF is the reference voltage; K is the number of loops; Ns1, Ns2... N SK are the total number of integrations in each cycle period in sequence.

[0022] To achieve the above object and other related objects, the present invention further provides an analog-to-digital conversion circuit for implementing the above analog-to-digital conversion method. The analog-to-digital conversion circuit at least includes:

[0023] A sample-and-hold module, an integration and comparison module, and a control and processing module;

[0024] The sampling and holding module receives an analog input signal and is connected to the output end of the integration and comparison module to sample and hold the analog input signal or the output signal of the integration and comparison module;

[0025] The integration and comparison module is connected to the output end of the sampling and holding module, integrates the first voltage output by the sampling and holding module to obtain a second voltage, and compares the second voltage with a reference voltage;

[0026] The control and processing module is connected to the output end of the integration and comparison module, controls the sampling and holding module and the integration and comparison module based on the comparison result between the second voltage and the reference voltage, and calculates a digital output signal based on the number of integration times of the integration and comparison module in each integration cycle.

[0027] Optionally, the sampling and holding module includes: a first, a second, a third, a fourth, and a fifth switch, a first, a second, and a third capacitor, and a first operational amplifier;

[0028] One end of the first switch receives the analog input signal, and the other end is connected to the first end of the first capacitor; the first end of the first capacitor is grounded via the second switch;

[0029] One end of the third switch is connected to the output end of the integration and comparison module to obtain the difference between the second voltage and the reference voltage, and the other end is connected to the first end of the second capacitor; the first end of the second capacitor is grounded via the fourth switch;

[0030] The first input end of the first operational amplifier is connected to the second ends of the first capacitor and the second capacitor, and the second input end of the first operational amplifier is grounded;

[0031] The fifth switch and the third capacitor are respectively connected in parallel between the output end and the first input end of the first operational amplifier.

[0032] More optionally, the integration and comparison module includes an integration and multiplication unit and a comparison unit;

[0033] The integration and multiplication unit is connected to the output end of the sampling and holding module, receives the reference voltage, integrates the first voltage to obtain a second voltage, and obtains the difference between the second voltage and the reference voltage;

[0034] The comparison unit is connected to the output end of the integration and multiplication unit, receives the reference voltage, and compares the second voltage with the reference voltage.

[0035] More optionally, the integration and multiplication unit includes:

[0036] The sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, and fourteenth switches, the fourth, fifth, and sixth capacitors, and the second operational amplifier;

[0037] One end of the sixth switch is connected to the output end of the sample and hold module, and the other end is connected to the first end of the fourth capacitor; the first end of the fourth capacitor is grounded via the seventh switch, and the second end of the fourth capacitor is grounded via the eighth switch;

[0038] One end of the ninth switch receives the reference voltage, and the other end is connected to the first end of the fifth capacitor; the first end of the fifth capacitor is grounded via the tenth switch, and the second end of the fifth capacitor is grounded via the eleventh switch;

[0039] The first input end of the second operational amplifier is connected to the second end of the fourth capacitor via the twelfth switch and is connected to the second end of the fifth capacitor via the thirteenth switch, and the second input end of the second operational amplifier is grounded;

[0040] The fourteenth switch and the sixth capacitor are respectively connected in parallel between the output end and the first input end of the second operational amplifier.

[0041] To achieve the above and other related purposes, the present invention further provides an electronic product, which at least includes: the above analog-to-digital conversion circuit.

[0042] As described above, the analog-to-digital conversion method, circuit, and electronic product of the present invention have the following beneficial effects:

[0043] 1. The analog-to-digital conversion method, circuit, and electronic product of the present invention adopt an integral search method, which is different from the binary search method. In circuit design, because it is a process of voltage or current signal accumulation, its transient power consumption is smaller, and the requirements for active circuits (such as the transient response performance of operational amplifiers) are reduced, which is beneficial to reducing the overall power consumption of the circuit.

[0044] 2. Since the analog-to-digital conversion method, circuit, and electronic product of the present invention adopt an integral method, it is not necessary to implement large-scale and precisely matched electronic devices (such as capacitors) on the chip, and the requirements for circuit matching are greatly reduced, which is beneficial to the realization of lower-cost analog circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It shows a schematic flow chart of the analog-to-digital conversion method of the present invention.

[0046] Figure 2 It shows a schematic structural diagram of the analog-to-digital conversion circuit of the present invention.

[0047] Figure 3 It shows a schematic diagram of the switch states of the analog-to-digital conversion circuit of the present invention during the sampling and holding stage.

[0048] Figure 4 It shows a schematic diagram of the switch states of the analog-to-digital conversion circuit of the present invention during the stage of integrating the first voltage.

[0049] Figure 5 It shows a schematic diagram of the switch states of the analog-to-digital conversion circuit of the present invention during the stage of updating the first voltage Vs.

[0050] Figure 6 It shows a schematic diagram of the switch states of the analog-to-digital conversion circuit of the present invention during the stage of integrating the updated first voltage.

[0051] Description of component labels

[0052] 1 Analog-to-digital conversion circuit

[0053] 11 Sampling and holding module

[0054] 12 Integration and comparison module

[0055] 121 Integration and multiplication unit

[0056] 122 Comparison unit

[0057] 13 Control and processing module Specific implementation manners

[0058] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content described in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0059] Please refer to Figures 1-6 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components during actual implementation. The types, quantities, and proportions of the components during actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0060] Embodiment 1

[0061] As Figure 1 shown, the present invention provides an analog-to-digital conversion method, and the analog-to-digital conversion method includes:

[0062] 1) Sample and hold the analog input signal Vin to obtain the first voltage Vs.

[0063] Specifically, provide an analog input signal Vin, which can be any signal that needs to be converted from analog to digital, and the signal source is not limited. Sample and hold the analog input signal Vin to obtain the amplitude at the sampling moment, denoted as the first voltage Vs.

[0064] 2) Integrate the first voltage Vs to obtain the second voltage Vc. If the second voltage Vc is less than the reference voltage V REF , then continue to cumulatively integrate the first voltage Vs and update the second voltage Vc until the second voltage Vc is greater than or equal to the reference voltage V REF , and then execute the next step.

[0065] Specifically, integrate the first voltage Vs at least once. As the number of integration times increases, the second voltage Vc continuously increases until the second voltage Vc is greater than or equal to the reference voltage V REF , and then stop the cumulative integration. Among them, the second voltage Vc satisfies the following relationship: Vc = Vs * ni, where ni is the current number of integration times within the cycle period; that is, when integrating for the first time, the second voltage Vc = Vs, when integrating for the second time, the second voltage Vc = 2Vs... and so on. When integrating for the nth time, the second voltage Vc = n * Vs, which will not be elaborated here one by one.

[0066] Specifically, compare the second voltage Vc with the reference voltage V REF to determine the magnitude relationship between the second voltage Vc and the reference voltage V REF .

[0067] 3) If the second voltage Vc is greater than the reference voltage V REF , then return to step 1) and replace the analog input signal Vin with the difference Vf between the second voltage Vc and the reference voltage V REF and update the first voltage Vs, and continuously loop until the second voltage Vc is equal to the reference voltage V REF , and then execute the next step. Among them, when the loop ends, the number of loop times is K1, and K1 is a positive integer greater than or equal to 2. If the second voltage Vc is equal to the reference voltage V REF , then execute the next step.

[0068] Specifically, after the integration in step 2), if the second voltage Vc is equal to the reference voltage V REF , then the number of loop times is recorded as 1 time.

[0069] Specifically, after the integration in step 2), if the second voltage Vc is greater than the reference voltage V REF , the difference Vf between the second voltage Vc and the reference voltage V REF is obtained, and step 1) is returned to sample and hold the difference Vf between the two to update the value of the first voltage Vs; then step 2) is executed again to integrate the sampled signal of the difference Vf between the second voltage Vc and the reference voltage V REF to update the value of the second voltage Vc. If the updated second voltage Vc is greater than the reference voltage V REF , the loop continues until the second voltage Vc is equal to the reference voltage V REF . The loop ends. At this time, the number of loops is denoted as K1, and K1 is a positive integer greater than or equal to 2.

[0070] More specifically, after sampling and holding, the first voltage V S1 = V i , where Vi is the sampled value of the analog input signal Vin; when the number of loops is 1, the updated first voltage V S2 = N S1 ·V S1 - V REF ; when the number of loops is 2, the updated first voltage V S3 = N S2 ·V S2 - V REF ; when the number of loops is 3, the updated first voltage V S4 = N S3 ·V S3 - V REF ... And so on, until the number of loops is K1, the updated first voltage V SK1+1 = V REF .

[0071] It should be noted that the number of loops can be set according to the accuracy requirements. Theoretically, the larger the number of loops K, the higher the accuracy of the finally obtained digital signal. As another implementation manner of the present invention, if the second voltage Vc is greater than the reference voltage V REF , the first voltage Vs is continuously updated to execute the loop, and the loop ends when the second voltage Vc is still greater than the reference voltage V REF (before reaching the condition that the second voltage Vc is equal to the reference voltage V REF ). At this time, the number of loops is a positive integer less than K1.

[0072] 4) Obtain the digital output signal Dout based on the number of integration times in each cycle.

[0073] Specifically, the number of integration times within each cycle is obtained, and a digital output signal Dout is generated accordingly. As an example, the digital output signal Dout satisfies:

[0074]

[0075]

[0076]

[0077] where Dout is the digital output signal; Vin is the analog input signal; V REF is the reference voltage; K is the number of cycles; Ns1, Ns2... N SK are the total integration times of each cycle in sequence.

[0078] It should be noted that when K = 3, when K = 4, Those skilled in the art can obtain the digital output signal when K is greater than or equal to 5 in sequence based on the above rules, which will not be elaborated here one by one.

[0079] The analog-to-digital conversion method of the present invention adopts an integration (or accumulation) approximation search method, compares and subtracts the input signal and the reference voltage, then searches and compares; and processes the search result through a digital circuit to obtain the final digital output, greatly reducing the transient power consumption.

[0080] Embodiment 2

[0081] As Figure 2 shown, this embodiment provides an analog-to-digital conversion circuit 1, and the analog-to-digital conversion circuit 1 includes:

[0082] A sample and hold module 11, an integration and comparison module 12, and a control and processing module 13.

[0083] As Figure 2 shown, the sample and hold module 11 receives the analog input signal Vin and is connected to the output end of the integration and comparison module 12 to sample and hold the analog input signal Vin or the output signal of the integration and comparison module 12 to obtain a first voltage Vs.

[0084] Specifically, in this embodiment, the sampling and holding module 11 includes: a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a first capacitor C1, a second capacitor C2, a third capacitor C3 and a first operational amplifier OP1. One end of the first switch S1 receives the analog input signal Vin, and the other end is connected to the first end of the first capacitor C1. One end of the second switch S2 is connected to the first end of the first capacitor C1, and the other end is grounded. One end of the third switch S3 is connected to the output end of the integral comparison module 12 to obtain the second voltage Vc and the reference voltage V REF The difference Vf is obtained by connecting the first end of the first operational amplifier OP1 to the output terminal of the first operational amplifier OP1, and the other end is connected to the first end of the second capacitor C2. One end of the fourth switch S4 is connected to the first end of the second capacitor C2, and the other end is grounded. The first input end of the first operational amplifier OP1 is connected to the second ends of the first capacitor C1 and the second capacitor C2, and the second input end of the first operational amplifier OP1 is grounded. The fifth switch S5 and the third capacitor C3 are respectively connected in parallel between the output end and the first input end of the first operational amplifier OP1. As an example, the inverting input end of the first operational amplifier OP1 is used as the first input end, and the non-inverting input end is used as the second input end. In actual use, the corresponding relationship between the input signal and the polarity of the input port can be adjusted by adding an inverter as needed, which will not be described in detail here.

[0085] It should be noted that any circuit structure that can perform time-sharing sampling and holding on the analog input signal Vin and the output signal of the integral comparison module 12 is applicable to the present invention, and is not limited to this embodiment.

[0086] like Figure 2 As shown, the integral comparison module 12 is connected to the output end of the sampling and holding module 11, integrates the first voltage Vs output by the sampling and holding module 11 to obtain a second voltage Vc, and compares the second voltage Vc with the reference voltage V REF Make a comparison.

[0087] Specifically, in this embodiment, the integral comparison module 12 includes an integral multiplication unit 121 and a comparison unit 122. The integral multiplication unit 121 is connected to the output end of the sampling and holding module 11 and receives the reference voltage V REF , integrate the first voltage Vs to obtain a second voltage Vc, and calculate the difference between the second voltage Vc and the reference voltage V REF The comparison unit 122 is connected to the output end of the integral multiplication unit 121 and receives the reference voltage V REF , the second voltage Vc and the reference voltage V REF By comparison, the second voltage Vc and the reference voltage VREF The size relationship.

[0088] More specifically, as an example, the integral multiplication unit 121 includes: a sixth switch S6, a seventh switch S7, an eighth switch S8, a ninth switch S9, a tenth switch S10, an eleventh switch S11, a twelfth switch S12, a thirteenth switch S13, a fourteenth switch S14, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, and a second operational amplifier OP2. One end of the sixth switch S6 is connected to the output end of the sample and hold module 11, and the other end is connected to the first end of the fourth capacitor C4. One end of the seventh switch S7 is connected to the first end of the fourth capacitor C4, and the other end is grounded. One end of the eighth switch S8 is connected to the second end of the fourth capacitor C4, and the other end is grounded. One end of the ninth switch S9 receives the reference voltage V REF , and the other end is connected to the first end of the fifth capacitor C5. One end of the tenth switch S10 is connected to the first end of the fifth capacitor C5, and the other end is grounded. One end of the eleventh switch S11 is connected to the second end of the fifth capacitor C5, and the other end is grounded. The first input terminal of the second operational amplifier OP2 is connected to the second end of the fourth capacitor C4 via the twelfth switch S12 and to the second end of the fifth capacitor C5 via the thirteenth switch S13. The second input terminal of the second operational amplifier OP2 is grounded. The fourteenth switch S14 and the sixth capacitor C6 are respectively connected in parallel between the output terminal and the first input terminal of the second operational amplifier OP2. As an example, the inverting input terminal of the second operational amplifier OP2 is used as the first input terminal, and the non-inverting input terminal is used as the second input terminal. In actual use, the corresponding relationship between the input signal and the input port polarity can be adjusted by adding an inverter as needed, which will not be elaborated here one by one.

[0089] It should be noted that the structure of the integral multiplication unit 121 is not limited to the switched-capacitor structure of this embodiment, and a transconductance-capacitor structure can also be used. Any circuit structure that can achieve integration is applicable, which will not be elaborated here one by one.

[0090] Such as Figure 2 shown, the control processing module 13 is connected to the output end of the integral comparison module 12, controls the sample and hold module 11 and the integral comparison module 12 based on the comparison result between the second voltage Vc and the reference voltage V REF , and calculates the digital output signal Dout based on the number of integration times of the integral comparison module 12 in each integration cycle.

[0091] Specifically, in this embodiment, the control processing module 13 provides switch control signals for the sample and hold module 11 and the integral comparison module 12.

[0092] The analog-to-digital conversion circuit 1 is used to perform the analog-to-digital conversion method of the first embodiment, and the specific working principle is as follows:

[0093] As Figure 3 shown, in the sampling and holding stage, in the sampling and holding module 11, the first switch S1 and the fifth switch S5 are closed, and the second switch S2, the third switch S3, and the fourth switch S4 are opened. Based on the sampling and holding module 11, the sampling and holding of the analog input signal Vin is completed to obtain the first voltage Vs. In the integration and multiplication unit 121, the sixth switch S6, the eighth switch S8, and the fourteenth switch S14 are closed, and the seventh switch S7, the ninth switch S9, the tenth switch S10, the eleventh switch S11, the twelfth switch S12, and the thirteenth switch S13 are opened.

[0094] As Figure 4 shown, in the stage of integrating the first voltage Vs, in the sampling and holding module 11, the second switch S2 is closed, and the first switch S1, the third switch S3, the fourth switch S4, and the fifth switch S5 are opened. In the integration and multiplication unit 121, the seventh switch S7, the ninth switch S9, the eleventh switch S11, and the twelfth switch S12 are closed, and the sixth switch S6, the eighth switch S8, the tenth switch S10, the thirteenth switch S13, and the fourteenth switch S14 are opened. Based on the integration and multiplication unit 121, the first integration of the first voltage Vs is completed to obtain the second voltage Vc. Then, based on the comparison unit 122, the second voltage Vc is compared with the reference voltage V REF for comparison. If the second voltage Vc is less than the reference voltage V REFThen, the control processing module 13 controls the integration multiplication unit 121 to perform a second integration. Before the second integration is executed, each switch in the integration multiplication unit 121 resumes its previous state, that is, the sixth switch S6, the eighth switch S8, and the fourteenth switch S14 are closed, and the seventh switch S7, the ninth switch S9, the tenth switch S10, the eleventh switch S11, the twelfth switch S12, and the thirteenth switch S13 are open; subsequently, in the integration multiplication unit 121, the seventh switch S7, the ninth switch S9, the eleventh switch S11, and the twelfth switch S12 are closed, and the sixth switch S6, the eighth switch S8, the tenth switch S10, the thirteenth switch S13, and the fourteenth switch S14 are open, completing the second integration of the first voltage Vs. During this process, the states of the switches in the sample and hold module 11 remain unchanged, and the switches in the integration multiplication unit 121 sequentially resume, integrate, resume, integrate... states, so as to achieve multiple integrations until the second voltage Vc is greater than or equal to the reference voltage V REF .

[0095] As Figure 5 shown, in the stage of updating the first voltage Vs, in the integration multiplication unit 121, the seventh switch S7, the tenth switch S10, the twelfth switch S12, and the thirteenth switch S13 are closed, and the sixth switch S6, the eighth switch S8, the ninth switch S9, the eleventh switch S11, and the fourteenth switch S14 are open, and the difference Vf between the second voltage Vc and the reference voltage V REF is obtained based on the integration multiplication unit 121. In the sample and hold module 11, the second switch S2, the third switch S3, and the fifth switch S5 are closed, and the first switch S1 and the fourth switch S4 are open, and the difference Vf between the second voltage Vc and the reference voltage V REF is sampled and held based on the sample and hold module 11 to update the first voltage Vs.

[0096] As Figure 6As shown, in the stage of integrating the updated first voltage Vs, in the sample and hold module 11, the fourth switch S4 is closed, and the first switch S1, the second switch S2, the third switch S3, and the fifth switch S5 are open. In the integration and multiplication unit 121, the seventh switch S7 and the twelfth switch S12 are closed, and the sixth switch S6, the eighth switch S8, the ninth switch S9, the tenth switch S10, the eleventh switch S11, the thirteenth switch S13, and the fourteenth switch S14 are open. Based on the integration and multiplication unit 121, the first integration of the updated first voltage Vs is completed to obtain the updated second voltage Vc (as another example, the states of the switches in the integration and multiplication unit 121 can be replaced with: the seventh switch S7, the ninth switch S9, the eleventh switch S11, and the twelfth switch S12 are closed, and the sixth switch S6, the eighth switch S8, the tenth switch S10, the thirteenth switch S13, and the fourteenth switch S14 are open. In this way, the integration of the updated first voltage Vs is completed. The states of the switches depend on the convenience of implementation, as long as the integration can be achieved, and it is not limited to the examples listed in the present invention). Then, based on the comparison unit 122, the updated second voltage Vc is compared with the reference voltage V REF for comparison. If the updated second voltage Vc is less than the reference voltage V REF then the control and processing module 13 controls the integration and multiplication unit 121 to perform a second integration. The principle of multiple integrations is the same as the principle of integrating the first voltage Vs, and will not be elaborated here one by one.

[0097] It should be noted that for the determination of the number of cycles, refer to Embodiment 1. This embodiment only takes the number of cycles as two as an example, and will not be elaborated here one by one.

[0098] The analog-to-digital conversion circuit of the present invention uses the accumulation of voltage or current signals to achieve integral search, with less transient power consumption in circuit design, which is beneficial to reducing the overall power consumption of the circuit; at the same time, there is no need to implement large-scale and precisely matched electronic devices on the chip, greatly reducing the requirements for circuit matching, which is beneficial to the realization of lower-cost analog circuits.

[0099] Embodiment 3

[0100] This embodiment provides an electronic product, which includes: the analog-to-digital conversion circuit 1 of Embodiment 2, used to achieve low power consumption and low cost.

[0101] In summary, the present invention provides an analog-to-digital conversion method, circuit and electronic product, including: 1) sampling and holding an analog input signal to obtain a first voltage; 2) integrating the first voltage to obtain a second voltage. If the second voltage is less than a reference voltage, continue to cumulatively integrate the first voltage and update the second voltage until the second voltage is greater than or equal to the reference voltage, and then execute the next step; 3) if the second voltage is greater than the reference voltage, return to step 1), replace the analog input signal with the difference between the second voltage and the reference voltage, and update the first voltage, and continuously loop until the second voltage is equal to the reference voltage, and then execute the next step, where the number of loops at the end of the loop is K1, and K1 is a positive integer greater than or equal to 2; if the second voltage is equal to the reference voltage, then execute the next step; 4) obtain a digital output signal based on the number of integration times in each cycle period. The analog-to-digital conversion method, circuit and electronic product of the present invention adopt an integration search method, which is different from the binary search method. In circuit design, because it is a process of accumulating voltage or current signals, its transient power consumption is smaller, and the requirements for active circuits (such as the transient response performance of operational amplifiers) are reduced, which is beneficial to reducing the overall power consumption of the circuit; since the integration method is adopted, there is no need to implement a large proportion of precisely matched electronic devices (such as capacitors) on the chip, and the requirements for circuit matching are greatly reduced, which is beneficial to the realization of lower-cost analog circuits. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0102] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for analog-to-digital conversion, characterized in that, The analog-to-digital conversion method at least includes: 1) Sampling and holding the analog input signal to obtain a first voltage; 2) Integrating the first voltage to obtain a second voltage. If the second voltage is less than the reference voltage, continue to cumulatively integrate the first voltage and update the second voltage until the second voltage is greater than or equal to the reference voltage, and then execute the next step; 3) If the second voltage is greater than the reference voltage, return to step 1), replace the analog input signal with the difference between the second voltage and the reference voltage, and update the first voltage. Keep looping until the second voltage is equal to the reference voltage, and then execute the next step. Here, the number of loops at the end of the loop is K1, and K1 is a positive integer greater than or equal to 2. If the second voltage is equal to the reference voltage, then execute the next step; 4) Obtain the digital output signal based on the number of integration times within each cycle period.

2. The analog-to-digital conversion method according to claim 1, wherein: The second voltage satisfies the following relationship: Vc = Vs * ni; where, Vc is the second voltage, Vs is the first voltage, and ni is the current number of integrations within the cycle period.

3. The analog-to-digital conversion method according to claim 1, characterized in that: In step 3), when the second voltage is greater than the reference voltage, set the number of loops to a positive integer less than K1. At the end of the loop, the second voltage is still greater than the reference voltage.

4. The analog-to-digital conversion method according to any one of claims 1-3, characterized in that: In step 4), the digital output signal satisfies: Wherein, Dout is the digital output signal; Vin is the analog input signal; V REF is the reference voltage; K is the number of cycles; Ns1, Ns2... N SK are the total integration times of each cycle period in sequence.

5. An analog-to-digital conversion circuit that implements the analog-to-digital conversion method described in any one of claims 1-4, characterized in that, The analog-to-digital conversion circuit at least includes: A sampling and holding module, an integration and comparison module, and a control and processing module; The sampling and holding module receives the analog input signal and is connected to the output end of the integration and comparison module, and samples and holds the analog input signal or the output signal of the integration and comparison module; The integration and comparison module is connected to the output end of the sampling and holding module, integrates the first voltage output by the sampling and holding module to obtain a second voltage, and compares the second voltage with the reference voltage; The control and processing module is connected to the output end of the integration and comparison module, controls the sampling and holding module and the integration and comparison module based on the comparison result between the second voltage and the reference voltage, and calculates the digital output signal based on the number of integrations of the integration and comparison module within each integration cycle period.

6. The analog-to-digital conversion circuit according to claim 5, wherein: The sampling and holding module includes: a first, second, third, fourth, and fifth switch, a first, second, and third capacitor, and a first operational amplifier; One end of the first switch receives the analog input signal, and the other end is connected to the first end of the first capacitor; the first end of the first capacitor is grounded via the second switch; One end of the third switch is connected to the output end of the integration and comparison module to obtain the difference between the second voltage and the reference voltage, and the other end is connected to the first end of the second capacitor; the first end of the second capacitor is grounded via the fourth switch; The first input end of the first operational amplifier is connected to the second ends of the first capacitor and the second capacitor, and the second input end of the first operational amplifier is grounded; The fifth switch and the third capacitor are respectively connected in parallel between the output end and the first input end of the first operational amplifier.

7. The analog-to-digital conversion circuit according to claim 5 or 6, characterized in that: The integration and comparison module includes an integration and multiplication unit and a comparison unit; The integration and multiplication unit is connected to the output end of the sample and hold module, receives the reference voltage, integrates the first voltage to obtain a second voltage, and obtains the difference between the second voltage and the reference voltage; The comparison unit is connected to the output end of the integration and multiplication unit, receives the reference voltage, and compares the second voltage with the reference voltage.

8. The analog-to-digital conversion circuit according to claim 7, wherein: The integration and multiplication unit includes: a sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, and fourteenth switch, a fourth, fifth, and sixth capacitor, and a second operational amplifier; One end of the sixth switch is connected to the output end of the sample and hold module, and the other end is connected to the first end of the fourth capacitor; the first end of the fourth capacitor is grounded via the seventh switch, and the second end of the fourth capacitor is grounded via the eighth switch; One end of the ninth switch receives the reference voltage, and the other end is connected to the first end of the fifth capacitor; the first end of the fifth capacitor is grounded via the tenth switch, and the second end of the fifth capacitor is grounded via the eleventh switch; The first input terminal of the second operational amplifier is connected to the second end of the fourth capacitor via the twelfth switch and to the second end of the fifth capacitor via the thirteenth switch, and the second input terminal of the second operational amplifier is grounded; The fourteenth switch and the sixth capacitor are respectively connected in parallel between the output end and the first input terminal of the second operational amplifier.

9. An electronic product, characterized in that, The electronic product at least includes: the analog-to-digital conversion circuit according to any one of claims 5-8.

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