A current detection circuit for DNA sequencing

Abstract

The present invention discloses a current detection circuit applied to DNA sequencing, comprising a capacitive transimpedance amplifier array, a difference sampling circuit and an analog-to-digital converter for performing analog-to-digital conversion; the capacitive transimpedance amplifier array is used to perform capacitive integration on an input current and output an integrated voltage, and the capacitive transimpedance amplifier array is composed of M rows and N columns of capacitive transimpedance amplifier units; the difference sampling circuit is used to simultaneously sample multiple integrated voltages of each row of the capacitive transimpedance amplifier array, and amplify the multiple integrated voltages in sequence and then output them; the N column output ports of the capacitive transimpedance amplifier array are respectively connected to the N input ports of the difference sampling circuit, and the output signal of the difference sampling circuit is sent to the input end of the analog-to-digital converter.

Description

Technical Field

[0001] The invention belongs to the field of electronic circuit design technology, and in particular relates to a current detection circuit applied to DNA sequencing. Background Art

[0002] DNA (Deoxyribonucleic Acid) sequencing is the process of determining the identity and order of DNA bases (ACGT) in a DNA fragment. There are many different sequencing methods currently in use, such as Sequence By Synthesis (SBS), nanopore sequencing, etc.

[0003] Charge induction measurement is a type of synthetic sequencing, which is suitable for integrated circuits to complete DNA sequencing. Since the current to be measured in DNA sequencing is very weak, generally in the order of tens of fA to hundreds of fA, traditional induction measurement mainly relies on ISFET (Ion-sensitive Field-Effect Transistor) for detection. Its disadvantage is that it uses a passivation layer for sensing, is not compatible with the excitation mode, and cannot support both excitation and sequencing functions.

[0004] In addition, traditional measurement solutions often use multiple ADCs (Analog to Digital Converters) in conjunction with microelectrode arrays for data acquisition, which greatly increases the complexity and chip area of ​​the chip. Summary of the invention

[0005] Purpose of the invention: To solve the problem that the currently used sequencing methods cannot support both excitation and sequencing functions, and to solve the problems of high chip complexity and large chip area in traditional measurement methods, the present invention proposes a current detection circuit for DNA sequencing.

[0006] Technical solution: A current detection circuit for DNA sequencing, comprising a capacitive transimpedance amplifier array, a differential sampling circuit, and an analog-to-digital converter for analog-to-digital conversion;

[0007] The capacitive transimpedance amplifier array is used to perform capacitive integration on the input current and output an integrated voltage, and the capacitive transimpedance amplifier array is composed of M rows and N columns of capacitive transimpedance amplifier units;

[0008] The difference sampling circuit is used to simultaneously sample multiple integrated voltages of each row of the capacitive transimpedance amplifier array, and amplify the multiple integrated voltages in sequence and then output them;

[0009] The N columns of output ports of the capacitor transimpedance amplifier array are respectively connected to the N input ports of the difference sampling circuit, and the output signal of the difference sampling circuit is sent to the input end of the analog-to-digital converter.

[0010] Further, the structure of each column in the capacitive transimpedance amplifier array includes a PCELL and M NCELLs; the M NCELLs are arranged in M ​​rows in the array;

[0011] The PCELL includes a first PMOS tube and a second PMOS tube, wherein the gate of the first PMOS tube is connected to a voltage V cp The drain of the first PMOS tube is used as the output port of the column, the source of the first PMOS tube is connected to the drain of the second PMOS tube, and the gate of the second PMOS tube is connected to the voltage V bp , the source of the second PMOS tube is connected to the voltage VDD;

[0012] Each of the NCELLs includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a first capacitor and an electrode; the gate of the first NMOS tube is connected to the electrode, the source of the first NMOS tube is grounded, the drain of the first NMOS tube is connected to the source of the second NMOS tube; the gate of the second NMOS tube is connected to a voltage V cn , the drain of the second NMOS tube is connected to the source of the third NMOS tube; the gate of the third NMOS tube is connected to the Row Select signal, the drain of the third NMOS tube is connected to the source of the fifth NMOS tube; the gate of the fourth NMOS tube is connected to the Row Select signal, the source of the fourth NMOS tube is connected to the drain of the first PMOS tube, and the drain of the fourth NMOS tube is connected to the electrode through the first capacitor; the gate of the fifth NMOS tube is connected to the RST signal, the drain of the fifth NMOS tube is connected to the electrode, and the source of the fifth NMOS tube is connected to the drain of the third NMOS tube;

[0013] When the Row Select signal is high and the RST signal is low, the NCELL enters the integration operation; when the Row Select signal is low, the NCELL stops working; when the Row Select signal and the RST signal are both high, the NCELL is reset to the initial level.

[0014] Furthermore, for any column in the capacitor transimpedance amplifier array, at most only one NCELL operates normally.

[0015] Furthermore, the electrode is a metal electrode.

[0016] Furthermore, the difference sampling circuit includes N-channel integral voltage receiving circuits, an amplifier, a first feedback loop and a second feedback loop;

[0017] The N-way integral voltage receiving circuits correspond to the N-column output ports of the capacitor transimpedance amplifier array in sequence, and the structure of each integral voltage receiving circuit is the same, including a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a second capacitor and a third capacitor;

[0018] One end of the first switch and one end of the second switch are both connected to the integration voltage, the other end of the first switch is connected to one end of the third switch through the second capacitor, and the other end of the third switch is connected to the positive input terminal of the amplifier; the other end of the second switch is connected to one end of the fourth switch through the third capacitor, and the other end of the fourth switch is connected to the negative input terminal of the amplifier; one end of the fifth switch is connected to the other end of the first switch, the other end of the fifth switch is connected to one end of the sixth switch, the other end of the sixth switch is connected to the other end of the second switch, and the other end of the fifth switch is connected to the voltage Vcm1;

[0019] The first feedback loop and the second feedback loop have the same structure, both comprising: a seventh switch, an eighth switch, a ninth switch and a fourth capacitor; one end of the fourth capacitor is connected to one end of the ninth switch;

[0020] The other end of the fourth capacitor is connected to the voltage Vcm2 through the eighth switch, and the other end of the fourth capacitor is connected to one end of the seventh switch;

[0021] One end of the fourth capacitor in the first feedback loop is connected to the positive input end of the amplifier, the other end of the ninth switch is connected to the negative output end of the amplifier, and the other end of the seventh switch is connected to the negative output end of the amplifier;

[0022] One end of the fourth capacitor in the second feedback loop is connected to the negative input end of the amplifier, the other end of the ninth switch is connected to the positive output end of the amplifier, and the other end of the seventh switch is connected to the positive output end of the amplifier.

[0023] Further, when the ninth switch and the eighth switch in the first feedback loop and the second feedback loop are at a high level, and the seventh switch is at a low level, and when the first switch and the third switch in the N-channel integral voltage receiving circuit are high, and the second switch and the fourth switch are low, the difference sampling circuit performs sampling at time t1, and t1 is the starting time of the integral measurement;

[0024] When the ninth switch and the eighth switch in the first feedback loop and the second feedback loop are at a high level and the seventh switch is at a low level, and when the second switch and the fourth switch in the N-channel integral voltage receiving circuit are high and the first switch and the third switch are low, the difference sampling circuit performs sampling at time t2, and t2 indicates the end time of the integral measurement.

[0025] Furthermore, when the ninth switch and the eighth switch in the first feedback loop and the second feedback loop are at a low level, the seventh switch is at a high level, and when the fifth switch and the sixth switch in a certain integral voltage receiving circuit are high, and the third switch and the fourth switch are high, the voltage sampled by the integral voltage receiving circuit is amplified to the output end.

[0026] Furthermore, each integrated voltage receiving circuit sequentially amplifies the sampled voltage to the output end.

[0027] Beneficial effects: Compared with the prior art, the present invention has the following advantages:

[0028] (1) The present invention uses a capacitive transimpedance amplifier array (CTIA Array) to perform capacitance integration measurement on a weak input current, which can achieve current measurement of the order of fA, can use metal electrodes for measurement, and can support both excitation and sequencing functions;

[0029] (2) The present invention adopts a difference sampling circuit DDS Circuit (Delta Difference Sampling Circuit) to sample multiple arrays in the microelectrode array simultaneously, that is, to sample multiple channels in each row simultaneously. A single ADC completes the sampling of the entire array by row and column scanning, and sends the sampled voltage to the ADC in series for quantization, which greatly reduces the number of subsequent ADCs and reduces the system area.

[0030] (3) The differential sampling circuit DDS used in the present invention supports offsetting the OTA offset and achieves a higher signal-to-noise ratio;

[0031] (4) The detection circuit of the present invention has the advantages of simple structure, small size, suitability for standard CMOS process processing, and easy realization of large-scale microelectrode arrays. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is the top-level block diagram of the present invention;

[0033] Figure 2 The structure block diagram of a column of capacitor transimpedance amplifiers in the capacitor transimpedance amplifier array CTIA Array;

[0034] Figure 3 It is the structural block diagram of the difference sampling circuit DDS Circuit;

[0035] Figure 4 This is the working status block diagram of the difference sampling circuit DDS Circuit. DETAILED DESCRIPTION

[0036] The technical solution of the present invention is now further described in conjunction with the accompanying drawings.

[0037] like Figure 1 As shown, the current detection circuit applied to DNA sequencing of the present invention mainly includes a capacitive transimpedance amplifier array (CTIA Array for short), a delta difference sampling circuit (DDS Circuit for short) and an analog to digital converter (ADC for short).

[0038] like Figure 1 As shown, the capacitive transimpedance amplifier array of the present invention is composed of M rows and N columns of CTIA units. Figure 2 The structure block diagram of a column of capacitive transimpedance amplifiers in the capacitive transimpedance amplifier array is shown, which mainly includes a PCELL (PMOS CELL) and M NCELLs (NMOS CELLs), and the M NCELLs are arranged in M ​​rows in the electrode array.

[0039] like Figure 2 As shown, PCELL is a unit composed of PMOS, which mainly includes: a first PMOS tube P1 and a second PMOS tube P2, and the gate of the first PMOS tube P1 is connected to the voltage V cp The drain of the first PMOS tube P1 is used as the output port of the capacitor transimpedance amplifier, the source of the first PMOS tube P1 is connected to the drain of the second PMOS tube P2, and the gate of the second PMOS tube P2 is connected to the voltage V bp , the source of the second PMOS tube P2 is connected to the voltage VDD.

[0040] like Figure 2 As shown, each NCELL is a unit composed of NMOS, which mainly includes: a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M3, a fourth NMOS tube M4, a fifth NMOS tube M5, a first capacitor C1 and a metal electrode MetalElectrode;

[0041] The gate of the first NMOS tube M1 is connected to the metal electrode, the source of the first NMOS tube M1 is grounded, and the drain of the first NMOS tube M1 is connected to the source of the second NMOS tube M2;

[0042] The gate of the second NMOS transistor M2 is connected to the voltage Vcn, and the drain of the second NMOS transistor M2 is connected to the source of the third NMOS transistor M3;

[0043] The gate of the third NMOS transistor M3 is connected to the Row Select signal, and the drain of the third NMOS transistor M3 is connected to the source of the fifth NMOS transistor M5;

[0044] The gate of the fourth NMOS transistor M4 is connected to the Row Select signal, the source of the fourth NMOS transistor M4 is connected to the drain of the first PMOS transistor P1, and the drain of the fourth NMOS transistor M4 is connected to the metal electrode through the first capacitor C1;

[0045] The gate of the fifth NMOS tube M5 is connected to the RST signal, the drain of the fifth NMOS tube M5 is connected to the metal electrode MetalElectrode, and the source of the fifth NMOS tube M5 is connected to the drain of the third NMOS tube M3.

[0046] When the Row Select signal is high, the NCELL works normally, and when the Row Select signal is low, the NCELL stops working. In a column of capacitor transimpedance amplifiers, at most only one NCELL works normally at the same time, and is selected by the Row Select signal. The fifth NMOS tube M5 is connected to the RST signal. When the Row Select signal and the RST signal of NCELL are both high, the CTIA is reset to the initial level; when the Row Select signal is high and the RST signal is low, the CTIA reset ends and enters the integration working mode.

[0047] The N columns of output ports of the capacitor transimpedance amplifier array are respectively connected to the N input ports of the difference sampling circuit. The output signal of the difference sampling circuit is sent to the input port of the analog-to-digital converter.

[0048] Capacitive transimpedance amplifier array (CTIA Array) can realize the integration measurement of weak currents of multiple inputs, and can obtain a measurable output voltage by reducing the integration capacitance and increasing the integration time.

[0049]

[0050] In the formula, I in (t) represents the weak current signal of the input capacitor transimpedance amplifier CTIA, C1 represents the capacitance of the first capacitor C1, t1 represents the starting time of the integral measurement, and t2 represents the ending time of the integral measurement.

[0051] Capacitive integration measurement of weak input current can be performed using metal electrodes, while supporting both excitation and sequencing functions.

[0052] Figure 3The structural block diagram of the difference sampling circuit DDS Circuit is shown. The difference sampling circuit samples multiple channels of each row of the capacitor transimpedance amplifier array simultaneously to obtain the voltage difference of the integrated voltage at two moments, and outputs it after amplification in sequence.

[0053] like Figure 3 The difference sampling circuit DDS Circuit comprises N-channel integral voltage receiving circuits, an amplifier, a first feedback loop and a second feedback loop; the amplifier used in the present invention is a transconductance amplifier OTA.

[0054] The N-way integral voltage receiving circuits correspond to the N-column output ports of the capacitor transimpedance amplifier array in sequence, and the structure of each integral voltage receiving circuit is the same, including a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a second capacitor C2 and a third capacitor C3;

[0055] One end of the first switch S1 and one end of the second switch S2 are both connected to the integration voltage, the other end of the first switch S1 is connected to one end of the third switch S3 via the second capacitor C2, and the other end of the third switch S3 is connected to the positive input terminal of the amplifier;

[0056] The other end of the second switch S2 is connected to one end of the fourth switch S4 through the third capacitor C3, and the other end of the fourth switch S4 is connected to the negative input end of the amplifier;

[0057] One end of the fifth switch S5 is connected to the other end of the first switch S1, the other end of the fifth switch S5 is connected to one end of the sixth switch S6, the other end of the sixth switch S6 is connected to the other end of the second switch S2, that is, the fifth switch S5 is connected in series with the sixth switch S6, and the other end of the fifth switch S5 is connected to the voltage Vcm1.

[0058] The first feedback loop and the second feedback loop have the same structure, and both include: a seventh switch S7, an eighth switch S8, a ninth switch S9 and a fourth capacitor C4;

[0059] One end of the fourth capacitor C4 is connected to one end of the ninth switch S9;

[0060] The other end of the fourth capacitor C4 is connected to the voltage V cm2 through the eighth switch S8 , and the other end of the fourth capacitor C4 is connected to one end of the seventh switch S7 .

[0061] One end of the first feedback loop is connected to the positive input end of the amplifier, and the other end of the first feedback loop is connected to the negative output end of the amplifier, that is, one end of the fourth capacitor C4 in the first feedback loop is connected to the positive input end of the amplifier, the other end of the ninth switch S9 is connected to the negative output end of the amplifier, and the other end of the seventh switch S7 is connected to the negative output end of the amplifier.

[0062] One end of the second feedback loop is connected to the negative input end of the amplifier, and the other end of the second feedback loop is connected to the positive output end of the amplifier, that is, one end of the fourth capacitor C4 in the second feedback loop is connected to the negative input end of the amplifier, the other end of the ninth switch S9 is connected to the positive output end of the amplifier, and the other end of the seventh switch S7 is connected to the positive output end of the amplifier.

[0063] like Figure 4 As shown, in a specific working process, the difference sampling circuit DDS Circuit of the present invention includes two working states: a sampling working state and an amplifying working state.

[0064] See also Figure 4 In the sample phase, when the difference sampling circuit DDS Circuit is in the sampling working state, for the first feedback loop and the second feedback loop, the ninth switch S9 and the eighth switch S8 are at a high level, and the seventh switch S7 is at a low level. When the first switch S1 and the third switch S3 of the N-way integral voltage receiving circuit are high, and the second switch S2 and the fourth switch S4 are low, that is, the first switch S1 and the third switch S3 are closed, and the second switch S2 and the fourth switch S4 are opened, the voltage of the N-way integral voltage receiving circuit charges the second capacitor C2 connected to the first switch S1 / the third switch S3, and the first switch S1 / the third switch S3 is pulled low, and the sampling is completed at time t1.

[0065] When the second switch S2 and the fourth switch S4 of the N-channel integral voltage receiving circuit are high and the first switch S1 and the third switch S3 are low, the voltage of the N-channel integral voltage receiving circuit charges the third capacitor C3 connected to the second switch S2 / the fourth switch S4, and the sampling is completed at the time t2 when the second switch S2 / the fourth switch S4 is pulled low.

[0066] After the above process is completed, the sampled voltages of the N-channel integral voltage receiving circuits at the two moments t1 and t2 are stored on the second capacitor C2 and the third capacitor C3.

[0067] See also Figure 4 In the Hold phase, when the difference sampling circuit DDS Circuit is in the amplification working state, for the first feedback loop and the second feedback loop, the ninth switch S9 and the eighth switch S8 are low level, and the seventh switch S7 is high level. When the fifth switch S5 and the sixth switch S6 of a certain integral voltage receiving circuit are high, and the third switch S3 and the fourth switch S4 are high, the voltage sampled by the integral voltage receiving circuit is amplified to the output end, and the output voltage V′ out It is expressed as:

[0068]

[0069] Where V in (t2) represents the sampling voltage at time t2, V in (t1) represents the sampling voltage at time t1, the capacitance of the second capacitor and the third capacitor is the same, which is C2; C4 is the capacitance of the fourth capacitor.

[0070] The left side of the equal sign of formula (3) represents the first sampling stage, and the right side thereof represents the amplification stage; the left side of the equal sign of formula (4) represents the second sampling stage, and the right side thereof represents the amplification stage; by subtracting formula (3) from formula (4), it can be seen that the difference sampling circuit DDS Circuit of the present invention also has an offset compensation function.

[0071]

[0072] (3)-(4):

[0073] (V os -(V1-V2))C2+V os C4=V os ·C2+(V os +V out )C4

[0074] V os ·C2-(V1-V2)·C2+V os C4=V os C2+V os C4+V out C4

[0075]

[0076] Wherein, C2 represents the capacitance of the second capacitor C2, and the second capacitor C2 is used as the input sampling capacitor of the DDS module; C4 represents the capacitance of the fourth capacitor C4, and the fourth capacitor C4 is used as the output feedback capacitor of the DDS module; V ota+ Represents the positive input voltage of OTA; V ota- represents the negative input voltage of OTA; V1 represents the input voltage of DDS at the start time t1 of the integral measurement; V2 represents the input voltage of DDS at the end time t2 of the integral measurement; V cm2 Represents the bias voltage of the DDS module output stage OTA; V cm1 Represents the bias voltage of the sampling capacitor at the input stage of the DDS module; V out- Represents the negative terminal voltage output of the DDS output stage OTA; V out+ Represents the positive terminal voltage output of the DDS output stage OTA; V os Represents the input offset voltage of the OTA, which is equal to V ota+ Subtract V ota- ; V outrepresents the differential voltage output of the DDS output stage OTA, which is equal to V out+ Subtract V out- .

[0077] After the three processes of first sampling, second sampling and amplification, the offset voltage at the OTA input can be offset.

[0078] In the specific use of DNA sequencing, the metal electrodes in NCELL are in contact with DNA cells. Under certain bioelectric experimental conditions, DNA cells will release weak currents. The DNA sequencing circuit composed of CTIA, DDS and ADC realizes the function of detecting the weak currents.

Claims

1. A current detection circuit for DNA sequencing, characterized in that: It includes a capacitive transimpedance amplifier array, a differential sampling circuit and an analog-to-digital converter for performing analog-to-digital conversion; The capacitive transimpedance amplifier array is used to perform capacitive integration on the input current and output an integrated voltage, and the capacitive transimpedance amplifier array is composed of M rows and N columns of capacitive transimpedance amplifier units; The difference sampling circuit is used to simultaneously sample multiple integrated voltages of each row of the capacitive transimpedance amplifier array, and amplify the multiple integrated voltages in sequence and then output them; The N columns of output ports of the capacitor transimpedance amplifier array are respectively connected to the N input ports of the difference sampling circuit, and the output signal of the difference sampling circuit is sent to the input end of the analog-to-digital converter; The structure of each column in the capacitive transimpedance amplifier array includes a PCELL and M NCELLs; the M NCELLs are arranged in M ​​rows in the array; The PCELL includes a first PMOS tube and a second PMOS tube, wherein the gate of the first PMOS tube is connected to a voltage V cp The drain of the first PMOS tube is used as the output port of the column, the source of the first PMOS tube is connected to the drain of the second PMOS tube, and the gate of the second PMOS tube is connected to the voltage V bp , the source of the second PMOS tube is connected to the voltage VDD; Each of the NCELLs includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a first capacitor and an electrode; the gate of the first NMOS tube is connected to the electrode, the source of the first NMOS tube is grounded, the drain of the first NMOS tube is connected to the source of the second NMOS tube; the gate of the second NMOS tube is connected to a voltage V cn , the drain of the second NMOS tube is connected to the source of the third NMOS tube; the gate of the third NMOS tube is connected to the Row Select signal, the drain of the third NMOS tube is connected to the source of the fifth NMOS tube; the gate of the fourth NMOS tube is connected to the Row Select signal, the source of the fourth NMOS tube is connected to the drain of the first PMOS tube, and the drain of the fourth NMOS tube is connected to the electrode through the first capacitor; the gate of the fifth NMOS tube is connected to the RST signal, the drain of the fifth NMOS tube is connected to the electrode, and the source of the fifth NMOS tube is connected to the drain of the third NMOS tube; When the Row Select signal is high and the RST signal is low, the NCELL enters the integration operation; when the Row Select signal is low, the NCELL stops working; when the Row Select signal and the RST signal are both high, the NCELL is reset to the initial level.

2. The current detection circuit for DNA sequencing according to claim 1, characterized in that: For any column in the capacitor transimpedance amplifier array, at most one NCELL operates normally.

3. The current detection circuit for DNA sequencing according to claim 1, characterized in that: The electrode is a metal electrode.

4. The current detection circuit for DNA sequencing according to claim 1, characterized in that: The difference sampling circuit includes N-channel integral voltage receiving circuits, an amplifier, a first feedback loop and a second feedback loop; The N-way integral voltage receiving circuits correspond to the N-column output ports of the capacitor transimpedance amplifier array in sequence, and the structure of each integral voltage receiving circuit is the same, including a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a second capacitor and a third capacitor; One end of the first switch and one end of the second switch are both connected to the integration voltage, the other end of the first switch is connected to one end of the third switch through the second capacitor, and the other end of the third switch is connected to the positive input terminal of the amplifier; the other end of the second switch is connected to one end of the fourth switch through the third capacitor, and the other end of the fourth switch is connected to the negative input terminal of the amplifier; one end of the fifth switch is connected to the other end of the first switch, the other end of the fifth switch is connected to one end of the sixth switch, the other end of the sixth switch is connected to the other end of the second switch, and the other end of the fifth switch is connected to the voltage Vcm1; The first feedback loop and the second feedback loop have the same structure, both comprising: a seventh switch, an eighth switch, a ninth switch and a fourth capacitor; one end of the fourth capacitor is connected to one end of the ninth switch; The other end of the fourth capacitor is connected to the voltage Vcm2 through the eighth switch, and the other end of the fourth capacitor is connected to one end of the seventh switch; One end of the fourth capacitor in the first feedback loop is connected to the positive input end of the amplifier, the other end of the ninth switch is connected to the negative output end of the amplifier, and the other end of the seventh switch is connected to the negative output end of the amplifier; One end of the fourth capacitor in the second feedback loop is connected to the negative input end of the amplifier, the other end of the ninth switch is connected to the positive output end of the amplifier, and the other end of the seventh switch is connected to the positive output end of the amplifier.

5. The current detection circuit for DNA sequencing according to claim 4, characterized in that: When the ninth switch and the eighth switch in the first feedback loop and the second feedback loop are at a high level, and the seventh switch is at a low level, and when the first switch and the third switch in the N-channel integral voltage receiving circuit are high, and the second switch and the fourth switch are low, the difference sampling circuit performs sampling at time t1, and t1 represents the start time of the integral measurement; When the ninth switch and the eighth switch in the first feedback loop and the second feedback loop are at a high level and the seventh switch is at a low level, and when the second switch and the fourth switch in the N-channel integral voltage receiving circuit are high and the first switch and the third switch are low, the difference sampling circuit performs sampling at time t2, and t2 indicates the end time of the integral measurement.

6. The current detection circuit for DNA sequencing according to claim 4, characterized in that: When the ninth switch and the eighth switch in the first feedback loop and the second feedback loop are at a low level, the seventh switch is at a high level, and when the fifth switch and the sixth switch in a certain integral voltage receiving circuit are high, and the third switch and the fourth switch are high, the voltage sampled by the integral voltage receiving circuit is amplified to the output end.

7. The current detection circuit for DNA sequencing according to claim 6, characterized in that: Each integral voltage receiving circuit sequentially amplifies the sampled voltage to the output end.

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