Low-power power limit circuit and electronic device

Abstract

The present invention provides a low-power consumption power limiting circuit, comprising: a power supply path module, a conversion module, a power control module and a first resistor; a first input end of the power supply path module is connected to a power supply input end, a first output end of the power supply path module is connected to a power supply output end, and the power supply output end is grounded through the first resistor, and a second output end of the power supply path module is used for outputting a detection current; the power supply path module includes a main power supply power tube, and the power supply path module is used for controlling the on-off of a current path between the power supply input end and the power supply output end by turning on or off the main power supply power tube; and when conducting, keeping the detection current proportional to the current flowing through the first resistor; wherein, the conversion module includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first current source and a second resistor.

Description

Technical Field

[0001] The present invention relates to the field of circuits, and in particular to a low-power consumption power limiting circuit and electronic equipment. Background Art

[0002] Power chips have various protections, among which overvoltage protection and overcurrent protection are more common, but a small number of power chips are designed with overpower protection, that is, they have power limiting function; power limiting is to monitor the voltage drop VIN-VOUT (set to VDS) of the main power channel power tube and the current (set to I) flowing through the main power tube, and calculate the circuit parameters related to the result of power P=VDS*I through the circuit. When the parameter exceeds a certain set value, it is considered that the power passing through the main power channel power tube exceeds the limit, and then related protective operations need to be performed, such as shutting down the main power channel power tube.

[0003] In the prior art, VDS is converted into Ivds with a fixed proportional relationship through a conversion circuit, and then calculated by a power control module to finally determine whether the power exceeds the limit. However, the circuit structure of the conversion circuit in the prior art is complex and the power consumption is high. Summary of the invention

[0004] The invention provides a low-power consumption power limiting circuit and electronic equipment, which solve the problem that the circuit structure of the conversion circuit is complex and the power consumption is high.

[0005] According to a first aspect of the present invention, there is provided a low-power consumption power limiting circuit, comprising: a power path module, a conversion module, a power control module and a first resistor;

[0006] The first input end of the power path module is connected to the power input end, the first output end of the power path module is connected to the power output end, and the power output end is grounded through the first resistor, and the second output end of the power path module is used to output a detection current; the power path module includes a main power supply power tube, and the power path module is used to control the on-off of the current path between the power input end and the power output end by turning on or off the main power supply power tube; and when turned on, the detection current is kept proportional to the current flowing through the first resistor; wherein the voltage drop VDS on the main power supply power tube is VIN-VOUT, wherein VIN is the voltage of the power input end, and VOUT is the voltage of the power output end;

[0007] The conversion module is used to convert the voltage drop VDS on the main power supply power tube into a first current according to a preset ratio;

[0008] The power control module is used to evaluate the channel power value of the main power supply power tube according to the value of the detection current and the value of the first current, and control the power path module according to the magnitude of the channel power value and a preset threshold value, so that the channel power value is below the preset threshold value;

[0009] Wherein, the conversion module includes: a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube, a first current source and a second resistor;

[0010] The source of the first PMOS tube is connected to the power output terminal; the gate of the first PMOS tube is connected to the gate of the second PMOS tube, the drain of the first PMOS tube is connected to the gate of the third PMOS tube and the drain of the first NMOS tube, the source of the second PMOS tube is connected to the source of the third PMOS tube, the drain of the second PMOS tube is connected to the gate of the first PMOS tube, the drain of the second PMOS tube is connected to the drain of the second NMOS tube and the gate of the second NMOS tube, the source of the first NMOS tube is connected to the first end of the first current source, the gate of the first NMOS tube is connected to the gate of the second NMOS tube, the source of the second NMOS tube is connected to the source of the first NMOS tube, and the second end of the first current source is connected to the second input end of the power control module; the drain of the third PMOS tube is connected to the third input end of the power control module, the source of the third PMOS tube is connected to the first end of the second resistor, and the second end of the second resistor is connected to the power input terminal;

[0011] The first PMOS tube, the second PMOS tube, the third PMOS tube, the first NMOS tube and the second NMOS tube form a negative feedback circuit, so that the voltage VO at the second end of the second resistor is equal to VOUT; the first current is the current flowing through the second resistor.

[0012] Optionally, the first current Ivds=(VIN-VO) / Rds=(VIN-VOUT) / Rds=VDS / Rds;

[0013] Wherein, Rds is the value of the second resistor.

[0014] Optionally, the low-power consumption power limiting circuit also includes a switching circuit module, which is used to cut off the path from the power supply input terminal to the second end of the second resistor when the low-power consumption power limiting circuit is not working, so that the first current is zero.

[0015] Optionally, the switch circuit module includes a second current source, a third resistor and a fourth PMOS tube;

[0016] Among them, the drain of the fourth PMOS tube is connected to the second end of the second resistor, the source of the fourth PMOS tube and the first end of the third resistor are both connected to the power input end, the second end of the third resistor is connected to the gate of the fourth PMOS tube, the second end of the third resistor is also connected to the first end of the second current source, and the second end of the second current source is connected to the power control module.

[0017] Optionally, the power control module is configured as:

[0018] When the low-power consumption power limiting circuit works normally, the second current source is controlled to generate a current value Isrc2 of the second current source to turn on the fourth PMOS tube.

[0019] Optionally, the current value Isrc2 of the second current source satisfies the condition: Isrc2<

[0020] (VIN+VTH) / Rp, wherein VTH is the threshold voltage of the fourth PMOS tube, and Rp is the resistance value of the third resistor.

[0021] Optionally, the power control module is further configured to:

[0022] When the low-power consumption power limiting circuit is not working, the current value Isrc2 of the second current source is controlled to become zero to turn off the fourth PMOS tube.

[0023] Optionally, the first PMOS tube and the second PMOS tube are of the same type and size, and the first NMOS tube and the second NMOS tube are of the same type and size.

[0024] Optionally, the power control module is configured to output a control signal to the power path module based on the magnitude of the channel power value and a preset threshold value to control the on and off of the main power supply power tube so that the channel power value is below the preset threshold value.

[0025] According to a second aspect of the present invention, there is provided an electronic device, comprising the first aspect and the optional low-power consumption power limiting circuit thereof.

[0026] The low-power consumption power limiting circuit provided by the present invention simplifies the circuit structure for converting VDS to Ivds by reducing the number of components in the conversion module, and further reduces the difficulty of circuit design and the power consumption of the circuit.

[0027] In a preferred embodiment, the present invention uses a switching circuit module to control the disconnection of the path from the power input terminal to the second end of the second resistor when the low-power power limiting circuit is not working, so that the first current is zero, further reducing the power consumption of the low-power power limiting circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0029] Figure 1 is a schematic diagram of the structure of a power limiting circuit of the prior art in an example of the present invention;

[0030] Figure 2 The structure of the low power consumption power limiting circuit in one embodiment of the present invention is shown in FIG. Figure 1 ;

[0031] Figure 3 The structure of the low power consumption power limiting circuit in one embodiment of the present invention is shown in FIG. Figure 2 ;

[0032] Figure 4 The structure of the low power consumption power limiting circuit in one embodiment of the present invention is shown in FIG. Figure 3 ;

[0033] Description of reference numerals:

[0034] 1- Power path module;

[0035] 2-Conversion module;

[0036] 201-first PMOS tube;

[0037] 202- second PMOS tube;

[0038] 203-first NMOS tube;

[0039] 204- a second NMOS tube;

[0040] 205- the third PMOS tube;

[0041] 206-a first current source;

[0042] 207- second resistor;

[0043] 3- Power control module;

[0044] 4- first resistor;

[0045] 5-Switch circuit module;

[0046] 501 - a second current source;

[0047] 502- a third resistor;

[0048] 503-the fourth PMOS tube. DETAILED DESCRIPTION

[0049] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0050] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0051] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0052] Before filing this application, the applicant conducted a thorough study on the power limiting circuit and proposed a Figure 1 The power limiting circuit shown, for Figure 1 The power limiting circuit shown in the figure needs to use 10 MOS tubes to convert VDS into Ivds with a fixed ratio. Figure 1As shown, the power limiting circuit includes: a power control module, a power path module, a first resistor R1, a second resistor Ro, a third resistor Ri, a first current source Isrc1, a second current source Isrc2, a first PMOS tube P1, a second PMOS tube P2, a first NMOS tube NC1, a second NMOS tube NC2, a third NMOS tube NC3, a fourth NMOS tube NC4, a fifth NMOS tube N1, a sixth NMOS tube N2, a seventh NMOS tube N3 and an eighth NMOS tube N4.

[0053] Wherein, a first end of the power control module is connected to VIN, a second end of the power control module is connected to a first end of the power path module, a third end of the power control module is connected to a control end of the power path module, a fourth end of the power control module is connected to a first end of the first current source Isrc1, a second end of the first current source Isrc1 is connected to a drain of the first NMOS tube NC1, a second end of the first current source Isrc1 is also connected to a gate of the fifth NMOS tube N1, a gate of the first NMOS tube NC1 is connected to a gate of the second NMOS tube NC2, a source of the first NMOS tube NC1 is connected to a drain of the fifth NMOS tube N1, a source of the first NMOS tube NC1 is also connected to a first end of the third resistor Ri, a second end of the third resistor Ri is connected to VIN, a drain of the second NMOS tube NC2 is connected to a drain of the first PMOS tube P1, a source of the second NMOS tube NC2 is connected to a drain of the sixth NMOS tube N2, a gate of the fifth NMOS tube N1 is connected to a gate of the sixth NMOS tube N2, and a gate of the fifth NMOS tube N1 is connected to a gate of the sixth NMOS tube N2. The source of the transistor N1 is grounded, the source of the fifth NMOS transistor N1 is also connected to the source of the sixth NMOS transistor N2; the gate of the first PMOS transistor P1 is connected to the gate of the second PMOS transistor P2, the drain of the first PMOS transistor P1 is also connected to the gate of the second PMOS transistor P2, the source of the first PMOS transistor P1 is connected to VIN, the source of the second PMOS transistor P2 is connected to VIN, the drain of the second PMOS transistor P2 is connected to the drain of the third NMOS transistor NC3, the drain of the second PMOS transistor P2 is also connected to the fifth end of the power control module, the gate of the third NMOS transistor NC3 is connected to the gate of the fourth NMOS transistor NC4, the source of the third NMOS transistor NC3 is connected to the seventh NMOS The drain of the fourth NMOS tube N3 is connected to the first end of the second current source Isrc2, the drain of the fourth NMOS tube NC4 is also connected to the gate of the seventh NMOS tube N3, the gate of the seventh NMOS tube N3 is connected to the gate of the eighth NMOS tube N4, the source of the seventh NMOS tube N3 is connected to the source of the eighth NMOS tube N4, the drain of the eighth NMOS tube N4 is also connected to the first end of the second resistor Ro, the second end of the second resistor Ro is connected to the first end of the first resistor R1, the second end of the first resistor R1 is grounded, the first end of the first resistor R1 is also connected to the second end of the power path module, and the third end of the power path module is connected to the sixth end of the power control module.

[0054] Specifically, Figure 1In the scheme shown, during circuit design, the gates of the first NMOS tube NC1, the second NMOS tube NC2, the third NMOS tube NC3 and the fourth NMOS tube NC4 are controlled to be given a voltage of the same magnitude, the power limit control module outputs the same current sources Isrc1 and Isrc2, i.e., Isrc1=Isrc2, the first NMOS tube NC1 and the fourth NMOS tube NC4 use the same NMOS tube, so the gate-source voltage of the first NMOS tube NC1 and the gate-source voltage of the fourth NMOS tube NC4 are also equal, so that Figure 1 The voltage in is Vi=Vo.

[0055] Specifically, by Figure 1 It can be known that: Iri=(VIN-Vi) / Ri, Iro=(VOUT-Vo) / Ro, In1=Iri+Isrc1, In4=Iro+Isrc2; due to the mirror current relationship between the fifth NMOS tube N1 and the sixth NMOS tube N2 and the mirror current relationship between the seventh NMOS tube N3 and the eighth NMOS tube N4, it can be obtained that: I1=In1=Iri+Isrc1, I2=In4=Iro+Isrc2; due to the mirror current relationship between the first PMOS tube P1 and the second PMOS tube P2, it can be obtained that: Ip1=Ip2; wherein Ip1=I1, Ip2=I2+Ivds, therefore I1=I2+Ivds.

[0056] Combining the above formulas, we can get: Ivds=I1-I2=In1-In4=Iri+Isrc1-(Iro+Isrc2)=Iri-Iro= (VIN-Vi) / Ri-(VOUT_Vo) / Ro; and because Vi=Vo and Ri=Ro, let R=Ri=Ro, and we can get Ivds=(VIN-VOUT) / R, that is, the voltage difference VDS of the power tube is converted into Ivds with a fixed proportional relationship through the above circuit, that is, VDS=VIN-VOUT=Ivds*R, where R is a fixed resistance value in the design.

[0057] In the above scheme, the current I of the main power channel from VIN to VOUT can flow into the system load Rl (i.e., the first resistor) through the power output pin VOUT. At this time, the current I can also generate Isns through the current mirror circuit. Usually, I is reduced by an integer multiple of n to Isns, that is, Isns=I / n.

[0058] Isns and Ivds are both connected to the power control module, which is used to calculate the product of current Isns and Ivds. When the result is greater than a preset threshold, that is, the product of VDS and I is greater than a certain power value, the power control module outputs a signal Ctrl to the power path module to control the shutdown of the main power channel (for example, disconnecting the power tube).

[0059] It can be seen that the power limiting circuit in the above scheme requires 10 MOS tubes, two current sources Isrc1 and Isrc2, and two resistors Ri and Ro to realize a circuit that converts VDS into Ivds with a fixed proportional relationship. There are many circuit components, which increases the difficulty of circuit design and circuit power consumption. In addition, the two current sources Isrc1 and Isrc2 and the two resistors Ri and Ro need to be ensured to be equal, resulting in the need for precise design or complex circuit feedback to ensure the equality of the above parameters, further increasing the complexity of the circuit.

[0060] In view of this, the present invention proposes a new power limiting circuit, which only requires five MOS tubes to achieve the above effect.

[0061] Regarding the solution of the present invention, the specific description is as follows:

[0062] Please refer to Figure 2 as well as Figure 3 The present invention provides a low-power consumption power limiting circuit, comprising: a power path module 1, a conversion module 2, a power control module 3 and a first resistor 4.

[0063] The first input end of the power path module 1 is connected to the power input end (i.e., VIN), the first output end of the power path module 1 is connected to the power output end (i.e., VOUT), and the power output end (i.e., VOUT) is grounded through the first resistor 4, and the second output end of the power path module 1 is used to output a detection current Isns; the power path module 1 includes a main power supply power tube, and the power path module 1 is used to control the on-off of the current path between the power input end (i.e., VIN) and the power output end (i.e., VOUT) by turning on or off the main power supply power tube; and when turned on, the detection current Isns is kept proportional to the current I flowing through the first resistor 4; wherein the voltage drop VDS on the main power supply power tube is VIN-VOUT, wherein VIN is the voltage of the power input end, and VOUT is the voltage of the power output end.

[0064] The conversion module 2 is used to convert the voltage drop VDS on the main power tube into a first current Ivds according to a preset ratio.

[0065] The power control module 3 is used to evaluate the channel power value of the main power supply power tube according to the value of the detection current Isns and the value of the first current Ivds, and control the power path module 1 according to the size of the channel power value and a preset threshold value, so that the channel power value is below the preset threshold value;

[0066] The conversion module 2 includes: a first PMOS transistor 201, a second PMOS transistor 202, a third PMOS transistor 205, a first NMOS transistor 203, a second NMOS transistor 204, a first current source 206 and a second resistor 207;

[0067] The source of the first PMOS tube 201 is connected to the power output terminal (i.e., VOUT); the gate of the first PMOS tube 201 is connected to the gate of the second PMOS tube 202, the drain of the first PMOS tube 201 is connected to the gate of the third PMOS tube 205 and the drain of the first NMOS tube 203, the source of the second PMOS tube 202 is connected to the source of the third PMOS tube 205, and the drain of the second PMOS tube 202 is connected to the gate of the first PMOS tube 201. The gate of the second PMOS tube 202 is connected to the drain of the second NMOS tube 204 and the gate of the second NMOS tube 204, the source of the first NMOS tube 203 is connected to the first end of the first current source 206, the gate of the first NMOS tube 203 is connected to the gate of the second NMOS tube 204, the source of the second NMOS tube 204 is connected to the source of the first NMOS tube 203, and the second end of the first current source 206 is connected to the second input end of the power control module 3; the drain of the third PMOS tube 205 is connected to the third input end of the power control module 3, the source of the third PMOS tube 205 is connected to the first end of the second resistor 207, and the second end of the second resistor 207 is connected to the power input end.

[0068] The first PMOS transistor 201, the second PMOS transistor 202, the third PMOS transistor 205, the first NMOS transistor 203, and the second NMOS transistor 204 form a negative feedback circuit, so that the voltage VO at the second end of the second resistor 207 is equal to VOUT; the first current Ivds is the current flowing through the second resistor 207.

[0069] In a preferred implementation manner, the first PMOS transistor 201 and the second PMOS transistor 202 are of the same type and size, and the first NMOS transistor 203 and the second NMOS transistor 204 are of the same type and size.

[0070] Regarding the calculation of the first current, in a specific embodiment:

[0071] The first current Ivds=(VIN−VO) / Rds=(VIN−VOUT) / Rds=VDS / Rds; wherein Rds is the value of the second resistor 207 .

[0072] Specifically, in combination with the above negative feedback circuit, the implementation of VO=VOUT in the above calculation formula is as follows:

[0073] In one example, when VOUT is greater than VO, the voltage of the drain of the first PMOS tube 201 and the gate of the third PMOS tube 205 are raised, so the source-gate voltage difference of the third PMOS tube 205 becomes smaller, and the source-drain current of the third PMOS tube 205 also becomes smaller, and then the voltage drop on the second resistor 207 becomes smaller, and VO is raised to achieve VO=VOUT.

[0074] In another example, when VOUT is less than VO, the voltage of the drain of the first PMOS tube 201 and the gate of the third PMOS tube 205 are pulled down, so the source-gate voltage difference of the third PMOS tube 205 becomes larger, and the source-drain current of the third PMOS tube 205 also becomes larger, and then the voltage drop on the second resistor 207 becomes larger, and VO is pulled down to achieve VO=VOUT.

[0075] Regarding the output of the detection current Isns, in a specific embodiment, the power path module 1 includes a current mirror unit, which is used to generate the detection current Isns and transmit the detection current Isns to the power control module 3, wherein the detection current is proportional to the current flowing through the first resistor 4, for example Isns=I / n, I is the current on the first resistor 4.

[0076] Regarding the evaluation of the channel power value of the main power supply power tube, in a specific embodiment, the power control module 3 receives the detection current Isns and the first current Ivds, and calculates the product of Isns and Ivds.

[0077] Regarding the power control module 3, in a specific embodiment, the power control module 3 is configured to: output a control signal to the power path module 1 based on the size of the channel power value and a preset threshold value, so as to control the on and off of the main power supply power tube so that the channel power value is below the preset threshold value.

[0078] Specifically, when Isns*Ivds is greater than a preset threshold, the power control module 3 outputs a signal to the control end of the power path module 1 to control the power path module 1 to be disconnected, thereby realizing power protection of the circuit.

[0079] Specifically, since the channel power value P of the main power supply power tube is P=VDS*I; and from the above scheme it can be seen that VDS=Ivds*Rds, Isns=I / n, therefore P=VDS*I=Ivds*Rds*nIsns, wherein the resistance value Rds of the second resistor 207 is a fixed resistance value, it can be seen that the channel power value of the main power supply power tube can be evaluated by Isns*Ivds.

[0080] It can be seen that the conversion module 2 in the above scheme can realize the conversion of the voltage drop VDS on the main power supply power tube into the first current according to the preset ratio by using five MOS tubes, one resistor and one current source, thereby reducing the number of circuit elements and simplifying the circuit structure. In addition, in addition to the first current Ivds, the additional working current required by the low-power power limiting circuit is only the current value Isrc1 of the first current source 206, and the current value Isrc1 is only Figure 1 The current value I1+I2+In1+In4 in the existing solution is reduced to a few tenths of the sum, thereby reducing circuit power consumption.

[0081] In addition, compared Figure 1 In the power limiting circuit of the prior art, the conversion circuit of VDS to Ivds in the low-power power limiting circuit provided in the present application only needs a second resistor 207, and does not need Figure 1 In the prior art, the power limiting circuit performs precise matching on Isrc1 and Isrc2 as well as Ri and Ro, and more matching designs are performed on the mirror current circuit.

[0082] Please refer to Figure 4 In a preferred embodiment, the low-power consumption power limiting circuit further includes a switch circuit module 5, and the switch circuit module 5 includes a second current source 501, a third resistor 502 and a fourth PMOS tube 503;

[0083] Among them, the drain of the fourth PMOS tube 503 is connected to the second end of the second resistor 207, the source of the fourth PMOS tube 503 and the first end of the third resistor 502 are both connected to the power input end, the second end of the third resistor 502 is connected to the gate of the fourth PMOS tube 503, the second end of the third resistor 502 is also connected to the first end of the second current source 501, and the second end of the second current source 501 is connected to the power control module 3.

[0084] The switch circuit module 5 is used to cut off the path from the power input terminal to the second end of the second resistor 207 when the low-power consumption power limiting circuit is not working, so that the first current is zero.

[0085] In one embodiment, the power control module 3 is configured to: when the low-power power limiting circuit operates normally, control the second current source 501 to generate a current value Isrc2 of the second current source 501 to turn on the fourth PMOS tube 503 .

[0086] In a specific embodiment, the current value Isrc2 of the second current source 501 satisfies the condition: Isrc2<(VIN+VTH) / Rp, wherein VTH is the threshold voltage of the fourth PMOS transistor 503 , and Rp is the resistance value of the third resistor 502 .

[0087] In a preferred embodiment, when the power control module 3 is working, a current value Isrc2 of the second current source 501 is generated, so that the voltage value obtained by Rp*Isrc2 can make the fourth PMOS tube 503 fully turned on and the fourth PMOS tube 503 will not be damaged due to too large a voltage value.

[0088] The on-resistance of the fourth PMOS transistor 503 can be ignored, that is, the voltage VIN at the power input terminal is approximately equal to the voltage VI on the fourth PMOS transistor 503 .

[0089] In other preferred implementations, when the low-power consumption power limiting circuit is not working, the current value Isrc2 of the second current source 501 is controlled to become zero to turn off the fourth PMOS tube 503 .

[0090] Specifically, when the power control module 3 is turned off, the current value Isrc2 of the second current source 501 becomes zero, and then the voltage drop Rp*Isrc2 on Rp is also 0, so that the fourth PMOS tube 503 is turned off.

[0091] In one embodiment, the switch circuit uses a switch tube to control the first current Ivds.

[0092] Of course, the present invention is not limited thereto, and other circuits capable of controlling the first current Ivds are within the protection scope of the present invention.

[0093] In the above scheme, by adding the switch control module, the opening and closing functions of the Ivds current are realized. Specifically, the power control module 3 controls the current value Isrc2 of the second current source 501 to control the on and off of the fourth PMOS tube 503, and finally realizes the control of the Ivds current; when the power control module 3 does not need to work, the fourth PMOS tube 503 is turned off, thereby realizing the shutoff of the Ivds current, further reducing the power consumption of the circuit; in addition, by controlling the current value Isrc2 of the second current source 501 through the power control module 3, it is ensured that the fourth PMOS tube 503 will not be damaged due to excessive gate-source voltage difference when it is turned off, thereby further ensuring the safety of the circuit.

[0094] The present invention also provides an electronic device, comprising the above-mentioned low-power consumption power limiting circuit.

[0095] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A low-power power limiting circuit, characterized in that, it includes: a power path module, a conversion module, a power control module, and a first resistor; The first input end of the power path module is connected to the power input end, the first output end of the power path module is connected to the power output end, and the power output end is grounded through the first resistor. The second output end of the power path module is used to output a detection current. The power path module includes a main power transistor. The power path module is used to control the on-off of the current path between the power input end and the power output end by turning on or off the main power transistor. And when conducting, keep the detection current proportional to the current flowing through the first resistor. Wherein, the voltage drop VDS on the main power transistor is VIN - VOUT, where VIN is the voltage of the power input end and VOUT is the voltage of the power output end; The conversion module is used to convert the voltage drop VDS on the main power transistor into a first current according to a preset ratio; The power control module is used to evaluate the channel power value of the main power transistor according to the value of the detection current and the value of the first current, and control the power path module according to the size relationship between the channel power value and a preset threshold, so that the channel power value is below the preset threshold; Wherein, the conversion module includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first current source, and a second resistor; The source of the first PMOS transistor is connected to the power output end; the gate of the first PMOS transistor is connected to the gate of the second PMOS transistor. The drain of the first PMOS transistor is connected to the gate of the third PMOS transistor and the drain of the first NMOS transistor. The source of the second PMOS transistor is connected to the source of the third PMOS transistor. The drain of the second PMOS transistor is connected to the gate of the first PMOS transistor. The drain of the second PMOS transistor is connected to the drain of the second NMOS transistor and the gate of the second NMOS transistor. The source of the first NMOS transistor is connected to the first end of the first current source. The gate of the first NMOS transistor is connected to the gate of the second NMOS transistor. The source of the second NMOS transistor is connected to the source of the first NMOS transistor. The second end of the first current source is connected to the second input end of the power control module; the drain of the third PMOS transistor is connected to the third input end of the power control module. The source of the third PMOS transistor is connected to the first end of the second resistor. The second end of the second resistor is connected to the power input end; Wherein, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the first NMOS transistor, and the second NMOS transistor form a negative feedback circuit, so that the voltage VO at the second end of the second resistor is equal to VOUT; the first current is the current flowing through the second resistor; Among them, the types and sizes of the first PMOS transistor and the second PMOS transistor are the same, and the types and sizes of the first NMOS transistor and the second NMOS transistor are the same.

2. The low-power power limiting circuit according to claim 1, wherein, the first current Ivds = (VIN - VO) / Rds = (VIN - VOUT) / Rds = VDS / Rds; wherein, Rds is the value of the second resistor.

3. The low-power power limiting circuit according to claim 1, wherein, it further includes a switch circuit module, and the switch circuit module is used to turn off the path from the power input terminal to the second end of the second resistor when the low-power power limiting circuit is not working, so that the first current is zero.

4. The low-power power limiting circuit according to claim 3, wherein, the switch circuit module includes a second current source, a third resistor, and a fourth PMOS transistor; wherein, the drain of the fourth PMOS transistor is connected to the second end of the second resistor, the source of the fourth PMOS transistor and the first end of the third resistor are both connected to the power input terminal, the second end of the third resistor is connected to the gate of the fourth PMOS transistor, the second end of the third resistor is also connected to the first end of the second current source, and the second end of the second current source is connected to the power control module.

5. The low-power power limiting circuit according to claim 4, wherein, the power control module is configured to: when the low-power power limiting circuit is working properly, control the second current source to generate the current value Isrc2 of the second current source to turn on the fourth PMOS transistor.

6. The low-power power limiting circuit according to claim 5, wherein, the condition satisfied by the current value Isrc2 of the second current source is: Isrc2 < (VIN + VTH) / Rp, where VTH is the threshold voltage of the fourth PMOS transistor, and Rp is the resistance value of the third resistor.

7. The low-power power limiting circuit according to claim 5, wherein, the power control module is further configured to: when the low-power power limiting circuit is not working, control the current value Isrc2 of the second current source to become zero to turn off the fourth PMOS transistor.

8. The low-power power limiting circuit according to claim 1, wherein, the power control module is configured to: output a control signal to the power path module according to the magnitude of the channel power value and a preset threshold value to control the on / off of the main power transistor, so that the channel power value is below the preset threshold value.

9. An electronic device, wherein, it includes the low-power power limiting circuit according to any one of claims 1 to 8.

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