Power supply control device and control method thereof

Abstract

The present invention discloses a power control device and a control method thereof, comprising: a first delay module, a second delay module, a NAND gate, first to third NAND gates, an input end and an output end; the input end is electrically connected to the input of the first delay module and the input of the second delay module through the first NAND gate; the output of the first delay module is electrically connected to one input of the NAND gate, and the output of the second delay module is electrically connected to the other input of the NAND gate through the second NAND gate; the output of the NAND gate is electrically connected to the output end through the third NAND gate; the input end is used to be electrically connected to the refresh control end of the memory, and the output end is used to be electrically connected to the power supply device of the memory to control the start and shut down of the power supply device. A power control device is added between the refresh control end and the power supply device, so that in the self-refresh action cycle, the power supply device only provides power for a part of the time, and the power supply device is shut down in the other part of the time when the self-refresh action is not actually performed, thereby reducing current consumption.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a power supply control device and a control method thereof. Background Art

[0002] In DRAM memory design, as the feature size of memory chips becomes smaller and smaller, the chip's power consumption requirements are also getting higher and higher. Due to the leakage of storage capacitors in memory chips, a self-refresh action must be performed at regular intervals. In this way, the internal power supply device of the memory chip must be driven frequently to achieve self-refresh, thereby continuously consuming a certain amount of current. As the storage capacity of the memory chip increases, its refresh power consumption also becomes higher and higher. Summary of the invention

[0003] The purpose of the present application is to propose a power supply control device and a control method thereof in view of the deficiencies of the above-mentioned prior art, and the purpose is achieved through the following technical solutions.

[0004] A first aspect of the present application provides a power control device, the power control device comprising: a first delay module, a second delay module, a NAND gate, first to third NAND gates, an input end and an output end;

[0005] The input end is electrically connected to the input of the first delay module and the input of the second delay module through the first NOT gate; the output of the first delay module is electrically connected to one input of the NAND gate, and the output of the second delay module is electrically connected to the other input of the NAND gate through the second NOT gate; the output of the NAND gate is electrically connected to the output end through the third NOT gate;

[0006] The input end is used to be electrically connected to a refresh control end of the memory, and the output end is used to be electrically connected to a power supply device of the memory to control the start and shut down of the power supply device.

[0007] A second aspect of the present application provides a control method for the power supply control device as described in the first aspect above, the method comprising:

[0008] Input a low level pulse signal to the input terminal of the power control device through the refresh control terminal of the memory;

[0009] When the delay time of the first delay module in the power control device has passed, the output end of the power control device inputs a high level signal to the power device of the memory to shut down the power device;

[0010] When the delay time of the second delay module in the power control device has passed, the output end of the power control device outputs a low level signal to the power device to start the power device;

[0011] Wherein, within the delay time of the first delay module, the memory completes a self-refresh action.

[0012] A third aspect of the present application provides a memory, comprising the power control device as described in the first aspect above.

[0013] Based on the power supply control device and the control method thereof described in the first and second aspects above, the present application has the following beneficial effects:

[0014] In practical applications, the self-refresh action of DRAM memory is periodic, and the actual execution of the self-refresh action only takes a part of the time in the entire cycle, but the power supply device of the memory is often driven and continuously consumes current. Therefore, the present application adds a power supply control device between the refresh control end of the memory and the power supply device, so that when a low-level pulse signal for executing the self-refresh action is generated at the refresh control end of the memory, the power supply device is maintained to continuously supply power within the delay time of the first delay module of the power supply control device to complete the execution of the self-refresh action of the memory. When the delay time of the first delay module is reached, the power supply device is turned off to reduce current consumption during the time when the self-refresh action is not actually executed, and the power supply device is turned on again after the delay time of the second delay module of the power supply control device has passed, so as to complete the next self-refresh action when the next low-level pulse signal is generated, and so on. It can be seen from this that in each self-refresh action cycle of the memory, the power supply device is only started for a part of the time to provide power for the actual execution of the self-refresh action. In the other part of the time when the self-refresh action is not actually performed, the power supply device is turned off and does not consume current. Therefore, without affecting the self-refresh action of the memory, the current consumption of the power supply device can be reduced through the power control device, thereby reducing the power consumption of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0016] Figure 1 A schematic diagram of the signal timing of a refresh control terminal and a power control terminal of a memory in the prior art;

[0017] Figure 2 This is a schematic diagram of the structure of a power supply control device according to an exemplary embodiment of the present application;

[0018] Figure 3Based on Figure 2 A schematic diagram of the signal timing of the refresh control terminal and the power control terminal of the memory shown in the embodiment shown;

[0019] Figure 4 A schematic diagram of the structure of a reference voltage generator shown in the present application;

[0020] Figure 5 This is a flow chart of an embodiment of a control method for a power control device according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0022] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0023] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element or an intervening layer / element may exist therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, the layer / element may be "below" the other layer / element when the orientation is reversed.

[0024] In existing memory chip designs, the internal power supply device needs to be frequently driven to implement the periodic self-refresh operation of the memory. In this way, the power supply device will continuously consume current, resulting in relatively high self-refresh power consumption of the memory chip.

[0025] The inventors have found that Figure 1As shown, the self-refresh action of the memory is triggered by the low-level pulse signal of the self-refresh control terminal SRPB. A self-refresh action is performed immediately each time a low-level pulse signal is generated. The time interval between two low-level pulse signals is the self-refresh cycle, and the time from the generation of the low-level pulse signal to the completion of the self-refresh action only takes a small part of the time in a complete self-refresh cycle. The time when the self-refresh action is not actually performed takes up most of the self-refresh cycle. However, the power control terminal SRPC of the power supply device inside the memory is always at a low level, and the power supply device continues to consume current.

[0026] In order to solve the above technical problems, the inventor added a power control device between the refresh control end of the memory and the power supply device to control the start and shut down of the power supply device according to the signal of the refresh control end. That is, during the actual execution of the self-refresh action, the power supply device continues to provide power, and during the period when the self-refresh action is not actually executed, the power supply device is turned off and does not consume current.

[0027] See also Figure 2 As shown, the power control device includes a first NOT gate 1, a first delay module 2, a second delay module 3, a second NOT gate 4, a NAND gate 5, a third NOT gate 6, an input terminal a and an output terminal b.

[0028] The specific link relationship is: the input terminal a is electrically connected to the input of the first delay module 2 and the input of the second delay module 3 through the first NOT gate 1; the output of the first delay module 2 is electrically connected to one input of the NAND gate 5, and the output of the second delay module 3 is electrically connected to the other input of the NAND gate 5 through the second NOT gate 4; the output of the NAND gate 5 is electrically connected to the output terminal b through the third NOT gate 6.

[0029] The input terminal a is used to be electrically connected to the refresh control terminal SRPB of the memory, and the output terminal b is used to be electrically connected to the power control terminal SRPC of the power supply device of the memory to control the start and stop of the power supply device.

[0030] In some embodiments, Figure 3 As shown, the Figure 2 The power control device shown is a timing diagram of the refresh control end and the power control end. In order to achieve the purpose of the power supply device continuously providing power during the actual execution of the self-refresh action, and turning off the power supply device during the actual non-execution of the self-refresh action, the delay time Delay1 of the first delay module 2 is set to be smaller than the delay time Delay2 of the second delay module 3.

[0031] Those skilled in the art can understand that, for the specific implementation of the first delay module 2 and the second delay module 3, the present application can adopt the existing delay circuit structure, and the present application does not make specific limitations on this, as long as the corresponding delay function can be achieved.

[0032] Combination Figure 2 and Figure 3 As shown, the process of the power control device controlling the start and shut down of the power supply device according to the signal of the refresh control terminal SRPB is as follows: after the refresh control terminal SRPB inputs a low-level pulse signal to the input terminal a, after the delay time Delay1 of the first delay module 2, the output terminal b outputs a high-level signal to the power control terminal SRPC of the power supply device to trigger the shutdown of the power supply device, and then after the delay time Delay2 of the second delay module 3, the output terminal b outputs a low-level signal to the power control terminal SRPC to trigger the startup of the power supply device.

[0033] The low level pulse signal inputted from the refresh control terminal SRPB to the input terminal a is used to control the memory to perform a self-refresh operation.

[0034] It can be seen that when a low-level pulse signal is generated at the refresh control terminal SRPB, the power supply device continues to supply power within the delay time Delay1 of the first delay module 2 to complete the execution of the self-refresh action of the memory. When the delay time Delay1 of the first delay module 2 is reached, the power supply device is turned off to reduce current consumption during the time when the self-refresh action is not actually performed. The power supply device is turned on again when the delay time Delay2 of the second delay module 3 of the power control device is passed to complete the next self-refresh action when the next low-level pulse signal is generated, and so on.

[0035] It should be noted that in order to ensure that the self-refresh action of the memory is executed thoroughly, the delay time Delay1 of the first delay module 2 needs to be greater than the duration of the low-level pulse signal, and the delay time Delay2 of the second delay module 3 needs to arrive some time before the next low-level pulse signal arrives, so that the time when the refresh control terminal SRPB generates a low-level pulse signal is completely within the startup period of the power supply device.

[0036] In some embodiments, the power supply device of the memory described above may be a reference voltage generator, such as Figure 4 As shown, it is a schematic diagram of the circuit structure of an exemplary reference voltage generator. When a low-level signal is input to the power control terminal SRPC, the voltage output terminal VREF of the reference voltage generator outputs a power reference voltage greater than 0 to provide power for the self-refresh action. When a high-level signal is input to the power control terminal SRPC, the power reference voltage output by the voltage output terminal VREF of the reference voltage generator is 0, and the reference voltage generator is in the off state.

[0037] Corresponding to the aforementioned power control device embodiment, the present application also provides an embodiment of a control method of the power control device.

[0038] Figure 5 This is a flow chart of an embodiment of a control method of a power control device according to an exemplary embodiment of the present application. Figures 2 to 3 Based on the embodiment shown, the control method of the power control device includes the following steps:

[0039] Step 501: Input a low level pulse signal to the input terminal of the power control device through the refresh control terminal of the memory.

[0040] The low-level pulse signal generated by the refresh control terminal of the memory is used to trigger the memory to perform a self-refresh action, and the generation of the low-level pulse signal is periodic.

[0041] Step 502: When the delay time of the first delay module in the power control device has elapsed, the output end of the power control device inputs a high level signal to the power device of the memory to shut down the power device.

[0042] See also Figure 2 and Figure 3 As shown, the low-level pulse signal input at the input terminal a is converted into a high-level signal after passing through the first NOT gate 1 and enters the first delay module 2. After the delay time Delay1 of the first delay module 2, the high-level signal reaches the input of the NAND gate 5. At this time, since the delay time Delay2 of the second delay module 3 has not yet arrived, the other input of the NAND gate 5 is in a suspended state. The suspended state of the NAND gate is equivalent to the input being at a high level, so that the output of the NAND gate 5 is a low-level signal. After the low-level signal passes through the third NOT gate 6, the output terminal b outputs a high-level signal, and the high-level signal triggers the power supply device to shut down.

[0043] Therefore, the power supply device is always turned on during the delay time of the first delay module 2 to ensure that the memory can complete the self-refresh action.

[0044] Step 503: After the delay time of the second delay module in the power control device has elapsed, the output end of the power control device inputs a low level signal to the power device to start the power device.

[0045] Among them, since the delay time of the first delay module 2 is shorter than the delay time of the second delay module 3, in terms of time, the high level signal converted from the low level pulse signal through the first NOT gate 1 first passes through the first delay module 2 and then passes through the second delay module 3 connected in parallel with the first delay module 2.

[0046] Continue to see Figure 2 and Figure 3As shown, the low-level pulse signal input at the input terminal a is converted into a high-level signal after passing through the first NOT gate 1 and enters the second delay module 3. After the delay time Delay2 of the second delay module 3, the high-level signal reaches the second NOT gate 4. The high-level signal is converted into a low-level signal after passing through the second NOT gate 4 and reaches the input of the NAND gate 5. At this time, no matter whether the other input of the NAND gate is a high-level signal or a low-level signal, the output of the NAND gate 5 is a high-level signal. After the high-level signal passes through the third NOT gate 6, the output terminal b outputs a low-level signal, and the low-level signal triggers the power supply device to start providing power.

[0047] For the specific implementation of the above steps 501 to 503, please refer to the above Figures 2 to 3 The relevant description of the illustrated embodiment will not be described in detail herein.

[0048] At this point, the above Figure 5 The control flow shown is that a power control device is added between the refresh control end of the memory and the power supply device, so that when a low-level pulse signal for executing a self-refresh action is generated at the refresh control end of the memory, the power supply device is maintained to supply power within the delay time of the first delay module of the power control device to complete the execution of the self-refresh action of the memory, and when the delay time of the first delay module is reached, the power supply device is turned off to reduce the current consumption during the time when the self-refresh action is not actually executed, and the power supply device is turned on again after the delay time of the second delay module of the power control device has passed, so as to complete the next self-refresh action when the next low-level pulse signal is generated, and so on. It can be seen that in each self-refresh action cycle of the memory, only a part of the time is the power supply device started to provide power for the actual execution of the self-refresh action, and the power supply device is turned off in the other part of the time when the self-refresh action is not actually executed, and does not consume current, so that the current consumption of the power supply device can be reduced by the power control device without affecting the self-refresh action of the memory, thereby reducing the power consumption of the memory.

[0049] The present application also proposes a memory, which includes the power control device as described in the above embodiment.

[0050] In some embodiments, the memory may be any one of DRAM (Dynamic Random-Access Memory), SDRAM (Synchronous Dynamic Random Access Memory), etc.

[0051] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0052] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, a person skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A power supply control device, characterized in that: The power supply control device comprises: a first delay module, a second delay module, a NAND gate, first to third NAND gates, an input terminal and an output terminal; The input end is electrically connected to the input of the first delay module and the input of the second delay module through the first NOT gate; the output of the first delay module is electrically connected to one input of the NAND gate, and the output of the second delay module is electrically connected to the other input of the NAND gate through the second NOT gate; the output of the NAND gate is electrically connected to the output end through the third NOT gate; The input end is used to be electrically connected to a refresh control end of the memory, and the output end is used to be electrically connected to a power supply device of the memory to control the start and shut down of the power supply device.

2. The power supply control device according to claim 1, characterized in that: The delay time of the first delay module is shorter than the delay time of the second delay module.

3. The power supply control device according to claim 2, characterized in that: After the refresh control end inputs a low-level pulse signal to the input end, after the delay time of the first delay module, the output end outputs a high-level signal to turn off the power supply device of the memory, and then after the delay time of the second delay module, the output end outputs a low-level signal to start the power supply device of the memory.

4. The power supply control device according to claim 3, characterized in that: The low level pulse signal inputted by the refresh control terminal to the input terminal is used to control the memory to perform a self-refresh action.

5. The power supply control device according to claim 1, characterized in that: The power supply device of the memory is a reference voltage generator.

6. A control method for a power supply control device as claimed in any one of claims 1 to 5, characterized in that: The method comprises: Input a low level pulse signal to the input terminal of the power control device through the refresh control terminal of the memory; When the delay time of the first delay module in the power control device has passed, the output end of the power control device inputs a high level signal to the power device of the memory to shut down the power device; When the delay time of the second delay module in the power control device has passed, the output end of the power control device outputs a low level signal to the power device to start the power device; Wherein, within the delay time of the first delay module, the memory completes a self-refresh action.

7. The method according to claim 6, characterized in that When the delay time of the first delay module in the power control device has passed, the output end of the power control device inputs a high level signal to the power device of the memory, including: The low-level pulse signal enters the first delay module after being converted into a high-level signal by the first NOT gate in the power control device; After the delay time of the first delay module, the high-level signal reaches the input of the NAND gate in the power control device, at which time the other input of the NAND gate is in a suspended state, and the output of the NAND gate is a low-level signal; After the low level signal passes through the third NOT gate in the power control device, the output end of the power control device outputs a high level signal.

8. The method according to claim 6, characterized in that When the delay time of the second delay module in the power control device has passed, the output end of the power control device outputs a low level signal to the power device, including: The low-level pulse signal is converted into a high-level signal through the first NOT gate in the power control device and enters the second delay module. After the delay time of the second delay module, the high-level signal reaches the second NOT gate in the power control device. The high level signal is converted into a low level signal by the second NOT gate and then reaches the input of the NAND gate in the power control device, so that the NAND gate outputs a high level signal; After the high level signal passes through the third NOT gate in the power control device, the output end of the power control device outputs a low level signal.

9. A memory, characterized in that: It comprises a power supply control device as described in any one of claims 1 to 5 above.

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