Gate-to-gate lateral short detection structure in FinFET process

Abstract

The present application relates to a gate-to-gate lateral short detection structure of a fin field effect transistor process. The structure comprises: a fin active region and a shallow trench isolation region are alternately arranged along a first direction; a gate structure is respectively provided in the middle of the fin active region and at both side edges of the fin active region in the first direction, and the gate structure extends along a second direction; a gate structure is respectively provided in the middle of the shallow trench isolation region and at both side edges of the shallow trench isolation region in the first direction, and the gate structure extends along a second direction; the second direction is perpendicular to the first direction; the detection lead comprises a first detection lead, a second detection lead, a third detection lead and a fourth detection lead; the first detection lead leads to a gate structure located in the middle of the shallow trench isolation region, the second detection lead leads to a gate structure located at both side edges of the shallow trench isolation region, the third detection lead leads to a gate structure located at both side edges of the fin active region, and the fourth detection lead leads to a gate structure located in the middle of the fin active region.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor integrated circuit detection, and in particular to a gate-to-gate lateral short detection structure of a fin field effect transistor process. Background Art

[0002] In FinFET semiconductor technology, defect management is crucial to improving the yield of semiconductor devices. However, due to the extremely small size (below nanometer level) and complex three-dimensional structure, defect detection and analysis are often very difficult.

[0003] In the related technology, a test structure (test-key) similar to the real circuit is usually placed on the wafer to monitor the defects in the real circuit during the manufacturing process. However, the free area outside the real circuit is very valuable and limited. How to improve the utilization rate of the test-key and the efficiency of capturing problems has always been a challenge to the design method. In addition, for the lateral short-circuit problem between gates in the FinFET process, it involves many modules such as the gate, fin active area (Fin), source and drain epitaxy (EPI), and the defect generation models vary greatly. At present, the relevant test-key design is not optimized enough, and a single structure cannot effectively detect and analyze various failure modes. It is often necessary to rely on the mutual reference of multiple groups of test-keys to explore the possibility of the problem, which wastes both area and time. Summary of the invention

[0004] The present application provides a gate-to-gate lateral short detection structure of a fin field effect transistor process, which can solve the problem that the gate-to-gate lateral short test structure of the related art wastes both integrated circuit area and detection time.

[0005] In order to solve the technical problem in the background technology, the present application provides a gate-to-gate lateral short detection structure of a fin field effect transistor process, wherein the gate-to-gate lateral short detection structure of the fin field effect transistor process comprises: a shallow trench isolation region, a gate structure, a fin active region and a detection lead;

[0006] The fin-type active area and the shallow trench isolation area are alternately arranged along a first direction;

[0007] A gate structure is respectively provided at the middle of the fin-type active area and at both side edges of the fin-type active area in the first direction, and the gate structure extends along the second direction;

[0008] A gate structure is respectively provided in the middle of the shallow trench isolation region and at both side edges of the shallow trench isolation region in the first direction, and the gate structure extends along the second direction;

[0009] The second direction is perpendicular to the first direction;

[0010] The detection leads include a first detection lead, a second detection lead, a third detection lead and a fourth detection lead;

[0011] The first detection lead leads to a gate structure located in the middle of the shallow trench isolation area, the second detection lead leads to a gate structure located at both side edges of the shallow trench isolation area, the third detection lead leads to a gate structure located at both side edges of the fin-type active area, and the fourth detection lead leads to a gate structure located in the middle of the fin-type active area.

[0012] Optionally, the first detection lead, the second detection lead, the third detection lead and the fourth detection lead all extend along the first direction.

[0013] Optionally, the first detection lead, the second detection lead, the third detection lead and the fourth detection lead are arranged in a spaced relationship from each other in the second direction.

[0014] Optionally, a first contact hole is formed at the intersection of the gate structure located in the middle of the shallow trench isolation region and the first detection lead; the gate structure located in the middle of the shallow trench isolation region and the first detection lead are interconnected through the first contact hole;

[0015] A second contact hole is formed at the intersection of the gate structure located at the edges of both sides of the shallow trench isolation region and the second detection lead; the gate structure located at the edges of both sides of the shallow trench isolation region and the second detection lead are interconnected through the second contact hole;

[0016] A third contact hole is formed at the intersection of the gate structure located at the two side edges of the fin-type active area and the third detection lead; the gate structure located at the two side edges of the fin-type active area and the third detection lead are interconnected through the third contact hole;

[0017] A fourth contact hole is formed at the intersection of the gate structure located in the middle of the fin-type active area and the fourth detection lead; the gate structure located in the middle of the fin-type active area and the fourth detection lead are interconnected through the fourth contact hole.

[0018] Optionally, the fin-type active region includes at least two columns, and the shallow trench isolation region is spaced between two adjacent columns of the fin-type active regions in the first direction.

[0019] Optionally, each column of the fin-type active regions includes a plurality of rows spaced apart from each other in the second direction, and the rows of the fin-type active regions in each column of the fin-type active regions are aligned in a row.

[0020] In order to solve the technical problems described in the background technology, the present application also provides a gate-to-gate lateral short detection structure of a fin field effect transistor process, the gate-to-gate lateral short detection structure of the fin field effect transistor process comprising: a shallow trench isolation region, a gate structure, a fin active region and a detection lead;

[0021] The fin-type active area and the shallow trench isolation area are alternately arranged along a first direction;

[0022] A plurality of gate structures are provided in the middle of the fin-type active area, and a gate structure is provided at both side edges of the fin-type active area in the first direction, respectively, and the gate structure extends along the second direction;

[0023] A gate structure is respectively provided in the middle of the shallow trench isolation region and at both side edges of the shallow trench isolation region in the first direction, and the gate structure extends along the second direction;

[0024] The second direction is perpendicular to the first direction;

[0025] The detection leads include a first detection lead, a second detection lead, a third detection lead and a fourth detection lead;

[0026] The first detection lead leads to a gate structure located in the middle of the shallow trench isolation area, the second detection lead leads to gate structures located at both side edges of the shallow trench isolation area, the third detection lead leads to gate structures located at both side edges of the fin-type active area and at least one gate structure located in the middle of the fin-type active area, and the fourth detection lead leads to a gate structure located in the middle of the fin-type active area and the remaining gate structures located in the middle of the fin-type active area except the gate structure led by the third detection lead.

[0027] Optionally, the first detection lead, the second detection lead, the third detection lead and the fourth detection lead all extend along the first direction.

[0028] Optionally, the first detection lead, the second detection lead, the third detection lead and the fourth detection lead are arranged in a spaced relationship from each other in the second direction.

[0029] Optionally, a first contact hole is formed at the intersection of the gate structure located in the middle of the shallow trench isolation region and the first detection lead; the gate structure located in the middle of the shallow trench isolation region and the first detection lead are interconnected through the first contact hole;

[0030] A second contact hole is formed at the intersection of the gate structure located at the edges of both sides of the shallow trench isolation region and the second detection lead; the gate structure located at the edges of both sides of the shallow trench isolation region and the second detection lead are interconnected through the second contact hole;

[0031] A third contact hole is formed at the intersection of the gate structures at the two side edges of the fin-type active area and the third detection lead, and at the intersection of at least one gate structure located in the middle of the fin-type active area and the third detection lead; the gate structures at the two side edges of the fin-type active area and at least one gate structure located in the middle of the fin-type active area are interconnected with the third detection lead through the third contact hole;

[0032] A fourth contact hole is formed at the intersection of the gate structure located in the middle of the fin-type active area and the fourth detection lead, and at the intersection of the remaining gate structures located in the middle of the fin-type active area except the gate structure led out by the third detection lead and the fourth detection lead; the gate structure located in the middle of the fin-type active area and the remaining gate structures located in the middle of the fin-type active area except the gate structure led out by the third detection lead are interconnected with the fourth detection lead through the fourth contact hole.

[0033] Optionally, any two gate structures led out from the third detection lead are not adjacent to each other, and any two gate structures led out from the fourth detection lead are not adjacent to each other.

[0034] Optionally, the fin-type active region includes at least two columns, and the shallow trench isolation region is spaced between two adjacent columns of the fin-type active regions in the first direction.

[0035] Optionally, each column of the fin-type active regions includes a plurality of rows spaced apart from each other in the second direction, and the rows of the fin-type active regions in each column of the fin-type active regions are aligned in a row.

[0036] The technical solution of the present application includes at least the following advantages: the present application can detect various lateral short-circuit problems between gates by setting up a shallow trench isolation area, a gate structure, a fin-type active area and a detection lead structure on a limited area, which greatly saves the detection area and the time for analyzing the problem. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0038] Figure 1 A schematic diagram of a top view of a gate-to-gate lateral short detection structure of a FinFET process provided by another embodiment of the present application is shown;

[0039] Figure 2A schematic top view of a gate-to-gate lateral short detection structure of a FinFET process provided by another embodiment of the present application is shown. DETAILED DESCRIPTION

[0040] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0041] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0042] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0043] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0044] Figure 1 FIG. 1 is a schematic diagram of a top view of a gate-to-gate lateral short detection structure of a fin field effect transistor process provided by an embodiment of the present application. It should be explained that the active area contact hole lateral short detection structure is composed of a plurality of basic units, the number of which can be set according to requirements, and the structure of each basic unit is as follows: Figure 1 shown.

[0045] from Figure 1 It can be seen from the figure that the gate-to-gate lateral short detection structure of the FinFET process includes: a shallow trench isolation region 110, a gate structure 130, a fin active region 120 and a detection lead.

[0046] The fin-type active area 120 and the shallow trench isolation area 110 are arranged alternately along a first direction. The first direction in this embodiment is Figure 1 As shown in the horizontal direction, the fin active regions 120 in this embodiment have two columns, namely a left column of fin active regions 120 and a right column of fin active regions 120 , and the shallow trench isolation region 110 is spaced between the two columns of fin active regions 120 .

[0047] The gate structure 130 is respectively disposed in the middle of the fin-type active area 120 and at both side edges of the fin-type active area 120 in the first direction, and the gate structure 130 extends along the second direction.

[0048] The middle of the shallow trench isolation region 110 and the two side edges of the shallow trench isolation region 110 in the first direction are respectively provided with a gate structure 130, and the gate structure 130 extends along the second direction. The second direction in this embodiment is Figure 1 In the longitudinal direction shown, the first direction and the second direction are perpendicular.

[0049] The detection leads include a first detection lead Pin1 for leading out a gate structure 130 located in the middle of the shallow trench isolation area 110, a second detection lead Pin2 for leading out a gate structure 130 located at both sides of the shallow trench isolation area 110, a third detection lead Pin3 for leading out a gate structure 130 located at both sides of the fin-type active area 120, and a fourth detection lead Pin4 for leading out a gate structure 130 located in the middle of the fin-type active area 120.

[0050] The first detection lead Pin1, the second detection lead Pin2, the third detection lead Pin3 and the fourth detection lead Pin4 are all along Figure 1 The first detection lead Pin1, the second detection lead Pin2, the third detection lead Pin3 and the fourth detection lead Pin4 are arranged in a first direction. Figure 2 They are arranged spaced apart from each other in the second direction as shown.

[0051] from Figure 1 It can be seen that the left column of fin active areas 120 and the right column of fin active areas 120 each include three rows of fin active areas, which are the first row of fin active areas, the second row of fin active areas, and the third row of fin active areas from top to bottom in the second direction. The rows of fin active areas in the same column are arranged alternately in the second direction, and the same rows of fin active areas in different columns are aligned in the first direction.

[0052] The first detection lead Pin1 is located above the first row of fin-type active areas and forms a first contact hole 141 at the intersection with the gate structure 130 located in the middle of the shallow trench isolation area 110. The first detection lead Pin1 and the gate structure 130 located in the middle of the shallow trench isolation area 110 are interconnected through the first contact hole 141.

[0053] The second detection lead Pin2 is located between the first row of fin-type active areas and the second row of fin-type active areas, and a second contact hole 142 is formed at the intersection of the second detection lead Pin2 and the gate structure 130 located at the edges of both sides of the shallow trench isolation area 110. The second detection lead Pin2 and the gate structure 130 located at the edges of both sides of the shallow trench isolation area 110 are interconnected through the second contact hole 142.

[0054] The third detection lead Pin2 is located between the second row of fin-type active areas and the third row of fin-type active areas, and a third contact hole 143 is formed at the intersection of the third detection lead Pin2 and the gate structure 130 located at the edges of both sides of the fin-type active area 120. The third detection lead Pin2 and the gate structure 130 located at the edges of both sides of the fin-type active area 120 are interconnected through the third contact hole 143.

[0055] The fourth detection lead Pin4 is located under the fourth row of the fin-type active area 120, and a fourth contact hole 144 is formed at the intersection of the fourth detection lead Pin4 and the gate structure 130 located in the middle of the fin-type active area 120. The fourth detection lead Pin4 and the gate structure 130 located in the middle of the fin-type active area 120 are interconnected through the fourth contact hole 144.

[0056] Figure 2 FIG. 1 is a schematic diagram of a top view of a gate-to-gate lateral short detection structure of a fin field effect transistor process according to another embodiment of the present application. It should be explained that the active area contact hole lateral short detection structure is composed of a plurality of basic units, the number of which can be set according to requirements, and the structure of each basic unit is as follows: Figure 2 shown.

[0057] from Figure 2 It can be seen from the figure that the gate-to-gate lateral short detection structure of the FinFET process includes: a shallow trench isolation region 110, a gate structure 130, a fin active region 120 and a detection lead.

[0058] The fin-type active area 120 and the shallow trench isolation area 110 are arranged alternately along a first direction. The first direction in this embodiment is Figure 1As shown in the horizontal direction, the fin active regions 120 in this embodiment have two columns, namely a left column of fin active regions 120 and a right column of fin active regions 120 , and the shallow trench isolation region 110 is spaced between the two columns of fin active regions 120 .

[0059] A gate structure is provided at both side edges of the fin-type active area 120. Figure 2 As shown, the gate structures located at the left and right edges of the fin-type active area 120 are both third gate structures 133 .

[0060] A plurality of gate structures are also provided in the middle between the two side edges of the fin-type active area 120. Figure 2 It can be seen that three gate structures are provided in the middle of the left column fin active area 120 and the middle of the right column fin active area 120 in this embodiment, namely a first gate structure 131 located in the middle, and a second gate structure 132 located between the first gate structure 131 and the left and right third gate structures 133.

[0061] It is understandable that a second gate structure 132 is provided between the first gate structure 131 and the third gate structures 133 on the left and right sides. Both the first gate structure 131 and the second gate structure 132 are gate structures located in the middle of the fin-type active region 120 .

[0062] A gate structure 130 is provided at both side edges of the shallow trench isolation region 110 and between both side edges of the shallow trench isolation region 110, and all the gate structures 130 extend along the second direction. The second direction in this embodiment is Figure 2 In the longitudinal direction shown, the first direction and the second direction are perpendicular.

[0063] The detection leads include a first detection lead Pin1, a second detection lead Pin2, a third detection lead Pin3 and a fourth detection lead Pin4.

[0064] The first detection lead Pin1 leads out the gate structure 130 located in the middle of the shallow trench isolation area 110, the second detection lead Pin2 leads out the gate structure 130 located at the two side edges of the shallow trench isolation area 110, the third detection lead Pin3 leads out the gate structures 130 located at the two side edges of the fin-type active area 120 and at least one gate structure 130 located in the middle of the fin-type active area 120, and the fourth detection lead Pin4 leads out the gate structure 130 located in the middle of the fin-type active area 120 and the remaining gate structures 130 located in the middle of the fin-type active area 120 except the gate structure 130 led out by the third detection lead Pin3.

[0065] from Figure 2It can be seen that the left column of fin active areas 120 and the right column of fin active areas 120 each include three rows of fin active areas 120, which are the first row of fin active areas, the second row of fin active areas, and the third row of fin active areas from top to bottom in the second direction. The rows of fin active areas 120 in the same column are arranged alternately in the second direction, and the same rows of fin active areas 120 in different columns are aligned in the first direction.

[0066] The first detection lead Pin1 is located above the first row of fin-type active areas 120 , and a first contact hole 141 is formed at the intersection of the gate structure 130 located in the middle of the shallow trench isolation area 110 . The first detection lead Pin1 is interconnected with the gate structure 130 located in the middle of the shallow trench isolation area 110 through the first contact hole 141 .

[0067] The second detection lead Pin2 is located between the first row of fin-type active areas 120 and the second row of fin-type active areas 120, and a second contact hole 142 is formed at the intersection of the gate structure 130 located at the edges of both sides of the shallow trench isolation area 110. The second detection lead Pin2 and the gate structure 130 located at the edges of both sides of the shallow trench isolation area 110 are interconnected through the second contact hole 142.

[0068] The third detection lead Pin3 is located between the second row of fin-type active areas 120 and the third row of fin-type active areas 120, and a third contact hole 143 is formed at the intersection with the third gate structure 133 and the intersection with the first gate structure 131. The third detection lead Pin3 and the third gate structure 133 are interconnected through the third contact hole 143, and the third detection lead Pin3 and the first gate structure 131 are interconnected through the third contact hole 143.

[0069] from Figure 2 It can also be seen that any two gate structures led out from the third detection lead Pin3 are not adjacent to each other, and any two gate structures led out from the third detection lead Pin3 are separated by a gate structure led out from other detection leads, that is, the third gate structure 133 led out from the third detection lead Pin3 and the first gate structure 131 are separated by a second gate structure 132, and the second gate structure 132 is led out from the fourth detection lead Pin4.

[0070] Likewise, any two gate structures derived from the fourth detection lead Pin4 are not adjacent to each other. A first gate structure 131 is spaced between two second gate structures 132 derived from the fourth detection lead Pin4.

[0071] It can be used through the following schemes Figure 1 or Figure 2The gate-to-gate lateral short detection structure of the FinFET process shown in the figure detects different failure modes of the following gate-to-gate lateral short problems:

[0072] A short circuit test can be performed by applying a relatively high voltage to any one of the first detection lead Pin1 and the second detection lead Pin2 and a relatively low voltage to the other detection lead. If the short circuit test result shows a short circuit, it is determined that an abnormality occurs at the top of the gate structure 130 located in the shallow trench isolation area 110.

[0073] A short circuit test can be performed by applying a relatively high voltage to any one of the third detection lead Pin3 and the fourth detection lead Pin4 and a relatively low voltage to the other detection lead. If the short circuit test result shows a short circuit, it is determined that an abnormality occurs at the bottom of the gate structure 130 located in the fin-type active area 120.

[0074] A short circuit test can be performed by applying a relatively high voltage to any one of the second detection lead Pin2 and the third detection lead Pin3 and a relatively low voltage to the other detection lead. If the short circuit test result shows a short circuit, it is determined that an abnormality occurs at the edge of the fin active area 120.

[0075] Figure 1 and Figure 2 The illustrated embodiment can detect various lateral short-circuit problems between gates by setting up a shallow trench isolation area, a gate structure, a fin-type active area and a detection lead structure on a limited area, thereby greatly saving the detection area and the time for analyzing the problem.

[0076] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A gate-to-gate lateral short detection structure for a fin field effect transistor process, characterized in that: The gate-to-gate lateral short detection structure of the Fin field effect transistor process comprises: a shallow trench isolation region, a gate structure, a fin-type active region and a detection lead; The fin-type active area and the shallow trench isolation area are alternately arranged along a first direction; A gate structure is respectively provided at the middle of the fin-type active area and at both side edges of the fin-type active area in the first direction, and the gate structure extends along the second direction; A gate structure is respectively provided in the middle of the shallow trench isolation region and at both side edges of the shallow trench isolation region in the first direction, and the gate structure extends along the second direction; The second direction is perpendicular to the first direction; The detection leads include a first detection lead, a second detection lead, a third detection lead and a fourth detection lead; The first detection lead leads to a gate structure located in the middle of the shallow trench isolation area, the second detection lead leads to a gate structure located at both side edges of the shallow trench isolation area, the third detection lead leads to a gate structure located at both side edges of the fin-type active area, and the fourth detection lead leads to a gate structure located in the middle of the fin-type active area.

2. The gate-to-gate lateral short detection structure of the FinFET process according to claim 1, wherein: The first detection lead, the second detection lead, the third detection lead and the fourth detection lead all extend along the first direction.

3. The gate-to-gate lateral short detection structure of the FinFET process according to claim 1, wherein: The first detection lead, the second detection lead, the third detection lead and the fourth detection lead are arranged in intervals with each other in the second direction.

4. The gate-to-gate lateral short detection structure of the FinFET process according to claim 1, wherein: A first contact hole is formed at the intersection of the gate structure located in the middle of the shallow trench isolation region and the first detection lead; the gate structure located in the middle of the shallow trench isolation region and the first detection lead are interconnected through the first contact hole; A second contact hole is formed at the intersection of the gate structure located at the edges of both sides of the shallow trench isolation region and the second detection lead; the gate structure located at the edges of both sides of the shallow trench isolation region and the second detection lead are interconnected through the second contact hole; A third contact hole is formed at the intersection of the gate structure located at the two side edges of the fin-type active area and the third detection lead; the gate structure located at the two side edges of the fin-type active area and the third detection lead are interconnected through the third contact hole; A fourth contact hole is formed at the intersection of the gate structure located in the middle of the fin-type active area and the fourth detection lead; the gate structure located in the middle of the fin-type active area and the fourth detection lead are interconnected through the fourth contact hole.

5. The gate-to-gate lateral short detection structure of the FinFET process according to claim 1, wherein: The fin-type active region includes at least two columns, and the shallow trench isolation region is spaced between two adjacent columns of the fin-type active regions in the first direction.

6. The gate-to-gate lateral short detection structure of the FinFET process according to claim 5, characterized in that: Each column of the fin-type active regions includes a plurality of rows spaced apart from each other in the second direction, and the rows of the fin-type active regions in each column of the fin-type active regions are aligned in a row.

7. A gate-to-gate lateral short detection structure for a fin field effect transistor process, characterized in that: The gate-to-gate lateral short detection structure of the Fin field effect transistor process comprises: a shallow trench isolation region, a gate structure, a fin-type active region and a detection lead; The fin-type active area and the shallow trench isolation area are alternately arranged along a first direction; A plurality of gate structures are provided in the middle of the fin-type active area, and a gate structure is provided at both side edges of the fin-type active area in the first direction, respectively, and the gate structure extends along the second direction; A gate structure is respectively provided in the middle of the shallow trench isolation region and at both side edges of the shallow trench isolation region in the first direction, and the gate structure extends along the second direction; The second direction is perpendicular to the first direction; The detection leads include a first detection lead, a second detection lead, a third detection lead and a fourth detection lead; The first detection lead leads to a gate structure located in the middle of the shallow trench isolation area, the second detection lead leads to a gate structure located at both side edges of the shallow trench isolation area, the third detection lead leads to gate structures located at both side edges of the fin-type active area and at least one gate structure located in the middle of the fin-type active area, and the fourth detection lead leads to a gate structure located in the middle of the fin-type active area and the remaining gate structures located in the middle of the fin-type active area except the gate structure led by the third detection lead.

8. The gate-to-gate lateral short detection structure of the FinFET process according to claim 7, wherein: The first detection lead, the second detection lead, the third detection lead and the fourth detection lead all extend along the first direction.

9. The gate-to-gate lateral short detection structure of the FinFET process according to claim 7, wherein: The first detection lead, the second detection lead, the third detection lead and the fourth detection lead are arranged in intervals with each other in the second direction.

10. The gate-to-gate lateral short detection structure of the FinFET process according to claim 7, wherein: A first contact hole is formed at the intersection of the gate structure located in the middle of the shallow trench isolation region and the first detection lead; the gate structure located in the middle of the shallow trench isolation region and the first detection lead are interconnected through the first contact hole; A second contact hole is formed at the intersection of the gate structure located at the edges of both sides of the shallow trench isolation region and the second detection lead; the gate structure located at the edges of both sides of the shallow trench isolation region and the second detection lead are interconnected through the second contact hole; A third contact hole is formed at the intersection of the gate structures at the two side edges of the fin-type active area and the third detection lead, and at the intersection of at least one gate structure located in the middle of the fin-type active area and the third detection lead; the gate structures at the two side edges of the fin-type active area and at least one gate structure located in the middle of the fin-type active area are interconnected with the third detection lead through the third contact hole; A fourth contact hole is formed at the intersection of the gate structure located in the middle of the fin-type active area and the fourth detection lead, and at the intersection of the remaining gate structures located in the middle of the fin-type active area except the gate structure led out from the third detection lead and the fourth detection lead; the gate structure located in the middle of the fin-type active area and the remaining gate structures located in the middle of the fin-type active area except the gate structure led out from the third detection lead are interconnected with the fourth detection lead through the fourth contact hole.

11. The gate-to-gate lateral short detection structure of the FinFET process according to claim 7, wherein: Any two gate structures led out from the third detection lead are not adjacent to each other, and any two gate structures led out from the fourth detection lead are not adjacent to each other.

12. The gate-to-gate lateral short detection structure of the FinFET process according to claim 7, wherein: The fin-type active region includes at least two columns, and the shallow trench isolation region is spaced between two adjacent columns of the fin-type active regions in the first direction.

13. The gate-to-gate lateral short detection structure of the FinFET process according to claim 12, wherein: Each column of the fin-type active regions includes a plurality of rows spaced apart from each other in the second direction, and the rows of the fin-type active regions in each column of the fin-type active regions are aligned in a row.

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