Scalable high-voltage control circuits using thin-film electronics

Abstract

The present invention is entitled "Scalable High Voltage Control Circuit Using Thin Film Electronics". The present disclosure relates to a device including a first stage having a first optical switch, a first transistor connected to the first optical switch, and a second transistor connected to the first optical switch and the first transistor. The device also includes a second stage having a second optical switch, a third transistor connected to the second transistor and the second optical switch, and a fourth transistor connected to the second transistor, the second optical switch, and the third transistor.

Description

Technical Field

[0001] The present teachings relate generally to microelectromechanical systems (MEMS), and more particularly to a high voltage switching device for driving a MEMS actuator. Background Art

[0002] MEMS are small (e.g., microscopic) systems, specifically systems with moving parts. MEMS are made of components with sizes between 1 micron and 100 microns (μm), and the size of MEMS is usually in the range of 20 microns to 1 millimeter (mm). MEMS usually include a central unit (e.g., a microprocessor) that processes data and several components 1148 that interact with the surrounding environment (e.g., microsensors). Due to the large surface area to volume ratio of MEMS, the forces generated by environmental electromagnetism (e.g., electrostatic charge and magnetic torque) and fluid dynamics (e.g., surface tension and viscosity) are more relevant design considerations than with larger-scale mechanical devices.

[0003] MEMS typically use electrostatic actuation, piezoelectric actuation, or thermal actuation. Electrostatic actuation scales down to smaller sizes better than electromagnetic actuation and thermal actuation. However, electrostatic actuation typically relies on higher voltages (e.g., several kV) than electromagnetic actuation and thermal actuation to generate sufficient output. Generating and controlling such high voltages in microelectronic devices with comparable actuator size and weight is a challenge. Summary of the invention

[0004] A brief summary of the invention is provided below to provide a basic understanding of some aspects of one or more embodiments of the present teaching. This summary of the invention is not a comprehensive overview, nor is it intended to identify the key or important elements of the present teaching, nor is it intended to describe the scope of the present disclosure. On the contrary, its main purpose is merely to present one or more concepts in a simplified form as a preface to the specific embodiments presented later.

[0005] A device is disclosed. The device includes a first stage having a first optical switch, a first transistor connected to the first optical switch, and a second transistor connected to the first optical switch and the first transistor. The device also includes a second stage having a second optical switch, a third transistor connected to the second transistor and the second optical switch, and a fourth transistor connected to the second transistor, the second optical switch, and the third transistor.

[0006] A switching device for driving an actuator is disclosed. The switching device includes a first stage. The first stage includes a first photodiode. The first stage also includes a first transistor having a source, a gate, and a drain. The source and the gate of the first transistor are connected to each other, and the drain of the first transistor is connected to the first photodiode. The first stage also includes a second transistor having a source, a gate, and a drain. The source of the second transistor is connected to the source and the gate of the first transistor. The gate of the second transistor is connected to the first photodiode and the drain of the first transistor. The drain of the second transistor is connected to the first photodiode. The switching device also includes a second stage. The second stage includes a second photodiode. The second stage also includes a third transistor having a source, a gate, and a drain. The source and the gate of the third transistor are connected to each other and to the drain of the second transistor, and the drain of the third transistor is connected to the second photodiode. The second stage also includes a fourth transistor having a source, a gate, and a drain. The source of the fourth transistor is connected to the drain of the second transistor and to the source and the gate of the third transistor. The gate of the fourth transistor is connected to the second photodiode and the drain of the third transistor. The drain of the fourth transistor is connected to the second photodiode.

[0007] A high voltage switch device for driving a microelectromechanical system (MEMS) actuator is disclosed. The switch device includes a first stage. The first stage includes a first photodiode having a semiconductor, the semiconductor having a first terminal contact and a second terminal contact. The semiconductor includes hydrogenated amorphous silicon (a-Si:H). The first terminal contact and the second terminal contact form a Schottky barrier of the semiconductor. The first stage also includes a first transistor having a source, a gate, and a drain. The source and the gate of the first transistor are connected to each other. The drain of the first transistor is connected to the first terminal contact of the first photodiode. The first transistor has a W / L ratio of about 0.1 to about 0.01. The first stage also includes a second transistor having a source, a gate, and a drain. The source of the second transistor is connected to the source and the gate of the first transistor. The gate of the second transistor is connected to the first terminal contact of the first photodiode and the drain of the first transistor. The drain of the second transistor is connected to the second terminal contact of the first photodiode. The switch device also includes a second stage. The second stage includes a second photodiode. The second stage also includes a third transistor having a source, a gate, and a drain. The source and the gate of the third transistor are connected to each other and to the drain of the second transistor. The drain of the third transistor is connected to a second photodiode. The second stage also includes a fourth transistor having a source, a gate and a drain. The source of the fourth transistor is connected to the drain of the second transistor and to the source and gate of the third transistor. The gate of the fourth transistor is connected to the second photodiode and the drain of the third transistor. The drain of the fourth transistor is connected to the second photodiode. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present teachings and, together with the description, serve to explain the principles of the present disclosure. In the drawings:

[0009] Figure 1 Depicted is a schematic diagram of a high voltage switch device for driving a MEMS actuator according to one embodiment.

[0010] Figure 2 Depicted is a Figure 1 An enlarged view of a portion of.

[0011] Figure 3 A circuit diagram of a first stage of an apparatus according to one embodiment is depicted.

[0012] Figure 4 Depicted is a circuit diagram of multiple (eg, 4) levels of devices stacked together according to one embodiment.

[0013] Figure 5Depicted is a schematic cross-sectional side view of a portion of a first stage of an apparatus according to one embodiment.

[0014] Figure 6 Depicted is a graph showing current and voltage characteristics of a first stage of a device according to one embodiment.

[0015] Figure 7 Depicted are graphs showing current and voltage characteristics of multiple stacked and / or cascaded stages (eg, four stages) of a device according to one embodiment.

[0016] Figure 8 Depicted is a schematic cross-sectional side view of a portion of a first stage of an apparatus according to one embodiment.

[0017] Fig. 9 Depicted are graphs showing current and voltage characteristics of an optical switch of a device when an n+ doped a-Si:H layer is at least partially positioned between the S / D metal layer and the channel, according to one embodiment.

[0018] Fig.10 Depicted is a diagram showing when the S / D metal layer is at least partially positioned on (ie, in direct contact with) the channel according to one embodiment (eg, Figure 8 ), a graph of the current and voltage characteristics of the optical switch.

[0019] Fig.11 Depicted is a schematic diagram of another high voltage switch device for driving a MEMS actuator according to one embodiment.

[0020] Fig.12 Depicted is a Fig.11 The enlarged part.

[0021] Fig.13 Depicted is a Fig.11 Schematic cross-sectional side view of a portion of the device shown in .

[0022] Fig.14 Depicted is a diagram showing a Fig.11 Figure 4 shows the transfer characteristics of the device. DETAILED DESCRIPTION

[0023] Reference will now be made in detail to exemplary implementations of the present teachings, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same, similar or like parts.

[0024] The present disclosure relates to micro-electromechanical systems (MEMS). A first embodiment of the MEMS may be or include an optical coupler (also referred to as an optocoupler). The optical coupler approach simplifies the interface and separation to a low voltage control circuit. The optical coupler approach may also cascade (e.g., stack) multiple stages to increase the rated voltage. The optical coupler approach may have reduced energy efficiency because a light source is required to turn the device on and off. A second embodiment of the MEMS may be or include a two-stage inverter / buffer transistor structure in which an inverter thin film transistor (TFT) and a buffer TFT are tightly integrated at the sub-device level. Such tight integration helps to evenly distribute high voltage over the drain region of the buffer TFT so that a high rated voltage can be achieved.

[0025] High voltage (HiV)-TFTs based on hydrogenated amorphous silicon (a-Si:H), in particular the "offset gate" TFT architecture, can provide 200V-500V or 300V-400V operating voltages. The offset gate TFT architecture can have a gateless drift channel region that provides one or more semiconductor segments to distribute the high voltage over the gateless region to prevent any turn-off process due to high electric fields. The length of the gateless region can be scaled to maintain the same electric field with an arbitrary voltage (e.g., E=V / L). In one example, an 800V HiV-TFT can be built based on this design.

[0026] However, in order to scale voltages above 800V, this approach becomes increasingly inefficient. It is difficult to keep the high voltage evenly distributed over the gate-free area so that it is not locally concentrated to cause an uncontrolled breakdown process. In addition, having a longer gate-free area may have a negative impact on the on-current. The gate-free channel is naturally "resistive". For the same channel width, the on-current of a TFT with a long gate-free channel can be small. Enlarging the length of the gate-free channel may cause the on / off ratio to decrease rapidly. An 800V HiV-TFT can have an on / off ratio of about 3-4 orders of magnitude. The fundamental difficulty of a scalable high-voltage driver with a reliable way of implementing a wide range of desired voltages is to prevent the high voltage from focusing on a small area of ​​the channel material or device, which will cause an uncontrolled breakdown process.

[0027] Multiple discrete transistors can be cascaded to extend the operating voltage range. However, implementing the circuit in a TFT is a challenge and has not been done before. There are several differences between using discrete devices and the TFT process. In the a-Si:H TFT process, only N-type metal oxide semiconductor (NMOS) active devices are available. There are no P-type metal oxide semiconductor (PMOS) or bipolar devices available. Resistors have a limited range in the a-Si:H TFT process and are generally considered an inefficient use of the actual footprint of the layout. Support subcircuits to provide multiple voltage rails to control the gates of the cascaded transistor array are generally not available because they are typically complex DC-DC converters that are beyond the capabilities of the TFT circuit.

[0028] Figure 1 A schematic diagram of a high voltage switch device 100 for driving a MEMS actuator is depicted, and Figure 2 Depicted is a Figure 1 1. An enlarged view of a portion of the device 100. The device 100 may include one or more optical switches (ten are shown: 110A-110J). The optical switches 110A-110J may be or include photodiodes (e.g., semiconductor diodes) that convert light into current. In one embodiment, the semiconductor may be or include a-Si:H. The semiconductors may each include two terminal contacts. The terminal contacts may form a Schottky barrier for the semiconductor. The terminal contact material may be or include TiW, MoCr, Mo, ITO, or a combination thereof.

[0029] The device 100 may also include one or more first transistors (ten are shown: 120A-120J). The first transistors 120A-120J may be or include TFTs. The first transistors 120A, 120J may be long and narrow to provide a discharge path for the gate of the second transistor (which is introduced and described below). For example, the first transistors 120A-120J may have a length of about 20 μm to about 500 μm, and a width of about 3 μm to about 10 μm.

[0030] Each of the first transistors 120A-120J may include a source 122A, a gate 124A, and a drain 124A. Each of the first transistors 120A-120J may be connected to a corresponding one of the optical switches 110A-110J, as described in more detail below. For example, the first transistor 120A may be connected to the optical switch 110A, the first transistor 120B may be connected to the optical switch 110B, and so on. The first transistors 120A-120J may have a W / L ratio less than 1. For example, the W / L ratio may be about 0.1 to about 0.01.

[0031] The device 100 may also include one or more second transistors (ten are shown: 140A-140J). The second transistors 140A-140J may be or include HiV-TFTs. More specifically, the second transistors 140A-140J may be configured to operate at a higher voltage than the first transistors 120A-120J. For example, the rated voltage of the first transistors 120A-120J may be about 10V to about 100V (e.g., 20V), and the rated voltage of the second transistors 140A-140J may be about 200V to about 1000V (e.g., 400V). The second transistors 140A-140J may be shorter and wider / thicker than the first transistors 120A-120J. For example, the second transistors 140A-140J may have a length of about 3μm to about 10μm, and a width of about 10μm to about 1000μm.

[0032] Each of the second transistors 140A-140J may include a source 142A, a gate 144A, and a drain 144A. Each of the second transistors 140A-140J may be connected to a corresponding one of the optical switches 110A-110J and to a corresponding one of the first transistors 120A-120J. For example, the second transistor 140A may be connected to the optical switch 110A and to the first transistor 120A, the second transistor 140B may be connected to the optical switch 110B and to the first transistor 120B, and so on. The gates 144A-144J of the second transistors 140A-140B may be controlled by the optical switches 110A-110J. For example, each of the second transistors (e.g., 140A) can be controlled using a corresponding one of the optical switches (e.g., 110A) and / or a corresponding one of the first transistors (e.g., 120A), which causes the gate (e.g., 144A) of the second transistor (e.g., 140A) to be at the same potential as the source (e.g., 142A) of the second transistor (e.g., 140A). This may cause the second transistor (e.g., 140A) to be in a closed state when the optical switch 110A is not illuminated.

[0033] The optical switch 110A, the first transistor 120A, and the second transistor 120A can form a first stage of the device 100, the optical switch 110B, the first transistor 120B, and the second transistor 120B can form a second stage of the device 100, and so on. Thus, the device 100 can include multiple (e.g., 10) stages that are stacked and / or cascaded, which can help the device 100 achieve a higher (e.g., 10 times) operable voltage range than a single TFT can handle / withstand. For example, the optical switches 110A-110J and the second transistors 140A-140J can be cascaded and connected in series to expand the operating voltage range of the device 100.

[0034] The device 100 may also include one or more pads (two are shown: 150A, 150B). The pads 150A, 150B may be metal pads configured for probing using a probe station. The first pad 150A may be connected to the first stage (e.g., to the first transistor 120A and / or the second transistor 140A). The second pad 150B may be connected to the last (e.g., tenth) stage (e.g., to the first transistor 120J and / or the second transistor 140J).

[0035] Device 100 may also include one or more pads (ten are shown: 160A-160J). First pad 160A may be connected to a first stage (e.g., to first transistor 120A and / or second transistor 140A), second pad 160B may be connected to a second stage (e.g., to first transistor 120B and / or second transistor 140B), and so on.

[0036] To turn on the device 100, a light source (e.g., an LED controlled by a low voltage control circuit) illuminates the optical switch 110A-110J, which induces a photocurrent and biases the gate potential of the second transistor 140A-140J toward the drain voltage. This causes the second transistor 140A-140J to turn on. The first transistor 120A-120J can act as a load for the optical switch 110A-110J. A predetermined resistance is required to induce a sufficient gate voltage by the photocurrent, which actuates the second transistor 140A-140J to a conducting state.

[0037] Figure 3 A circuit diagram of a first stage of the device 100 according to one embodiment is depicted. As described above, the first transistor 120A may include a source 122A, a gate 124A, and a drain 126A, and the second transistor 140A may include a source 142A, a gate 144A, and a drain 146A. The drain 126A of the first transistor 120A may be connected to a first side of the optical switch 110A and to a gate 144A of the second transistor 140A. The source 122A of the first transistor 120A may be connected to the gate 124A of the first transistor 120A and to the source 142A of the second transistor 140A (e.g., at a common node 170A). The drain 146A of the second transistor 140A may be connected to a second side of the optical switch 110A.

[0038] Figure 4A circuit diagram 400 of multiple (e.g., 4) stages of stacked devices 100 according to one embodiment is depicted. As shown, the optical switch 110A of the first stage and the drain 146A of the second transistor 140A can be connected to the common node 170B of the second stage, the optical switch 110B of the second stage and the drain 146B of the second transistor 140B can be connected to the common node 170C of the third stage, and the optical switch 110C of the third stage and the drain 146C of the second transistor 140C can be connected to the common node 170D of the fourth stage. The optical switches 110A-110D can be closely positioned together into the illuminated area to ensure light utilization and uniformity of illumination. The optical switches 110A-110D can be grouped together and controlled by one (or more) light sources, which are actuated by low voltage electronics.

[0039] Figure 5 A schematic cross-sectional side view of a portion of a first stage of a device 100 according to one embodiment is depicted. The first stage can be formed using a back channel etch stop a-Si:H TFT process. The first stage can include a gate dielectric layer (also referred to as a bottom nitride layer) 510, an interlayer dielectric (ILD) layer 512 positioned on the gate dielectric layer 510, and a (top) passivation layer 514 positioned on the ILD layer 512.

[0040] The first stage may also include an optical switch 110A, a first transistor 120A ( Figure 5 512 and the second transistor 140A. The optical switch 110A may be at least partially positioned within the ILD layer 512 and / or the passivation layer 514. The optical switch 110A may be implemented on an S / D metal layer (six portions are shown: 120A-120F). As shown, a first side of the optical switch 110A may be implemented on a first portion of the S / D metal layer 520A, and a second side of the optical switch 110A may be implemented on a second portion of the S / D metal layer 520B. The first and second portions of the S / D metal layers 520A, 520B may be positioned within the ILD layer 512. The first and second portions of the S / D metal layers 520A, 520B may be separated from each other (i.e., a portion of the ILD layer 512 may be positioned between the first and second portions). The second portion of the S / D metal layer 520B may be connected to a third portion of the S / D metal layer 520C, which may be at least partially positioned within the gate dielectric layer 510. A third portion of the S / D metal layer 520C may be positioned on and / or connected to the field plate 522, which is positioned within the gate dielectric layer 510. A third portion of the S / D metal layer 520C may be connected to a fourth portion of the S / D metal layer 520D, which is positioned in the ILD layer 512.

[0041] The n+ doped a-Si:H layer (five portions are shown: 524A-524E) may be at least partially positioned within the ILD layer 512. As shown, a first portion of the S / D metal layer 520A may be at least partially positioned on a first portion of the n+ doped a-Si:H layer 524A, a second portion of the S / D metal layer 520B may be at least partially positioned on a second portion of the n+ doped a-Si:H layer 524B, and a fourth portion of the S / D metal layer 520D may be at least partially positioned on a third portion of the n+ doped a-Si:H layer 524C.

[0042] The second transistor 140A may include a source 142A, a gate 144A, and a drain 146A. The second transistor 140A may also include a field plate 530 that is offset from the gate 144A within the gate dielectric layer 510. The field plate 530 may be positioned between the gate 144A and the drain 146A. A gateless channel (e.g., an offset region) 532 may be positioned within the gate dielectric layer 510. The gateless channel 532 may be positioned between the gate 144A and the field plate 530. The gateless channel 532 may also or alternatively be positioned between the gate 144A and the drain 146A. The field plate 530 and / or the gateless channel region 532 may be positioned near the drain 146A to extend the volt S / D operating range of about 10 seconds to a few hundred volt operating range. This is unique to the offset gate HiV-TFT architecture.

[0043] The second transistor 140A may also include a fifth portion and a sixth portion of the S / D metal layers 520E, 520F. The fifth portion and the sixth portion of the S / D metal layers 520E, 520F may be positioned within the ILD layer 512. The fifth portion and the sixth portion of the S / D metal layers 520E, 520F may be spaced apart from each other (i.e., a portion of the ILD layer 512 may be positioned between the fifth portion and the sixth portion). The fifth portion and the sixth portion of the S / D metal layers 520E, 520F may have a stepped profile such that as they move closer toward each other, they each move closer to the passivation layer 514.

[0044] The second transistor 140A may also include a fourth portion and a fifth portion of the n+ doped a-Si:H layer 524D, 524E. The fourth portion and the fifth portion of the n+ doped a-Si:H layer 524D, 524E may be positioned within the ILD layer 512. The fourth portion and the fifth portion of the n+ doped a-Si:H layer 524D, 524E may be separated from each other (i.e., a portion of the ILD layer 512 may be positioned between the fourth portion and the fifth portion). The fourth portion and the fifth portion of the n+ doped a-Si:H layer 524D, 524E may have a stepped profile such that as they move closer toward each other, they each move closer to the passivation layer 514.

[0045] The second transistor 140A may further include a channel 540 (e.g., including a-Si:H) and a top nitride (T.Nit.) layer 542. The channel 540 may be positioned on the gate dielectric layer 510 and / or within the ILD layer 512. The channel 540 may be at least partially positioned between the fourth and fifth portions of the n+ doped a-Si:H layers 524D, 524E. The top nitride layer 542 may be positioned on the channel 540. The top nitride layer 542 may be at least partially positioned between the fourth and fifth portions of the n+ doped a-Si:H layers 524D, 524E. The channel 540 may have a greater width than the top nitride layer 542.

[0046] The source 142A may include at least a portion of the sixth portion of the S / D metal layer 520F, the fifth portion of the n+ doped a-Si:H layer 524E, the channel 540, and the top nitride layer 542. The drain 146A may include at least a portion of the fifth portion of the S / D metal layer 520E, the fourth portion of the n+ doped a-Si:H layer 524D, the channel 540, and the top nitride layer 542. The channel 540 and the top nitride layer 542 may be at least partially positioned between the source 142A and the drain 146.

[0047] In one embodiment, the separated a-Si:H layer 520 of the optical switch 110A can be implemented in the same a-Si:H channel material. However, process modifications are required to ensure that the optical switch 110A has a predetermined on / off ratio. This alternative implantation will be discussed later.

[0048] Figure 6 depicts a graph 600 showing current and voltage characteristics of a first stage of the apparatus 100 according to one embodiment, and Figure 7A graph 700 showing current and voltage characteristics of multiple stacked and / or cascaded stages (e.g., four stages) of the device 100 is depicted. Both graphs 600, 700 show one curve for a first (e.g., on) state of the device 100 and another curve for a second (e.g., off) state of the device 100. It can be seen that when the device 100 has four stages, the device 100 can generate 4 times the voltage when compared to when the device 100 has a single stage. For example, the single-stage embodiment operates at up to about 300V, and the multi-stage embodiment operates at up to about 1200V. The current limit of the single-stage embodiment is set to 20μA, and the current limit of the multi-stage embodiment is set to 50μA. For both the single-stage embodiment and the multi-stage embodiment, on / off ratios of more than 6 orders of magnitude are demonstrated.

[0049] Figure 8 A schematic cross-sectional side view of a portion of a first stage of apparatus 100 is depicted according to one embodiment. Figure 8 The implementation scheme in Figure 5 In this embodiment, the first level may include a gate dielectric layer 510 and an interlayer dielectric (ILD) layer 512 positioned on the gate dielectric layer 510. The (top) passivation layer 514 may optionally be omitted.

[0050] The optical switch 110A may include two portions of S / D metal layers 820A, 820B. The portions of the S / D metal layers 820A, 820B may have a stepped profile so that as they move closer toward each other, they each travel farther from the gate dielectric layer 510. The optical switch 110A may also include a channel 840 (e.g., including a-Si:H) and a top nitride layer 842. The channel 840 may be positioned on the gate dielectric layer 510 and / or within the ILD layer 512. The channel 840 may be at least partially positioned between the portions of the S / D metal layers 820A, 820B. The top nitride layer 842 may be positioned on the channel 840. The top nitride layer 842 may be at least partially positioned between the portions of the S / D metal layers 820A, 820B.

[0051] As described above, the optical switch 110A and the second transistor 140A can share the same a-Si:H material layer, which can simplify the layer structure and process. As shown, because the optical switch 110A is a two-terminal device, unless the optical switch 110A does not include a gate, the second transistor 140A (shown on the left) and the optical switch 110A (shown on the right) share almost the same structure. In addition, there is no n+ doped a-Si:H layer between the S / D metal layers 820A, 820B and the channel 840. Compared with the conventional a-Si:HTFT process, this structure may require additional steps to build, which assumes that the S / D metal and n+, a-Si:H are patterned in one step and share the same mask pattern.

[0052] However, Fig. 9 and Fig.10 The importance of using different contact structures for the optical switch 110A and the second transistor 140A, respectively, is shown.

[0053] Fig. 9 A graph 900 is depicted showing current and voltage characteristics of an optical switch 110A when an n+ doped a-Si:H layer is at least partially positioned between the S / D metal layer and the channel, according to one embodiment. More specifically, Fig. 9 Shown with Figure 8 The optical switch 110A shown on the right side of FIG. 1 has current and voltage characteristics of an optical switch of similar structure, except that the n+ doped a-Si:H layer is positioned between the S / D metal layer and the channel, similar to Figure 8 The second transistor 140A is shown on the left. The on / off ratio of this device is less than 10, which is poor.

[0054] Fig.10 Depicted is a diagram showing when the S / D metal layers 820A, 820B are at least partially positioned on (ie, in direct contact with) the channel 840 according to one embodiment (eg, Figure 8 ), a graph 1000 of current and voltage characteristics of the optical switch 110A. The on / off ratio is improved by more than 2 orders of magnitude to greater than 1000. Similarly, without the n+ doped a-Si:H layer for the second transistor 140A, the second transistor 140A can have a very small on-current.

[0055] Fig.11 A schematic diagram of another high voltage switch device 1100 for driving a MEMS actuator is depicted, and Fig.12 Depicted is a Fig.11 Device 1100 may be or include an all-electric implant. Fig.11 The device 1100 shown in FIG. Figure 1-10One difference between the described devices 100 is that Fig.11 The device 1100 in can directly scale up to a KV range.

[0056] Device 1100 may be or include a composite device. Device 1100 may include one or more transistors (two are shown: 1120, 1140). The first (e.g., upper) transistor 1120 may be or include a TFT. For example, the first transistor 1120 may be or include a HiV-TFT having a source 1122, a gate 1124, and a drain 1126. The first transistor 1120 may be long and narrow. For example, the first transistor 1120 may have a length of about 20 μm to about 1000 μm, and a width / thickness of about 3 μm to about 20 μm. The first transistor 1120 may be used as an inverter (e.g., a first-stage inverter). In the embodiment shown, there is no load resistor for the first transistor 1120, which is different from a conventional inverter circuit.

[0057] The device 1100 can be actuated between a first (e.g., off) state and a second (e.g., on) state. When the gate 1124 turns off the first transistor 1120, the device 1100 can be in an off (e.g., low current) state. When the gate 1124 turns on the first transistor 1120, the device 1100 can be in an on (e.g., higher current) state.

[0058] The second (e.g., lower) transistor 1140 may also be or include a TFT. For example, the second transistor 1140 may be or include a HiV-TFT having a source 1242, a gate 1144, and a drain 1146. The second transistor 1140 may be wider than the first transistor 1120. For example, the width of the second transistor 1140 may have a width of about 20 μm to about 1000 mm. The second transistor 1140 may be used as a driver and / or output transistor.

[0059] Sources 1122, 1142 may be connected (e.g., by metal); however, sources 1122, 1142 may not be shared (e.g., their semiconductor channels may be separated). Similarly, drains 1126, 1146 may be connected (e.g., by metal); however, drains 1126, 1146 may not be shared (e.g., their semiconductor channels may be separated). The subcomponents of transistors 1120, 1140 are tightly coupled, so that device 1100 is not a conventional inverter + output transistor. Instead, device 1100 is a composite three-terminal device with a source, a gate, and a drain.

[0060] The first transistor 1120 may include one or more tap electrodes (five are shown: 1130A-1130E). The electrodes 1130A-1130E may be distributed over a high voltage drive region of a gateless channel (also referred to as a gateless drift region) 1132 of the first transistor 1120. The electrodes 1130A-1130E of the first transistor 1120 may be at least partially positioned between the gate 1124 and the drain 1126. One of the electrodes 1130A may be connected to the gate 1144 of the second transistor 1140.

[0061] The second transistor 1140 may include one or more field plates (five are shown: 1148A-1148E). The gate 1144 and field plates 1148A-1148E of the second transistor 1140 may be connected (e.g., directly) to the electrodes 1130A-1130E of the first transistor 1120. The field plates 1148A-1148E may be at least partially positioned between the gate 1144 and one or more drains 1126, 1146. The field plates 1148A-1148E may distribute the high voltage substantially evenly over the gateless channel (also referred to as the gateless drift region) 1152 of the second transistor 1140, which may reduce and / or prevent premature breakdown. As shown, the gateless channels 1132, 1152 may be at least partially positioned between the one or more gates 1124, 1144 and the one or more drains 1126, 1146. The operating voltage range of the device 1100 may be extended by increasing the number of electrodes 1130A- 1130E of the first transistor 1120 and / or increasing the number of field plates 1148A- 1148E of the second transistor 1140 .

[0062] The source 1122, 1142, the gate 1144, the drain 1126, 1146, the electrodes 1130A-1130E, or a combination thereof may be made of a first material (e.g., S / D metal). The gate 1124, the field plates 1148A-1148E, or a combination thereof may be made of a second material (e.g., gate metal) different from the first material. The channel 1132, 1152 may be made of a third material (e.g., a:Si:H) different from the first material and the second material.

[0063] like Fig.11 As shown in , the device 1100 can be connected to one or more pads (four are shown: 1160A-1160D). Pads 1160A-1160D can be metal pads configured for probing using a probe station. As shown, pad 1160A can be connected to one or more sources 1122, 1142, pad 1160B can be connected to gate 1144, and pad 1160D can be connected to one or more drains 1126, 1146.

[0064] The first transistor 1120 may have a modified (e.g., unconventional) structure. More specifically, in addition to the source 1122, the gate 1124, and the drain 1126, the first transistor 1120 may also include one or more tapped drains distributed along the gateless drift region 1132 between the gate 1124 and the drain 1126. The tapped drain may be or include a gate 1144 and / or electrodes 1130A-1130E. The tapped drain may be configured to sample the stepped voltage of the second transistor 1140. The tapped drain may also or alternatively be configured to provide a field plate voltage of the second transistor 1140. In one embodiment, the tapped drain may be a field plate for the first transistor 1120. In another embodiment, the tapped drain may not be a field plate for the first transistor 1120.

[0065] In one embodiment, the electrode 1130 can function as a field plate and / or drain of the first transistor 1120. In one embodiment, the gate 1144 can function as a field plate and / or drain of the first transistor 1120. In one embodiment, the electrode 1130 can function as a field plate of the second transistor 1140.

[0066] Fig.13 Depicted is a method of performing a Fig.11 13-13 in FIG. 13 is a schematic cross-sectional side view of a portion of the device 1100 taken along line 13-13. Fig.11 The cross section is shown as being through gate 1144, but the cross section may also or instead be taken through any of electrodes 1130A-1130E.

[0067] The device 1100 may include a first (e.g., lower) metal layer 1310. The first metal layer 1310 may be made of the same type of metal as the gate 1124. The gate dielectric layer 1120 may be at least partially positioned on the first metal layer 1310. The second (e.g., upper) metal layer 1330 may be at least partially positioned on the gate dielectric layer 1120. The second metal layer 1330 may be made of the same type of metal as the drain 1126. In at least one embodiment, the metal layers 1310, 1330 may be made of the same type of metal. In another embodiment, the metal layers 1310, 1330 may be made of different types of metals. The second metal layer 1330 may include one or more legs (two are shown: 1332, 1334) extending at least partially through the gate dielectric layer 1120 toward the first metal layer 1310. In at least one embodiment, the legs 1332, 1334 are positioned on and / or contact the first metal layer 1310.

[0068] Channel 1340 may be at least partially positioned within second metal layer 1330. Channel 1340 may be made of a:Si:H. N+ layer 1350 may be at least partially positioned within second metal layer 1330. N+ layer 1350 may be at least partially positioned on channel 1340 and / or above channel 1340. N+ layer 1350 may be or include an n+ doped a-Si:H layer. Top nitride layer 1360 may be at least partially positioned within second metal layer 1330. Top nitride layer 1360 may be at least partially positioned between channel 1340 and n+ layer 1350. For example, top nitride layer 1360 may be positioned above channel 1340 and below top nitride layer 1360.

[0069] Third metal layer 1370 may be at least partially positioned on and / or over second metal layer 1330 and / or n+ layer 1350. Third metal layer 1370 may be made of the same type of metal as second metal layer 1330. In at least one embodiment, layers 1330, 1370 may be the same layer.

[0070] Fig.14 A graph 1400 showing the transfer characteristics of the device 1100 according to one embodiment is depicted. At low input gate voltage (V g <2V), the device 1100 is in the "on" state with an on-state current >10uA (e.g., device compliance setting). For high gate input voltages (V g >2.5V), the device 1100 is in the "off" state, and the leakage current can be several hundred pA at 1100V. In one embodiment, 1100V can be the highest voltage that the device 1100 can provide. The input voltage can be swept from -5V to 10V, and the S / D drain can be set to the maximum voltage range of the measurement setup (e.g., 1100V). The compliance current is set to 10μA. The device 1100 can achieve 4-5 orders of magnitude on / off.

[0071] Although the numerical ranges and parameters describing the broad scope of the present teachings are approximate, the numerical values ​​given in the specific examples are reported as accurately as possible. However, any numerical value inherently contains certain errors, which are necessarily caused by the standard deviations present in their respective test measurements. In addition, all ranges disclosed herein are understood to cover any and all subranges contained therein. For example, a range of "less than 10" may include any and all subranges between (and including) a minimum value of 0 and a maximum value of 10, i.e., any and all subranges having a minimum value equal to or greater than 0 and a maximum value equal to or less than 10, such as 1 to 5.

[0072] Although the present teaching content has been shown with respect to one or more embodiments, changes and / or modifications can be made to the illustrated examples without departing from the spirit and scope of the appended claims. For example, it should be understood that although the process is described as a series of actions or events, the present teaching content is not limited by the ordering of such actions or events. Some actions may occur in different orders and / or occur simultaneously with other actions or events other than those described herein. In addition, all process stages are not required to implement the method according to one or more aspects or embodiments of the present teaching content. It should be understood that structural objects and / or processing levels can be added, or existing structural objects and / or processing levels can be removed or modified. In addition, one or more of the actions depicted herein can be performed in one or more separate actions and / or stages. In addition, if the term "include", "comprise", "have", "with" or its variant is used in a specific embodiment and claim, such terms are intended to be inclusive in a manner similar to the term "include". The term "at least one of ..." is used to refer to one or more of the items listed that can be selected. In addition, in the discussion and claims herein, the term "on..." used with respect to two materials that are "on" one another means at least some contact between the two materials, while "above..." means that the two materials are close, but there may be one or more additional intermediate materials so that contact is possible but not required. Neither "on..." nor "above..." implies any directionality as used herein. The term "conformal" describes a coating material in which the angle of the underlying material is preserved due to a conformal material. The term "about" indicates that the listed values ​​may be slightly changed, as long as the change does not cause the process or structure to be inconsistent with the embodiment shown. The terms "couple", "coupled", "connect", "connection", "connected", "in connection with", and "connecting" mean "directly connected to..." or "connected to..." via one or more intermediate elements or members. Finally, the terms "exemplary" or "illustrative" indicate that the description is used as an example, rather than implying that it is ideal. Other embodiments of the present teachings may be apparent to those skilled in the art by considering this specification and practicing the disclosure herein. It is intended that the specification and examples be considered exemplary only, with the true scope and spirit of the present teachings being indicated by the following claims.

Claims

1. A device, include: The first level includes: a first optical switch; a first transistor connected to the first optical switch; and a second transistor connected to the first optical switch and the first transistor, wherein the second transistor comprises a source, a gate, and a drain, and wherein the gate of the second transistor is controlled by the first optical switch, and wherein the second transistor comprises: A thin film transistor TFT having a non-gate channel region between a gate and a drain; one or more field plates between the gate and drain; and The second level includes: a second optical switch; a third transistor connected to the second transistor and the second optical switch; and A fourth transistor is connected to the second transistor, the second optical switch and the third transistor.

2. The apparatus of claim 1, wherein the first optical switch comprises a semiconductor having two terminal contacts, wherein the semiconductor comprises hydrogenated amorphous silicon (a-Si:H), and wherein the terminal contacts form a Schottky barrier for the semiconductor. 3 . The device of claim 1 , wherein the first optical switch comprises a semiconductor having two terminal contacts, wherein the semiconductor comprises an organic material, a metal oxide, or a combination thereof.

4. The device of claim 1, wherein the first optical switch and the second optical switch are connected in cascade series with the second transistor and a fourth transistor to extend an operating voltage range of the device.

5. The device according to claim 1, wherein the device further include: a gate dielectric layer; an interlayer dielectric ILD layer, the interlayer dielectric layer being positioned on the gate dielectric layer; and The second transistor comprises: source; Gate; Drain; a first field plate, wherein the gate and the first field plate are at least partially positioned within the gate dielectric layer, and wherein the gate and the first field plate are separated by a gateless channel between the gate and the first field plate; a channel at least partially positioned within the ILD layer and between the source and the drain, wherein the channel comprises hydrogenated amorphous silicon (a-Si:H); and A nitride layer is at least partially positioned within the ILD layer and between the source and the drain, wherein the nitride layer is at least partially positioned on the channel.

6. The device according to claim 5, wherein the first optical switch include: a second field plate positioned within the gate dielectric layer; an n+ doped a-Si:H layer, the n+ doped a-Si:H layer being at least partially positioned within the ILD layer, wherein the n+ doped a-Si:H layer comprises a first portion, a second portion, and a third portion separated from each other; as well as a metal layer, the metal layer being at least partially positioned within the ILD layer, wherein the metal layer comprises: a first portion, the first portion being at least partially positioned on the first portion of the n+ doped a-Si:H layer; a second portion, the second portion being at least partially positioned on the second portion of the n+ doped a-Si:H layer; a third portion, the third portion being at least partially positioned on the third portion of the n+ doped a-Si:H layer; and A fourth portion is at least partially positioned on the second field plate, at least partially located between the second portion and the third portion of the n+ doped a-Si:H layer, and at least partially located between the second portion and the third portion of the metal layer.

7. The device according to claim 5, wherein the first optical switch include: a metal layer positioned at least partially within the ILD layer, wherein the metal layer includes a first portion and a second portion, wherein the first portion and the second portion of the metal layer have a stepped profile; a second channel positioned at least partially within the ILD layer and between the first portion and the second portion of the metal layer, wherein the second channel comprises a-Si:H; as well as A second nitride layer is positioned at least partially within the ILD layer, at least partially between the first portion and the second portion of the metal layer, and at least partially on the second via.

8. A device, include: The first level includes: a first optical switch; a first transistor connected to the first optical switch; and a second transistor connected to the first optical switch and the first transistor, wherein the first transistor is longer and narrower than the second transistor, wherein The first transistor has a W / L ratio of 0.1 to 0.01, and wherein the second transistor is configured to operate at a higher voltage than the first transistor; and The second level includes: a second optical switch; a third transistor connected to the second transistor and the second optical switch; and A fourth transistor is connected to the second transistor, the second optical switch and the third transistor.

9. A switch device for driving an actuator, the switch device include: The first level includes: a first photodiode; a first transistor including a source, a gate, and a drain, wherein the source and the gate of the first transistor are connected to each other, and wherein the drain of the first transistor is connected to the first photodiode; and a second transistor including a source, a gate, and a drain, wherein the source of the second transistor is connected to the source and the gate of the first transistor, wherein the gate of the second transistor is connected to the first photodiode and the drain of the first transistor, and wherein the drain of the second transistor is connected to the first photodiode; and The second level includes: a second photodiode; a third transistor including a source, a gate, and a drain, wherein the source and the gate of the third transistor are connected to each other and to the drain of the second transistor, and wherein the drain of the third transistor is connected to the second photodiode; and a fourth transistor comprising a source, a gate and a drain, wherein the source of the fourth transistor is connected to the drain of the second transistor and to the source and the gate of the third transistor, wherein the gate of the fourth transistor is connected to the second photodiode and the drain of the third transistor, and wherein the drain of the fourth transistor is connected to the second photodiode.

10. The switch device of claim 9, wherein the first transistor is longer and narrower than the second transistor, and wherein the second transistor is configured to operate at a higher voltage than the first transistor. 11 . The switching device according to claim 9 , wherein the second transistor comprises a thin film transistor (TFT), and wherein the gate of the second transistor is controlled by the first photodiode.

12. The switching device of claim 11, wherein the second transistor further comprises a field plate and a gateless channel region positioned between the gate and the drain of the second transistor, and wherein the gateless channel region is positioned between the gate and the field plate of the second transistor.

13. A switching device according to claim 9, wherein the switching device is configured to be actuated into an on state in response to a light source causing an induced photocurrent in the first photodiode and the second photodiode, which biases the gate potential of the second transistor and the fourth transistor toward a drain voltage.

14. A high voltage switch device for driving a micro-electromechanical system (MEMS) actuator, the switch device include: The first level includes: a first photodiode comprising a semiconductor having a first terminal contact and a second terminal contact, wherein the semiconductor comprises hydrogenated amorphous silicon, a-Si:H, and wherein the first terminal contact and the second terminal contact form a Schottky barrier for the semiconductor; a first transistor including a source, a gate, and a drain, wherein the source and the gate of the first transistor are connected to each other, wherein the drain of the first transistor is connected to the first terminal contact of the first photodiode, and wherein the first transistor has a W / L ratio of 0.1 to 0.01; and a second transistor comprising a source, a gate, and a drain, wherein the source of the second transistor is connected to the source and the gate of the first transistor, wherein the gate of the second transistor is connected to the first terminal contact of the first photodiode and the drain of the first transistor, and wherein the drain of the second transistor is connected to the second terminal contact of the first photodiode; and The second level includes: a second photodiode; a third transistor including a source, a gate, and a drain, wherein the source and the gate of the third transistor are connected to each other and to the drain of the second transistor, and wherein the drain of the third transistor is connected to the second photodiode; and a fourth transistor comprising a source, a gate and a drain, wherein the source of the fourth transistor is connected to the drain of the second transistor and to the source and the gate of the third transistor, wherein the gate of the fourth transistor is connected to the second photodiode and the drain of the third transistor, and wherein the drain of the fourth transistor is connected to the second photodiode.

15. The switch device of claim 14, wherein the first transistor is longer and narrower than the second transistor, and wherein the second transistor is configured to operate at a higher voltage than the first transistor.

16. The switch device according to claim 14, further comprising: include: a gate dielectric layer; an interlayer dielectric ILD layer, the interlayer dielectric layer being positioned on the gate dielectric layer; and The second transistor comprises: a first field plate, wherein the gate of the second transistor and the first field plate are at least partially positioned within the gate dielectric layer, and wherein the gate of the second transistor and the first field plate are separated by a gateless channel between the gate and the first field plate; a channel positioned at least partially within the ILD layer and between the source and the drain of the second transistor, wherein the channel comprises hydrogenated amorphous silicon a-Si:H; and A nitride layer is positioned at least partially within the ILD layer and between the source and the drain of the second transistor, wherein the nitride layer is positioned at least partially on the channel.

17. The switching device according to claim 16, wherein the first photodiode include: a second field plate positioned within the gate dielectric layer; an n+ doped a-Si:H layer, the n+ doped a-Si:H layer being at least partially positioned within the ILD layer, wherein the n+ doped a-Si:H layer comprises a first portion, a second portion, and a third portion separated from each other; as well as a metal layer, the metal layer being at least partially positioned within the ILD layer, wherein the metal layer comprises: a first portion, the first portion being at least partially positioned on the first portion of the n+ doped a-Si:H layer; a second portion, the second portion being at least partially positioned on the second portion of the n+ doped a-Si:H layer; a third portion, the third portion being at least partially positioned on the third portion of the n+ doped a-Si:H layer; and A fourth portion is at least partially positioned on the second field plate, at least partially located between the second portion and the third portion of the n+ doped a-Si:H layer, and at least partially located between the second portion and the third portion of the metal layer.

18. The switching device according to claim 16, wherein the first photodiode include: a metal layer positioned at least partially within the ILD layer, wherein the metal layer includes a first portion and a second portion, wherein the first portion and the second portion of the metal layer have a stepped profile; a second channel positioned at least partially within the ILD layer and between the first portion and the second portion of the metal layer, wherein the second channel comprises a-Si:H; as well as A second nitride layer is positioned at least partially within the ILD layer, at least partially between the first portion and the second portion of the metal layer, and at least partially on the second via.

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