A display panel and a method for manufacturing the same

Abstract

The present application provides a display panel and a manufacturing method thereof. The display panel includes: a light-emitting functional layer including a plurality of light-emitting units; a driving backplane including a bonding electrode, and a first barrier layer, a driving circuit layer, and a driving chip that are sequentially stacked in a direction away from the light-emitting functional layer. A plurality of grooves are formed on a side of the first barrier layer facing the light-emitting functional layer; the bonding electrode is received in the groove and electrically connected to the light-emitting unit; the driving chip is located in the display area and is electrically connected to the bonding electrode through a driving circuit in the driving circuit layer. By sequentially forming the bonding electrode, the first barrier layer, the substrate, the driving circuit layer, and the driving chip, a groove for receiving the bonding electrode can be formed on a side of the first barrier layer facing the light-emitting functional layer, and the driving chip can be directly formed on the driving circuit layer located in the display area, no longer occupying the space of the border area, narrowing the border width of the display panel, and improving the screen-to-body ratio of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a method for preparing the same. Background Art

[0002] With the development of display panel technology, display forms have gradually become diversified. Among them, narrow-border display panels have been favored by consumers due to their high screen-to-body ratio and beautiful appearance, and have broad market prospects.

[0003] Current narrow-border display panels can often only achieve narrow border effects on the top, left, and right sides. The bottom border is more difficult to achieve a narrow border because a driver chip needs to be set up. This problem needs to be solved urgently. Summary of the invention

[0004] The present application provides a display panel and a method for manufacturing the same, which can effectively solve the problem of a larger border width caused by disposing a driver chip in a border area in the prior art.

[0005] In one aspect, the present application provides a display panel, the display panel having a display area, and the display panel comprising:

[0006] A light-emitting functional layer, comprising a plurality of light-emitting units arranged in an array in the display area;

[0007] The driving backplane comprises a first barrier layer, a driving circuit layer and at least one driving chip which are sequentially stacked in a direction away from the light-emitting functional layer, wherein:

[0008] The driving backplane further comprises a plurality of binding electrodes, a plurality of grooves are formed on a side of the first barrier layer facing the light-emitting functional layer, the binding electrodes are accommodated in the grooves and are electrically connected to the light-emitting units;

[0009] The driving circuit layer includes a driving circuit. The driving chip is located in the display area and is electrically connected to the binding electrodes through the driving circuit.

[0010] Optionally, the driving backplane also includes a plurality of first-type vias, the binding electrodes are arranged corresponding to the first-type vias, and are electrically connected to the driving circuit through the first-type vias, wherein the aperture of the first-type vias gradually decreases in the direction from the driving backplane toward the light-emitting functional layer.

[0011] Optionally, the driving backplane further includes a passivation layer, a wiring layer, and a plurality of second vias. The wiring layer is located on a side of the driving circuit layer away from the light-emitting functional layer. The passivation layer is located between the wiring layer and the driving circuit layer. The second vias penetrate through the passivation layer. Wherein, the wiring layer includes a plurality of traces. One end of each trace is electrically connected to the driving chip, and the other end of each trace is electrically connected to the driving circuit through the vias.

[0012] Optionally, in a direction of the driving backplane facing the light-emitting functional layer, the aperture diameter of the second vias gradually decreases.

[0013] Optionally, the driving backplane further includes a planarization layer. The planarization layer is disposed on a side of the wiring layer away from the light-emitting functional layer and covers the wiring layer and the driving chip. Wherein, a surface of the planarization layer away from the wiring layer is a flat surface.

[0014] Optionally, the display panel further includes a cover plate. The cover plate is disposed on a side of the planarization layer away from the light-emitting functional layer. Wherein, the cover plate is a rigid cover plate.

[0015] Optionally, a surface of the first barrier layer away from the driving circuit layer has a first roughness, and a surface of the first barrier layer facing the driving circuit layer has a second roughness. The first roughness is greater than the second roughness.

[0016] Optionally, the driving backplane further includes a substrate layer, a second barrier layer, and a buffer layer. The substrate layer, the second barrier layer, and the buffer layer are located between the first barrier layer and the driving circuit layer and are sequentially stacked in a direction away from the light-emitting functional layer. Wherein, a surface of the second barrier layer away from the driving circuit layer has a third roughness, and a surface of the second barrier layer facing the driving circuit layer has a fourth roughness. The first roughness is greater than the third roughness and the fourth roughness.

[0017] On the other hand, the present application provides a method for manufacturing a display panel. The method for manufacturing the display panel includes the following steps:

[0018] Provide a carrier substrate, and form a sacrificial layer on one side of the carrier substrate;

[0019] A driving backplane is formed on a side of the sacrificial layer facing away from the carrier substrate. Among them, the steps of fabricating and forming the driving backplane include: forming a plurality of bonding electrodes on a side of the sacrificial layer facing away from the carrier substrate; forming a first barrier layer on a side of the sacrificial layer and the bonding electrodes facing away from the carrier substrate; forming a driving circuit layer on a side of the first barrier layer facing away from the carrier substrate; forming at least one driving chip on a side of the driving circuit layer facing away from the carrier substrate; wherein, the driving circuit layer includes a driving circuit, and the driving chip is electrically connected to the bonding electrodes through the driving circuit;

[0020] A cover plate is formed on a side of the driving backplane facing away from the carrier substrate, wherein the cover plate is a rigid cover plate;

[0021] The carrier substrate and the sacrificial layer are peeled off to expose the bonding electrodes;

[0022] Taking the cover plate as a carrier plate, a light-emitting functional layer is formed on a side of the driving backplane facing away from the cover plate. Among them, the light-emitting functional layer includes a plurality of light-emitting units arranged in an array, and the light-emitting units are electrically connected to the exposed bonding electrodes;

[0023] Among them, a plurality of grooves are formed on a side of the first barrier layer facing the light-emitting functional layer, the bonding electrodes are accommodated in the grooves, the display panel has a display area, and both the driving chip and the light-emitting units are located in the display area.

[0024] Optionally, in the step of peeling off the carrier substrate and the sacrificial layer, the carrier substrate and the sacrificial layer are peeled off by a laser peeling process. Among them, the surface of the sacrificial layer on a side facing the driving circuit layer has a second roughness, and the laser peeling process makes the surface of the sacrificial layer on a side facing away from the driving circuit layer have a first roughness, and the first roughness is greater than the second roughness.

[0025] The present application provides a display panel and a manufacturing method thereof. By sequentially forming bonding electrodes, a first barrier layer, a substrate, a driving circuit layer, and a driving chip, the present application enables a plurality of grooves for accommodating the bonding electrodes to be formed on a side of the first barrier layer facing the light-emitting functional layer, and enables the driving chip to be directly formed on the driving circuit layer located in the display area, no longer occupying the space of the border area, narrowing the border width of the display panel, and improving the screen-to-body ratio of the display panel. Description of the Drawings

[0026] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those skilled in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0027] Figure 1 It is a schematic cross-sectional view of the display panel provided by the embodiment of the present application;

[0028] Figure 2 It is a schematic diagram of the position of the driving chip in the display panel provided by the embodiment of the present application;

[0029] Figure 3 It is a flowchart of the manufacturing method of the display panel provided by the embodiment of the present application;

[0030] Figure 4 It is a schematic cross-sectional view of the display panel corresponding to step S01 provided by the embodiment of the present application;

[0031] Figure 5 It is a schematic cross-sectional view of the display panel corresponding to step S02 provided by the embodiment of the present application;

[0032] Figure 6 It is a schematic cross-sectional view of the display panel corresponding to step S03 provided by the embodiment of the present application;

[0033] Figure 7 It is a schematic cross-sectional view of the display panel corresponding to step S04 provided by the embodiment of the present application;

[0034] Figure 8 It is a schematic cross-sectional view of the display panel corresponding to step S05 provided by the embodiment of the present application. Detailed implementation manners

[0035] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application. In addition, it should be understood that the specific implementation manners described here are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the orientation words such as "upper" and "lower" usually refer to the upper and lower in the actual use or working state of the device, specifically the drawing direction in the accompanying drawings; and "inner" and "outer" refer to the outline of the device.

[0036] The following disclosure provides many different embodiments or examples for implementing different structures of the present application. To simplify the disclosure of the present application, components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numerals and / or reference letters in different examples. Such repetition is for the purpose of simplification and clarity and does not itself indicate the relationship between various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art may be aware of the application of other processes and / or the use of other materials. The following will be described in detail respectively. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments.

[0037] Figure 1 It is a schematic cross-sectional view of a display panel provided by an embodiment of the present application; Figure 2 It is a schematic diagram of the position of a driving chip in a display panel provided by an embodiment of the present application. Referring to Figure 1 - Figure 2 The present application provides a display panel. The display panel has a display area 100. The display panel includes: a light-emitting functional layer including a plurality of light-emitting units 10 arranged in an array in the display area 100; a driving backplane 20 including a first barrier layer 202, a driving circuit layer, and at least one driving chip 215 that are sequentially stacked in a direction away from the light-emitting functional layer. Among them, the driving backplane 20 further includes a plurality of bonding electrodes 201. A plurality of grooves 2021 are formed on a side of the first barrier layer 202 facing the light-emitting functional layer. The bonding electrodes 201 are received in the grooves 2021 and are electrically connected to the light-emitting units 10; the driving circuit layer includes a driving circuit. The driving chip 215 is located in the display area 100 and is electrically connected to the bonding electrodes 201 through the driving circuit.

[0038] In the display panel provided by the present application, the driving backplane 20 includes a first barrier layer 202, a driving circuit layer, and at least one driving chip 215 that are sequentially stacked in a direction away from the light-emitting functional layer. Since the driving chip 215 is integrated in the driving backplane 20 and is electrically connected to the bonding electrodes 201 through the driving circuit in the driving circuit layer, therefore, the driving chip 215 can be directly disposed in the display area 100 of the display panel, without separately disposing the driving chip and the display panel body as in the display panel of the prior art, greatly reducing the width of the border area of the display panel and improving the screen-to-body ratio of the display panel.

[0039] In addition, since the first barrier layer 202 is formed with a groove 2021 for accommodating the bonding electrode 201 on the side facing the light-emitting functional layer, the bonding electrode 201 can be directly exposed by the groove 2021, thereby realizing electrical connection with the light-emitting unit 10.

[0040] In some embodiments of the present application, the driving backplane 20 is formed in the following manner: first, the bonding electrode 201 is fabricated on a planarized surface, then the first barrier layer 202 is formed to cover the planarized surface and the bonding electrode 201, and then the driving circuit layer and the driving chip 215 are sequentially formed. This formation method of the driving backplane 20 can enable the first barrier layer 202 to naturally form a groove 2021 having the same size as the bonding electrode 201.

[0041] In some embodiments of the present application, the driving backplane 20 further includes a plurality of first-type vias. The bonding electrode 201 is correspondingly arranged with the first-type vias and is electrically connected to the driving circuit through the first-type vias. Wherein, in the direction of the driving backplane 20 facing the light-emitting functional layer, the aperture diameter of the first-type vias gradually decreases.

[0042] Specifically, as described above, the bonding electrode 201, the first barrier layer 202, the driving circuit layer, and the driving chip 215 are sequentially formed in the direction away from the light-emitting functional layer. That is, during the formation of the first-type vias, the etching direction is along the direction from the driving circuit layer towards the first barrier layer 202. Therefore, in the direction of the driving backplane 20 facing the light-emitting functional layer, the aperture diameter of the first-type vias gradually decreases.

[0043] In some embodiments of the present application, the driving backplane 20 further includes a passivation layer 213, a wiring layer 214, and a plurality of second-type vias. The wiring layer 214 is located on the side of the driving circuit layer away from the light-emitting functional layer, the passivation layer 213 is located between the wiring layer 214 and the driving circuit layer, and the second-type vias penetrate through the passivation layer 213. Wherein, the wiring layer 214 includes a plurality of traces. One end of each trace is electrically connected to the driving chip 215, and the other end of the trace is electrically connected to the driving circuit through the vias.

[0044] Specifically, in order to facilitate the electrical connection between the driving circuits at various positions in the driving circuit layer and the driving chip 215, the driving backplane 20 further includes a wiring layer 214 located on the side of the driving circuit layer away from the light-emitting functional layer, and the lap joint between the driving circuit and the pins of the driving chip 215 is realized through each trace in the wiring layer 214.

[0045] In some embodiments of the present application, in the direction of the driving backplane 20 towards the light-emitting functional layer, the aperture of the second type of via hole gradually decreases.

[0046] Specifically, the second type of via hole is formed in the passivation layer 213 and penetrates through the passivation layer 213. Since the passivation layer 213 and the polyline layer 214 are sequentially formed on the driving circuit layer after the driving circuit layer is formed, that is, during the formation of the second type of via hole, the etching direction is along the direction of the driving circuit layer towards the first barrier layer 202. Therefore, in the direction of the driving backplane 20 towards the light-emitting functional layer, the aperture of the second type of via hole gradually decreases.

[0047] In some embodiments of the present application, the driving backplane 20 further includes a planarizing layer 216, which is disposed on the side of the polyline layer 214 facing away from the light-emitting functional layer and covers the polyline layer 214 and the driving chip 215. Wherein, the surface of the planarizing layer 216 facing away from the polyline layer 214 is a flat surface.

[0048] Specifically, as described above, the driving backplane 20 is formed on a planarized surface. After the driving backplane 20 is formed, only by separating the driving backplane 20 from the planarized surface and then inverting it can the bonding electrode 201 located in the groove 2021 be exposed, so that the light-emitting unit 10 can be formed on the bonding electrode 201. After the driving backplane 20 is inverted, in order to avoid damage to the driving chip 215 and the driving circuit on the driving backplane 20, a protective cover plate 30 needs to be formed on the driving backplane 20. In order to ensure the bonding stability between the cover plate 30 and the driving backplane 20, the surface of the driving backplane 20 facing away from the first barrier layer 202 needs to have flatness. Therefore, the driving backplane 20 is provided with the planarizing layer 216 on the side of the polyline layer 214 facing away from the light-emitting functional layer.

[0049] In some embodiments of the present application, the display panel further includes a cover plate 30, which is disposed on the side of the planarizing layer 216 facing away from the light-emitting functional layer. Wherein, the cover plate 30 is a rigid cover plate.

[0050] Specifically, as described above, in order to prevent damage to the driving chips 215 and driving circuits on the driving backplane 20 after the driving backplane 20 is inverted, a protective cover plate 30 needs to be formed on the driving backplane 20. To electrically connect the light-emitting unit 10 and the bonding electrode 201, the transfer and bonding operations need to be performed on the side of the driving backplane 20 facing away from the cover plate 30 with the cover plate 30 as the carrier plate. When the cover plate 30 is a flexible cover plate 30, it is difficult to ensure the transfer and bonding quality of the light-emitting unit 10. Therefore, the cover plate 30 is a rigid cover plate, that is, a non-bendable hard cover plate 30, and its material can be glass.

[0051] In some embodiments of the present application, the surface of the first barrier layer 202 facing away from the driving circuit layer has a first roughness, and the surface of the first barrier layer 202 facing the driving circuit layer has a second roughness, and the first roughness is greater than the second roughness.

[0052] Specifically, as described above, the driving backplane 20 is formed on a planarized surface. To expose the bonding electrode 201 accommodated in the groove 2021, the driving backplane 20 needs to be peeled off from the planarized surface. The peeling process is, for example, laser peeling. Since the energy of laser peeling is relatively high, it will cause certain burns to the surface of the film layer and increase the roughness. And the surface of the first barrier layer 202 facing away from the driving circuit layer is the surface in contact with the planarized surface. Therefore, the surface of the first barrier layer 202 facing away from the driving circuit layer has a first roughness greater than the second roughness.

[0053] In some embodiments of the present application, the driving backplane 20 further includes a substrate layer 203, a second barrier layer 204, and a buffer layer 205. The substrate layer 203, the second barrier layer 204, and the buffer layer 205 are located between the first barrier layer 202 and the driving circuit layer and are sequentially stacked in a direction away from the light-emitting functional layer.

[0054] Specifically, the substrate layer 203 is, for example, made of polyimide material; the first barrier layer 202 and the second barrier layer 204 are made of the same material, such as silicon nitride material or silicon oxide material.

[0055] Further, a surface of the second barrier layer 204 facing away from the driving circuit layer has a third roughness, and a surface of the second barrier layer 204 facing the driving circuit layer has a fourth roughness. The first roughness is greater than the third roughness and the fourth roughness. Since the second barrier layer 204 does not need to undergo a stripping process, the third roughness and the fourth roughness are both less than the first roughness. It should be noted that the third roughness may be the same as or different from the fourth roughness and the second roughness.

[0056] In some embodiments of the present application, the driving circuit layer includes: an active layer 206, a first gate insulating layer 207, a first gate layer 208, a second gate insulating layer 209, a second gate layer 210, an interlayer insulating layer 211, and a source-drain metal layer 212. The active layer 206 includes a channel 2061 and source regions 2062 and drain regions 2063 located on both sides of the channel 2061. The material of the channel 2061 is, for example, low-temperature polysilicon. The first gate layer 208 includes a first gate and a first signal transfer terminal. The second gate layer 210 includes a second gate and a second signal transfer terminal. The source-drain metal layer 212 includes: a source, a drain, an interconnect structure, a first signal line, a second signal line, and a third signal line. The drain is electrically connected to one of the adjacent two bonding electrodes 201 through the interconnect structure. The first signal line is electrically connected to the other of the adjacent two bonding electrodes 201. The second signal line is electrically connected to the first signal transfer terminal. The third signal line is electrically connected to the second signal transfer terminal.

[0057] In some embodiments of the present application, the bonding electrode 201 is electrically connected to the light-emitting unit 10 through a pad 40.

[0058] On the other hand, the present application also provides a method for manufacturing a display panel. Figure 4 is a cross-sectional schematic diagram of the display panel corresponding to step S01 provided by the embodiment of the present application; Figure 5 is a cross-sectional schematic diagram of the display panel corresponding to step S02 provided by the embodiment of the present application; Figure 6 is a cross-sectional schematic diagram of the display panel corresponding to step S03 provided by the embodiment of the present application; Figure 7 is a cross-sectional schematic diagram of the display panel corresponding to step S04 provided by the embodiment of the present application; Figure 8 is a cross-sectional schematic diagram of the display panel corresponding to step S05 provided by the embodiment of the present application. Refer to Figure 1 、 Figure 3 - Figure 8 , the method for manufacturing the display panel includes the following steps:

[0059] S01: Provide a carrier substrate 50, and form a sacrificial layer 60 on one side of the carrier substrate 50.

[0060] S02: Form a driving backplane 20 on the side of the sacrificial layer 60 facing away from the carrier substrate 50.

[0061] S03: Form a cover plate 30 on the side of the driving backplane 20 facing away from the carrier substrate 50.

[0062] S04: Peel off the carrier substrate 50 and the sacrificial layer 60 to expose the bonding electrode 201.

[0063] S05: Using the cover plate 30 as a carrier plate, form a light-emitting functional layer on the side of the driving backplane 20 facing away from the cover plate 30.

[0064] In the S01 step, the material of the carrier substrate 50 is, for example, polyimide, and the sacrificial layer 60 is used to improve the peeling efficiency of the carrier substrate 50 from the driving backplane 20 in subsequent peeling processes.

[0065] The S02 step of preparing and forming the driving backplane 20 includes:

[0066] Form a plurality of bonding electrodes 201 on the side of the sacrificial layer 60 facing away from the carrier substrate 50;

[0067] Form a first barrier layer 202 on the side of the sacrificial layer 60 and the bonding electrodes 201 facing away from the carrier substrate 50;

[0068] Form a driving circuit layer on the side of the first barrier layer 202 facing away from the carrier substrate 50;

[0069] Form at least one driving chip 215 on the side of the driving circuit layer facing away from the carrier substrate 50.

[0070] Among them, the driving circuit layer includes a driving circuit, and the driving chip 215 is electrically connected to the bonding electrode 201 through the driving circuit.

[0071] Further, the S02 step of preparing and forming the driving backplane 20 is specifically:

[0072] Form a plurality of bonding electrodes 201 on the side of the sacrificial layer 60 facing away from the carrier substrate 50;

[0073] Form a first barrier layer 202 on the side of the sacrificial layer 60 and the bonding electrodes 201 facing away from the carrier substrate 50;

[0074] A buffer layer 203 is formed on a side of the first barrier layer 202 facing away from the carrier substrate 50. Herein, the buffer layer 203 and the carrier substrate 50 are made of the same material;

[0075] A second barrier layer 204 is formed on a side of the buffer layer 203 facing away from the carrier substrate 50. Herein, the second barrier layer 204 is made of the same material as the first barrier layer 202;

[0076] A buffer layer 205 is formed on a side of the second barrier layer 204 facing away from the carrier substrate 50;

[0077] A driving circuit layer is formed on a side of the buffer layer 205 facing away from the carrier substrate 50. Herein, the driving circuit in the driving circuit layer is electrically connected to the bonding electrode through a via connection;

[0078] At least one driving chip 215 is formed on a side of the driving circuit layer facing away from the carrier substrate 50. Herein, the driving chip 215 is electrically connected to the driving circuit through a via connection.

[0079] In the step S03, the cover plate 30 is a rigid cover plate.

[0080] In the step S04, the carrier substrate 50 and the sacrificial layer 60 are peeled off by a laser lift-off process. Herein, a surface of a side of the sacrificial layer 60 facing the driving circuit layer has a second roughness, and the laser lift-off process makes a surface of a side of the sacrificial layer 60 facing away from the driving circuit layer have a first roughness, and the first roughness is greater than the second roughness.

[0081] In the step S05, the light-emitting functional layer includes a plurality of light-emitting units 10 arranged in an array, and the light-emitting units 10 are electrically connected to the exposed bonding electrodes 201.

[0082] Furthermore, in the display panel prepared by the above preparation method, a plurality of grooves 2021 are formed on a side of the first barrier layer 202 facing the light-emitting functional layer, and the bonding electrodes 201 are accommodated in the grooves 2021; the display panel has a display area 100, and both the driving chip 215 and the light-emitting units 10 are located in the display area 100.

[0083] In summary, the present application provides a display panel and a manufacturing method thereof. The display panel includes: a light-emitting functional layer including a plurality of light-emitting units; a driving backplane including a bonding electrode, and a first barrier layer, a driving circuit layer, and at least one driving chip that are sequentially stacked in a direction away from the light-emitting functional layer. A plurality of grooves are formed on a side of the first barrier layer facing the light-emitting functional layer; the bonding electrode is received in the groove and electrically connected to the light-emitting unit; the driving chip is located in the display area and is electrically connected to the bonding electrode through a driving circuit in the driving circuit layer. By sequentially forming the bonding electrode, the first barrier layer, the substrate, the driving circuit layer, and the driving chip, the present application enables a groove for receiving the bonding electrode to be formed on a side of the first barrier layer facing the light-emitting functional layer, and enables the driving chip to be directly formed on the driving circuit layer located in the display area, no longer occupying the space of the border area, narrowing the border width of the display panel, and increasing the screen-to-body ratio of the display panel.

[0084] The above has introduced in detail a display panel and a manufacturing method thereof provided by an embodiment of the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A display panel, characterized in that, the display panel has a display area, and the display panel includes: a light-emitting functional layer including a plurality of light-emitting units arranged in an array in the display area; a driving backplane including a first barrier layer, a driving circuit layer, and at least one driving chip stacked in sequence in a direction away from the light-emitting functional layer, wherein, the driving backplane further includes a plurality of bonding electrodes, a plurality of grooves are formed on a side of the first barrier layer facing the light-emitting functional layer, and the bonding electrodes are accommodated in the grooves and electrically connected to the light-emitting units; the driving circuit layer includes a driving circuit, the driving chip is located on the driving circuit layer in the display area and is electrically connected to the bonding electrodes through the driving circuit; the driving backplane further includes a plurality of first-type vias, the bonding electrodes are correspondingly arranged with the first-type vias and are electrically connected to the driving circuit through the first-type vias; the driving backplane further includes a passivation layer, a wire aggregation layer, and a plurality of second-type vias, the wire aggregation layer is located on a side of the driving circuit layer away from the light-emitting functional layer, the passivation layer is located between the wire aggregation layer and the driving circuit layer, and the second-type vias penetrate through the passivation layer, wherein the wire aggregation layer includes a plurality of traces, one end of each trace is electrically connected to the driving chip, and the other end of each trace is electrically connected to the driving circuit through the second-type vias.

2. The display panel according to claim 1, characterized in that, in a direction of the driving backplane facing the light-emitting functional layer, the aperture of the first-type via gradually decreases.

3. The display panel according to claim 1, characterized in that, in a direction of the driving backplane facing the light-emitting functional layer, the aperture of the second-type via gradually decreases.

4. The display panel according to claim 1, characterized in that, the driving backplane further includes a planarization layer, the planarization layer is arranged on a side of the wire aggregation layer away from the light-emitting functional layer and covers the wire aggregation layer and the driving chip, wherein a surface of the planarization layer away from the wire aggregation layer is a flat surface.

5. The display panel according to claim 4, characterized in that, the display panel further includes a cover plate, the cover plate is arranged on a side of the planarization layer away from the light-emitting functional layer, wherein the cover plate is a rigid cover plate.

6. The display panel according to claim 1, characterized in that, a surface of the first barrier layer away from the driving circuit layer has a first roughness, a surface of the first barrier layer facing the driving circuit layer has a second roughness, and the first roughness is greater than the second roughness.

7. The display panel according to claim 6, characterized in that, The driving backplane further includes a substrate layer, a second barrier layer, and a buffer layer. The substrate layer, the second barrier layer, and the buffer layer are located between the first barrier layer and the driving circuit layer, and are sequentially stacked in a direction away from the light-emitting functional layer. Wherein, the surface of the second barrier layer on the side away from the driving circuit layer has a third roughness, the surface of the second barrier layer on the side facing the driving circuit layer has a fourth roughness, and the first roughness is greater than the third roughness and the fourth roughness.

8. A method for manufacturing a display panel, characterized in that, the method for manufacturing the display panel includes the following steps: providing a carrier substrate, and forming a sacrificial layer on one side of the carrier substrate; forming a driving backplane on the side of the sacrificial layer away from the carrier substrate. Wherein, the step of preparing and forming the driving backplane includes: forming a plurality of bonding electrodes on the side of the sacrificial layer away from the carrier substrate; forming a first barrier layer on the side of the sacrificial layer and the bonding electrodes away from the carrier substrate; forming a driving circuit layer on the side of the first barrier layer away from the carrier substrate; forming at least one driving chip on the side of the driving circuit layer away from the carrier substrate. Wherein, the driving circuit layer includes a driving circuit, and the driving chip is electrically connected to the bonding electrodes through the driving circuit; forming a cover plate on the side of the driving backplane away from the carrier substrate, wherein the cover plate is a rigid cover plate; peeling off the carrier substrate and the sacrificial layer to expose the bonding electrodes; using the cover plate as a carrier plate, and forming a light-emitting functional layer on the side of the driving backplane away from the cover plate. Wherein, the light-emitting functional layer includes a plurality of light-emitting units arranged in an array, and the light-emitting units are electrically connected to the exposed bonding electrodes; wherein, a plurality of grooves are formed on the side of the first barrier layer facing the light-emitting functional layer, the bonding electrodes are accommodated in the grooves, the display panel has a display area, the light-emitting units are located in the display area, and the driving chips are located on the driving circuit layer in the display area; the driving backplane further includes a plurality of first type vias, the bonding electrodes are correspondingly arranged with the first type vias, and are electrically connected to the driving circuit through the first type vias; the driving backplane further includes a passivation layer, a wiring layer, and a plurality of second type vias. The wiring layer is located on the side of the driving circuit layer away from the light-emitting functional layer, the passivation layer is located between the wiring layer and the driving circuit layer, and the second type vias penetrate through the passivation layer. Wherein, the wiring layer includes a plurality of traces, one end of the trace is electrically connected to the driving chip, and the other end of the trace is electrically connected to the driving circuit through the second type vias.

9. According to the method for manufacturing a display panel as claimed in claim 8, characterized in that, In the step of peeling the carrier substrate and the sacrificial layer, the laser lift-off process is used to peel the carrier substrate and the sacrificial layer. Among them, the surface of the side of the sacrificial layer facing the driving circuit layer has a second roughness, and the laser lift-off process makes the surface of the side of the sacrificial layer facing away from the driving circuit layer have a first roughness, and the first roughness is greater than the second roughness.

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