A planar-gate SJ IGBT device with a PN junction contact

Abstract

The present invention relates to a planar-gate SJ IGBT device with a PN junction contact, belonging to the technical field of power semiconductor devices. In the present invention, a P-type ring region is introduced into the JFET region of a traditional planar-gate SJ IGBT device, and the P-type ring region is connected to the emitter metal through a polysilicon PN junction. In the on state, a barrier is formed by the PN junction of the polysilicon between the P-type ring region and the emitter. The low forward conduction voltage drop is not sufficient to forward-conduct the PN junction, so it will not affect the on state of the device; in the blocking state, the P-type ring region is reverse-biased, and the PN junction structure of the polysilicon is shielded by the P-type ring region and will not affect the blocking state of the device; during the turn-off process, as the collector voltage rises, the barrier of the PN junction decreases and forward-conducts, providing an additional path for the extraction of holes, accelerating the extraction speed of the carriers in the drift region, improving the switching speed of the planar-gate SJ IGBT device, and reducing the turn-off loss of the device.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductors, and particularly relates to a planar-gate SJ IGBT device with PN junction contacts. Background Art

[0002] After being invented, the Insulated Gate Bipolar Transistor (IGBT) has quickly become a research hotspot in power semiconductor devices. The IGBT not only has the advantages of voltage control, high input impedance, fast switching speed, and easy driving of field-effect transistor devices, but also has the advantage of low forward conduction voltage drop of bipolar devices. Therefore, it has become one of the most important power semiconductor devices. The development of IGBT mainly focuses on three aspects: the optimization of its body region, the optimization of the collector structure, and the optimization of the surface structure. Among them, the optimization of the body region mainly includes Field Stop (FS) technology, Carrier Stored (CS) technology, and floating P-body region. The optimization of the collector structure includes passive collector structure and active collector structure. The optimization of the surface structure is mainly the improvement from planar gate to trench gate. The application of these technologies has significantly improved the dynamic and static performance and reliability of IGBT devices. The use of Super Junction (SJ) technology further optimizes the trade-off relationship between the breakdown voltage and the on-resistance of IGBT devices, and the P-columns of the superjunction structure accelerate the extraction of holes during the turn-off process of IGBT devices, further improving the dynamic and static performance of IGBT devices. Compared with traditional IGBT devices, SJ IGBT devices can have lower turn-off losses at the same breakdown voltage level. However, with the continuous development of the application scenarios of IGBT devices, there is a requirement for IGBT devices to have faster switching speeds. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a planar-gate SJ IGBT device with PN junction contacts in view of the problems existing in the prior art. The present invention introduces a P-type ring region doped with P-type in the JFET region of the planar-gate SJ IGBT device. The P-type ring region is connected to the emitter metal through the PN junction of polysilicon, thereby improving the hole extraction speed during the turn-off process of the planar-gate SI IGBT device, increasing the switching speed of the planar-gate SJ IGBT device, and reducing the turn-off loss of the device.

[0004] To solve the above technical problems, an embodiment of the present invention provides a planar-gate SJ IGBT device with a PN junction contact. Its cell structure includes a collector metal 1, a P+ collector region 2, an N-type field stop layer 3, a P pillar 4, an N pillar 5, an N-type carrier storage layer 6, a P-type body region 7, an N+ emitter 8, a polysilicon gate 9, a P-type ring region 10, a gate oxide 11, a P-type polysilicon 12, an N-type polysilicon 13, and an emitter metal 14;

[0005] The collector metal 1, the P+ collector region 2, and the N-type field stop layer 3 are stacked in sequence from bottom to top; the P pillar 4 and the N pillar 5 are located on the N-type field stop layer 3, and the P pillar 4 is located on both sides of the N pillar 5 to form a superjunction structure; the N-type carrier storage layer 6 is located on the P pillar 4 and the N pillar 5; the P-type body region 7 is located on both sides of the top layer of the N-type carrier storage region 6, the P-type ring region 10 is located on the top layer of the N-type carrier storage layer 6 between the two P-type body regions 7, and the P-type body region 7 and the P-type ring region 10 are isolated by the N-type carrier storage region 6; the N+ emitter 8 is located on the top layer of the P-type body region 7;

[0006] The gate oxide 11 is located on the first part of the N+ emitter 8, the first part of the P-type body region 7, and the N-type carrier storage layer 6. The polysilicon gate 9 is located in the gate oxide 11. The two gate oxides 11 are isolated by the P-type polysilicon 12 and the N-type polysilicon 13 stacked in sequence from bottom to top. The polysilicon gate 9 is isolated from other parts through the gate oxide 11; the P-type polysilicon 12 is located on the P-type ring region 10; the P-type ring region 10 is connected to the emitter metal 14 through the PN junction formed by the P-type polysilicon 12 and the N-type polysilicon 13; the emitter metal 14 is located on the second part of the N+ emitter 8, the second part of the P-type body region 7, the gate oxide 11, and the N-type polysilicon 13; an ohmic contact is formed between the emitter metal 14 and the P-type body region 7.

[0007] Based on the above technical solutions, the present invention can be further improved as follows.

[0008] Further, the P-type polysilicon 12 and the N-type polysilicon 13 are formed by ion implantation.

[0009] The beneficial effects of the present invention are as follows: Compared with the traditional planar-gate SJ IGBT structure, for a planar-gate SJ IGBT structure with PN junction contact provided by the present invention, in the on-state, a potential barrier is formed by the PN junction of polysilicon between the P-type ring region and the emitter. The low forward conduction voltage drop is not sufficient to forward-conduct this PN junction, so it will not affect the on-state of the device; in the blocking state, the P-type ring region is reverse-biased, and this PN junction structure still will not affect the blocking state of the device; during the turn-off process, as the collector voltage rises, the potential barrier of this PN junction decreases and it conducts forward, providing an additional path for the extraction of holes, accelerating the extraction speed of carriers in the drift region, improving the switching speed of the planar-gate SJ IGBT device, and reducing the turn-off loss of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 FIG. is a schematic structural diagram of a planar-gate SJ IGBT device with PN junction contact according to an embodiment of the present invention;

[0011] Figure 2 FIG. is a schematic structural diagram of a traditional planar-gate SJ IGBT.

[0012] In the drawings, the list of components represented by each reference numeral is as follows:

[0013] 1 is the collector metal, 2 is the P+ collector region, 3 is the N field-stop layer, 4 is the P pillar, 5 is the N pillar, 6 is the N-type carrier storage layer, 7 is the P-type body region, 8 is the N+ emitter, 9 is the polysilicon gate, 10 is the P-type ring region, 11 is the gate oxide, 12 is the P-type polysilicon, 13 is the N-type polysilicon, and 14 is the emitter metal. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0014] The principles and features of the present invention will be described below with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0015] As Figure 1 shown, a planar-gate SJ IGBT device with PN junction contact provided by the first embodiment of the present invention has a cell structure including a collector metal 1, a P+ collector region 2, an N-type field-stop layer 3, a P pillar 4, an N pillar 5, an N-type carrier storage layer 6, a P-type body region 7, an N+ emitter 8, a polysilicon gate 9, a P-type ring region 10, a gate oxide 11, a P-type polysilicon 12, an N-type polysilicon 13, and an emitter metal 14;

[0016] The collector metal 1, the P+ collector region 2, and the N-type field stop layer 3 are stacked in sequence from bottom to top; the P pillars 4 and the N pillars 5 are located on the N-type field stop layer 3, and the P pillars 4 are located on both sides of the N pillars 5 to form a superjunction structure; the N-type carrier storage layer 6 is located on the P pillars 4 and N pillars 5; the P-type body region 7 is located on both sides of the top layer of the N-type carrier storage region 6, the P-type ring region 10 is located on the top layer of the N-type carrier storage layer 6 between the two P-type body regions 7, and the P-type body region 7 and the P-type ring region 10 are isolated by the N-type carrier storage region 6; the N+ emitter 8 is located on the top layer of the P-type body region 7;

[0017] The gate oxide 11 is located on the first part of the N+ emitter 8, the first part of the P-type body region 7, and the N-type carrier storage layer 6. The polysilicon gate 9 is located in the gate oxide 11. The two gate oxides 11 are isolated by the P-type polysilicon 12 and the N-type polysilicon 13 stacked in sequence from bottom to top. The polysilicon gate 9 is isolated from other parts through the gate oxide 11; the P-type polysilicon 12 is located on the P-type ring region 10; the P-type ring region 10 is connected to the emitter metal 14 through the PN junction formed by the P-type polysilicon 12 and the N-type polysilicon 13; the emitter metal 14 is located on the second part of the N+ emitter 8, the second part of the P-type body region 7, the gate oxide 11, and the N-type polysilicon 13; an ohmic contact is formed between the emitter metal 14 and the P-type body region 7.

[0018] The working principle of this embodiment is as follows:

[0019] For a planar gate SJ IGBT device with a PN junction contact provided by the present invention, its connection mode in the off state is: the emitter metal 14 is grounded, the polysilicon gate 9 is grounded, and the collector metal 1 is connected to a high potential. Its connection mode in the on state is: the emitter metal 14 is grounded, the polysilicon gate 9 is connected to a gate turn-on potential higher than the threshold voltage, and the collector metal 1 is connected to a high potential.

[0020] When the device is in the on state, a potential barrier is formed by the PN junction of the polysilicon between the P-type ring region and the emitter. The low forward conduction voltage drop is not sufficient to make the PN junction conduct forward, ensuring the carrier concentration on the cathode side of the device. Compared with the traditional planar gate SJ IGBT structure (as Figure 2 shown), the conduction voltage drop remains basically unchanged.

[0021] In the blocking state, the P-type ring region is reverse-biased, and the PN junction structure of the polysilicon is shielded by the P-type ring region and will not affect the blocking state of the device.

[0022] During the turn-off process, as the collector voltage rises, the potential barrier of this PN junction decreases, and it conducts forward, providing an additional path for the extraction of holes, accelerating the extraction speed of carriers in the drift region, increasing the switching speed of the planar-gate SJ IGBT device, and reducing the turn-off loss of the device.

[0023] In summary, compared with the traditional SJ IGBT, the present invention optimizes the surface structure of the device. Without affecting the static characteristics of the device, the turn-off speed of the device is increased, and the turn-off loss of the device is reduced.

[0024] Optionally, the P-type polysilicon 12 and the N-type polysilicon 13 are formed by ion implantation.

[0025] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. They are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present invention.

[0026] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present invention, "a plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0027] In the present invention, unless otherwise clearly specified and defined, the terms "mounted", "connected", "coupled", "fixed", etc. should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0028] In the present invention, unless otherwise clearly defined and limited, the first feature being "on" or "under" the second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may mean that the first feature is directly above or obliquely above the second feature, or merely indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "below" and "beneath" the second feature may mean that the first feature is directly below or obliquely below the second feature, or merely indicates that the horizontal height of the first feature is less than that of the second feature.

[0029] In the description of this specification, the description of reference terms such as "an embodiment", "some embodiments", "examples", "specific examples", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0030] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection scope of the present invention.

Claims

1. A planar-gate SJ IGBT device with a PN junction contact, characterized in that, Its cell structure includes collector metal (1), P+ collector region (2), N-type field stop layer (3), P pillars (4), N pillars (5), N-type carrier storage layer (6), P-type body region (7), N+ emitter (8), polysilicon gate (9), P-type ring region (10), gate oxide (11), P-type polysilicon (12), N-type polysilicon (13) and emitter metal (14); The collector metal (1), the P+ collector region (2) and the N-type field stop layer (3) are stacked in sequence from bottom to top; the P pillars (4) and the N pillars (5) are located on the N-type field stop layer (3), and the P pillars (4) are located on both sides of the N pillars (5) to form a superjunction structure; the N-type carrier storage layer (6) is located on the P pillars (4) and N pillars (5); the P-type body region (7) is located on both sides of the top layer of the N-type carrier storage region (6), the P-type ring region (10) is located on the top layer of the N-type carrier storage layer (6) between the two P-type body regions (7), and the P-type body region (7) and the P-type ring region (10) are isolated by the N-type carrier storage region (6); the N+ emitter (8) is located on the top layer of the P-type body region (7); The gate oxide (11) is located on the first part of the N+ emitter (8), the first part of the P-type body region (7) and the N-type carrier storage layer (6), the polysilicon gate (9) is located in the gate oxide (11), and the two gate oxides (11) are isolated by the P-type polysilicon (12) and N-type polysilicon (13) stacked in sequence from bottom to top, and the polysilicon gate (9) is isolated from other parts through the gate oxide (11); the P-type polysilicon (12) is located on the P-type ring region (10); the P-type ring region (10) and the emitter metal (14) are connected through the PN junction formed by the P-type polysilicon (12) and the N-type polysilicon (13); the emitter metal (14) is located on the second part of the N+ emitter (8), the second part of the P-type body region (7), the gate oxide (11) and the N-type polysilicon (13); an ohmic contact is formed between the emitter metal (14) and the P-type body region (7).

2. The planar-gate SJ IGBT device with a PN junction contact according to claim 1, characterized in that, The P-type polysilicon (12) and the N-type polysilicon (13) are formed by ion implantation.

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