Semiconductor devices

Abstract

The present invention discloses a semiconductor device, comprising a first gate, a second gate, a third gate, a first semiconductor layer, a second semiconductor layer, a source electrode and a drain electrode. The first semiconductor layer is located between the first gate and the second gate electrode. The second gate electrode is located between the first semiconductor layer and the second semiconductor layer. The second semiconductor layer is located between the second gate electrode and the third gate electrode. The source electrode is electrically connected to the first semiconductor layer and the second semiconductor layer. The drain electrode is electrically connected to the first semiconductor layer and the second semiconductor layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] Dual-gate thin-film transistors have the advantage of high driving current, and therefore are often used as driving elements of organic light-emitting diode display devices or micro light-emitting diode display devices. Specifically, in order to make the display device have a sufficiently high resolution, the area of ​​the driving element used to drive the light-emitting diode in the display device is limited. Therefore, many manufacturers will choose to set a dual-gate thin-film transistor as a driving element in a limited area, thereby making the driving element have a sufficiently high driving current.

[0003] However, compared with the conventional single-gate thin film transistor, the reliability of the dual-gate thin film transistor is lower, and after long-term operation, the dual-gate thin film transistor is prone to problems of driving current decay and threshold voltage shift. Summary of the invention

[0004] The invention provides a semiconductor device which can improve the negative impact caused by current stress or hot carrier effect.

[0005] A semiconductor device includes a first gate, a second gate, a third gate, a first semiconductor layer, a second semiconductor layer, a source electrode, and a drain electrode. The first semiconductor layer is located between the first gate and the second gate. The second gate is located between the first semiconductor layer and the second semiconductor layer. The second semiconductor layer is located between the second gate and the third gate. The source electrode is electrically connected to the first semiconductor layer and the second semiconductor layer. The drain electrode is electrically connected to the first semiconductor layer and the second semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A is a top view schematically showing a semiconductor device according to an embodiment of the present invention;

[0007] Figure 1B It is along Figure 1A A schematic cross-sectional view of line A-A';

[0008] Figure 1C It is along Figure 1A A schematic cross-sectional view of line BB';

[0009] Figures 2A to 2G yes Figures 1A to 1C A schematic cross-sectional view of a method for manufacturing a semiconductor device;

[0010] Figure 3A is a top view schematically showing a semiconductor device according to an embodiment of the present invention;

[0011] Figure 3B It is along Figure 3AA schematic cross-sectional view of line A-A';

[0012] Figure 3C It is along Figure 3A A schematic cross-sectional view of line BB';

[0013] FIG. 4A to FIG. 4E yes FIG. 3A to FIG. 3C A schematic cross-sectional view of a method for manufacturing a semiconductor device;

[0014] Figure 5A is a top view schematically showing a semiconductor device according to an embodiment of the present invention;

[0015] Figure 5B It is along Figure 5A A schematic cross-sectional view of line A-A';

[0016] Figure 5C It is along Figure 5A A schematic cross-sectional view of line BB';

[0017] 6A to 6H yes FIG. 5A to FIG. 5C A schematic cross-sectional view of a method for manufacturing a semiconductor device;

[0018] Fig. 7A is a top view schematically showing a semiconductor device according to an embodiment of the present invention;

[0019] Figure 7B It is along Fig. 7A A schematic cross-sectional view of line A-A';

[0020] Figure 7C It is along Fig. 7A A schematic cross-sectional view of line BB';

[0021] Figure 8 yes 7A to 7C A schematic cross-sectional view of a method for manufacturing a semiconductor device;

[0022] Fig. 9 FIG. 4 is a schematic diagram of an equivalent circuit of a semiconductor device according to an embodiment of the present invention.

[0023] Explanation of symbols

[0024] 10,20,30,40:Semiconductor devices

[0025] 100: Insulation structure

[0026] 110: first gate dielectric layer

[0027] 112: first nitride layer

[0028] 114: first oxygen-containing dielectric layer

[0029] 120: second gate dielectric layer

[0030] 130: third gate dielectric layer

[0031] 132: Second nitride layer

[0032] 134: second oxygen-containing dielectric layer

[0033] 140: fourth gate dielectric layer

[0034] 150: Protective layer

[0035] 210: first gate

[0036] 220: first semiconductor layer

[0037] 220': first semiconductor material layer

[0038] 222: first source region

[0039] 224: First channel region

[0040] 226 first drain region

[0041] 230: Second gate

[0042] 240: Second semiconductor layer

[0043] 240': second semiconductor material layer

[0044] 242: Second source region

[0045] 244: Second channel region

[0046] 246: Second drain region

[0047] 250: The third gate

[0048] 262,S: Source

[0049] 264,D:Drain

[0050] CH1: first contact hole

[0051] CH2: Second contact hole

[0052] CH3: The third contact hole

[0053] CH4: fourth contact hole

[0054] CH5: fifth contact hole

[0055] CH6: Sixth contact hole

[0056] CL1, CL2, DL1, DL2, SL1, SL2: Length

[0057] G1, G2, G3: Gate

[0058] ND: Normal direction

[0059] P1, P2: Doping process

[0060] OP1,CH1': First opening

[0061] OP2,CH2': Second opening

[0062] PR: Patterned photoresist layer

[0063] SB:Substrate

[0064] TFT1, TFT2: switching elements

[0065] TH1: First through hole

[0066] TH2: Second through hole DETAILED DESCRIPTION

[0067] Figure 1A is a top view of a semiconductor device 10 according to an embodiment of the present invention. Figure 1B It is along Figure 1A A schematic cross-sectional view of line AA'. Figure 1C It is along Figure 1A A schematic cross-sectional view of the line B-B'. Figure 1A , the first gate 210 , the second gate 230 , the third gate 250 , the first semiconductor layer 220 , the second semiconductor layer 240 , the source 262 , and the drain 264 are illustrated, and other components are omitted.

[0068] Please refer to Figures 1A to 1C The semiconductor device 10 includes a first gate 210 , a second gate 230 , a third gate 250 , a first semiconductor layer 220 , a second semiconductor layer 240 , a source 262 , and a drain 264 . In the present embodiment, the semiconductor device 10 further includes a substrate SB and an insulating structure 100 .

[0069] The material of the substrate SB includes glass, quartz, organic polymer or opaque / reflective material (e.g., conductive material, metal, wafer, ceramic or other applicable material) or other applicable materials. If a conductive material or metal is used, an insulating layer (not shown) is covered on the substrate SB to avoid short circuit problems.

[0070] The first gate 210, the second gate 230 and the third gate 250 are located on the substrate 100. In some embodiments, one or more buffer layers (not shown) are further included between the first gate 210 and the substrate 100. The materials of the first gate 210, the second gate 230 and the third gate 250 include metals such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, the above alloys, the above metal oxides, the above metal nitrides or the above combinations or other conductive materials. For example, the first gate 210, the second gate 230 and the third gate 250 are respectively stacked layers of titanium metal, aluminum metal and titanium metal. The first gate 210, the second gate 230 and the third gate 250 are electrically connected to each other.

[0071] The first semiconductor layer 220 is located between the first gate 210 and the second gate 230. The second gate 230 is located between the first semiconductor layer 220 and the second semiconductor layer 240. The second semiconductor layer 240 is located between the second gate 220 and the third gate 250.

[0072] The materials of the first semiconductor layer 220 and the second semiconductor layer 240 include amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor materials, metal oxide semiconductor materials (such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO), indium zinc oxide (IZO), gallium zinc oxide (GZO), zinc tin oxide (ZTO), indium tin oxide (ITO) or other suitable materials) or other suitable materials or combinations thereof. The materials of the first semiconductor layer 220 and the second semiconductor layer 240 are the same or different from each other.

[0073] In some embodiments, the thickness of the first semiconductor layer 220 and the thickness of the second semiconductor layer 240 are 10 nanometers to 80 nanometers. The thickness of the first semiconductor layer 220 and the thickness of the second semiconductor layer 240 are the same as or different from each other.

[0074] In the present embodiment, the first semiconductor layer 220 includes a first source region 222 , a first channel region 224 , and a first drain region 226 connected in sequence. The resistivity of the first source region 222 and the first drain region 226 is smaller than the resistivity of the first channel region 224 .

[0075] In the present embodiment, the second semiconductor layer 240 includes a second source region 242 , a second channel region 244 , and a second drain region 246 connected in sequence. The resistivity of the second source region 242 and the second drain region 246 is smaller than the resistivity of the second channel region 244 .

[0076] In some embodiments, the first gate 210, the second gate 230, the third gate 250, the first channel region 224, and the second channel region 244 overlap in the normal direction ND of the top surface of the substrate SB. The length CL1 of the first channel region 224 and the length CL2 of the second channel region 244 are the same as or different from each other. In the present embodiment, the length SL2 of the second source region 242 and the length DL2 of the second drain region 246 are less than the length SL1 of the first source region 222 and the length DL1 of the first drain region 226, and the length of the second semiconductor layer 220 (the sum of the length SL2, the length CL2, and the length DL2) is less than the length of the first semiconductor layer 220 (the sum of the length SL1, the length CL1, and the length DL1).

[0077] The insulating structure 100 covers the first gate 210, the second gate 230, the third gate 250, the first semiconductor layer 220 and the second semiconductor layer 240. The insulating structure 100 has a first contact hole CH1, a second contact hole CH2, a third contact hole CH3 and a fourth contact hole CH4. In this embodiment, the insulating structure 100 further includes a fifth contact hole CH5 and a sixth contact hole CH6.

[0078] In the present embodiment, the insulating structure 100 includes a first gate dielectric layer 110 , a second gate dielectric layer 120 , a third gate dielectric layer 130 , a fourth gate dielectric layer 140 and a protection layer 150 .

[0079] The first gate dielectric layer 110 is located between the first gate electrode 210 and the first semiconductor layer 220. The first gate dielectric layer 110 is a single layer or a multilayer structure. In the present embodiment, the first gate dielectric layer 110 includes a first nitride layer 112 and a first oxygen-containing dielectric layer 114. The first nitride layer 112 contacts the first gate electrode 210 and the first oxygen-containing dielectric layer 114 contacts the first semiconductor layer 220. In some embodiments, the material of the first nitride layer 112 includes, for example, silicon nitride or other suitable materials. In some embodiments, the thickness of the first nitride layer 112 is 30 nanometers to 300 nanometers. In some embodiments, the material of the first oxygen-containing dielectric layer 114 includes, for example, silicon oxynitride, silicon oxide, hafnium oxide or other suitable materials. For example, the first oxygen-containing dielectric layer 114 is SiO x N y , wherein x is 1 to 0.5, and y is 0 to 0.5. In some embodiments, the first oxygen-containing dielectric layer 114 has a thickness of 50 nanometers to 200 nanometers.

[0080] The second gate dielectric layer 120 is located between the first semiconductor layer 220 and the second gate 230. The second gate dielectric layer 120 is a single layer or multilayer structure. In the present embodiment, the material of the second gate dielectric layer 120 includes, for example, silicon oxynitride, silicon oxide, hafnium oxide or other suitable materials. In some embodiments, the thickness of the second gate dielectric layer 120 is 50 nanometers to 200 nanometers.

[0081] The third gate dielectric layer 130 is located between the second gate electrode 230 and the second semiconductor layer 240. The third gate dielectric layer 130 is a single layer or a multilayer structure. In the present embodiment, the third gate dielectric layer 130 includes a second nitride layer 132 and a second oxygen-containing dielectric layer 134. The second nitride layer 132 contacts the second gate electrode 230 and the second oxygen-containing dielectric layer 134 contacts the second semiconductor layer 240. In some embodiments, the material of the second nitride layer 132 includes, for example, silicon nitride or other suitable materials. In some embodiments, the thickness of the second nitride layer 132 is 30 nanometers to 300 nanometers. In some embodiments, the material of the second oxygen-containing dielectric layer 134 includes, for example, silicon oxynitride, silicon oxide, hafnium oxide or other suitable materials. For example, the second oxygen-containing dielectric layer 134 is SiO x N y , wherein x is 1 to 0.5, and y is 0 to 0.5. In some embodiments, the second oxygen-containing dielectric layer 134 has a thickness of 50 nanometers to 200 nanometers.

[0082] The fourth gate dielectric layer 140 is located between the second semiconductor layer 240 and the third gate 250. The fourth gate dielectric layer 140 is a single layer or multilayer structure. In the present embodiment, the material of the fourth gate dielectric layer 140 includes, for example, silicon oxynitride, silicon oxide, hafnium oxide or other suitable materials. In some embodiments, the thickness of the fourth gate dielectric layer 140 is 50 nanometers to 200 nanometers.

[0083] The protective layer 150 covers the third gate 250. The protective layer 150 is a single layer or multi-layer structure. In this embodiment, the material of the protective layer 150 includes silicon oxynitride, silicon oxide, silicon nitride or other suitable materials. In some embodiments, the thickness of the protective layer 150 is 100 nanometers to 600 nanometers.

[0084] In the insulating structure 100, the first contact hole CH1 and the second contact hole CH2 penetrate the second gate dielectric layer 120, the third gate dielectric layer 130, the fourth gate dielectric layer 140 and the protection layer 150. The first contact hole CH1 and the second contact hole CH2 overlap the first source region 222 and the first drain region 226 of the first semiconductor layer 220 in the normal direction ND.

[0085] In the insulating structure 100, the third contact hole CH3 and the fourth contact hole CH4 penetrate the fourth gate dielectric layer and the protective layer 150. The third contact hole CH3 and the fourth contact hole CH4 overlap the second source region 242 and the second drain region 246 of the second semiconductor layer 240 in the normal direction ND of the top surface of the substrate SB. The second semiconductor layer 240 is located between the first contact hole CH1 and the second contact hole CH2, and the second semiconductor layer 240 is separated from the first contact hole CH1 and the second contact hole CH2.

[0086] In the insulating structure 100, the fifth contact hole CH5 penetrates the first gate dielectric layer 110 and the second gate dielectric layer 120, and the sixth contact hole CH6 penetrates the third gate dielectric layer 130 and the fourth gate dielectric layer 140. The second gate 230 is filled in the fifth contact hole CH5 to be electrically connected to the first gate 210, and the third gate 250 is filled in the sixth contact hole CH6 to be electrically connected to the second gate 230.

[0087] The source 262 and the drain 264 are respectively filled into the first contact hole CH1 and the second contact hole CH2 to respectively electrically connect the first source region 222 and the first drain region 226 of the first semiconductor layer 220, and the source 262 and the drain 264 are respectively filled into the third contact hole CH3 and the fourth contact hole CH4 to respectively electrically connect the second source region 242 and the second drain region 246 of the second semiconductor layer 240. The materials of the source 262 and the drain 264 include metals such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, etc., the above alloys, the above metal oxides, the above metal nitrides, or the above combinations or other conductive materials. For example, the source 262 and the drain 264 are respectively stacked layers of titanium metal, aluminum metal, and titanium metal.

[0088] Based on the above, the semiconductor device 10 includes a first semiconductor layer 220 and a second semiconductor layer 240, thereby dispersing the current between the source 262 and the drain 264 and improving the negative effects caused by current stress or hot carrier effects. In addition, the driving voltage of the semiconductor device 10 can be smaller than that of a dual-gate thin film transistor or a single-gate thin film transistor, so that better results can be obtained in a PBTS (Positive Bias Temperature Stress) test. The aforementioned PBTS test is a test that measures the change in threshold voltage under the condition of loading a positive voltage.

[0089] Figures 2A to 2G yes Figures 1A to 1C A schematic cross-sectional view of a method for manufacturing a semiconductor device.

[0090] Please refer to Figure 2A , a first gate 210 is formed on the substrate SB.

[0091] Please refer to Figure 2B , forming a first gate dielectric layer 110 on the first gate electrode 210 . The method of forming the first gate dielectric layer 110 includes forming a first nitride layer 112 on the first gate electrode 210 and forming a first oxygen-containing dielectric layer 114 on the first nitride layer 112 .

[0092] A first semiconductor material layer 220 ′ is formed on the first gate dielectric layer 110 .

[0093] Please refer to Figure 2C , forming a second gate dielectric layer 120 on the first semiconductor material layer 220'. Forming a second gate 230 on the second gate dielectric layer 120. Using the second gate 230 as a mask, performing a doping process P1 on the first semiconductor material layer 220' to form a first semiconductor layer 220 including a first source region 222, a first channel region 224 and a first drain region 226, wherein the first channel region 224 is aligned with the second gate 230. In some embodiments, the doping process P1 includes a hydrogen plasma process, an ion implantation process or other suitable process. It should be noted that, in some embodiments, the hydrogen element in the formed gate dielectric layer, the subsequently formed gate dielectric layer and / or the protective layer can diffuse into the first semiconductor layer 220 during the manufacturing process, thereby changing the hydrogen content in the first semiconductor layer 220.

[0094] In some embodiments, before forming the second gate 230, an etching process is performed to form a fifth contact hole penetrating the first gate dielectric layer 110 and the second gate dielectric layer 120 (see Figure 1C ), wherein the fifth contact hole exposes the first gate 210. Then, a second gate 230 is formed in the fifth contact hole to be electrically connected to the first gate 210.

[0095] Please refer to Figure 2D , forming a third gate dielectric layer 130 on the second gate electrode 230 . The method of forming the third gate dielectric layer 130 includes forming a second nitride layer 132 on the second gate electrode 230 and forming a second oxygen-containing dielectric layer 134 on the second nitride layer 132 .

[0096] A second semiconductor material layer 240 ′ is formed on the third gate dielectric layer 130 .

[0097] Please refer to Figure 2E , a fourth gate dielectric layer 140 is formed on the second semiconductor material layer 240 ′.

[0098] A third gate 250 is formed on the fourth gate dielectric layer 140. Using the third gate 250 as a mask, a doping process P2 is performed on the second semiconductor material layer 240' to form a second semiconductor layer 240 including a second source region 242, a second channel region 244, and a second drain region 246, wherein the second channel region 244 is aligned with the third gate 250. In some embodiments, the doping process P2 includes a hydrogen plasma process, an ion implantation process, or other suitable processes. In some embodiments, hydrogen elements in the formed gate dielectric layer, the subsequently formed gate dielectric layer, and / or the protective layer can diffuse into the second semiconductor layer 240 during the process, thereby changing the hydrogen content in the second semiconductor layer 240.

[0099] In some embodiments, before forming the third gate 250, an etching process is performed to form a sixth contact hole penetrating the third gate dielectric layer 130 and the fourth gate dielectric layer 140 (see Figure 1C ), wherein the sixth contact hole exposes the second gate 230. Then, a third gate 250 is formed in the sixth contact hole to be electrically connected to the second gate 230.

[0100] Please refer to Figure 2F , forming a protection layer 150 on the third gate 250. In some embodiments, the protection layer 150 contains hydrogen elements, and during or after forming the protection layer 150, a heat treatment is performed to diffuse the hydrogen elements in the protection layer 150 downward to the second semiconductor layer 240, thereby reducing the resistivity of the second semiconductor layer 240.

[0101] Please refer to Figure 2G , a patterning process is performed to form an insulating structure 100 having a first contact hole CH1, a second contact hole CH2, a third contact hole CH3, and a fourth contact hole CH4. The first contact hole CH1 and the second contact hole CH2 expose the first source region 222 and the first drain region 226 of the first semiconductor layer 220, respectively, and the third contact hole CH3 and the fourth contact hole CH4 expose the second source region 242 and the second drain region 246 of the second semiconductor layer 240, respectively. In some embodiments, the patterning process includes: forming a patterned photoresist layer (not shown) on the protection layer 150, and then performing an etching process on the protection layer 150, the fourth gate dielectric layer 140, the third gate dielectric layer 130, and the second gate dielectric layer 120 using the patterned photoresist layer as a mask, and the first semiconductor layer 220 and the second semiconductor layer 240 can be used as etching stop layers in the etching process. In other words, the first contact hole CH1 , the second contact hole CH2 , the third contact hole CH3 , and the fourth contact hole CH4 may be formed together in the same etching process.

[0102] Finally, please return to Figure 1B , a source electrode 262 and a drain electrode 264 are formed on the protection layer 150 , and the source electrode 262 and the drain electrode 264 are filled into the first contact hole CH1 , the second contact hole CH2 , the third contact hole CH3 and the fourth contact hole CH4 . At this point, the semiconductor device 10 is substantially completed.

[0103] Figure 3A is a top view of a semiconductor device 20 according to an embodiment of the present invention. Figure 3B It is along Figure 3A A schematic cross-sectional view of line AA'. Figure 3C It is along Figure 3A It must be noted that: FIG. 3A to FIG. 3C The implementation examples are used Figures 1A to 1C The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0104] FIG. 3A to FIG. 3C The semiconductor device 20 and Figures 1A to 1C The main difference between the semiconductor device 10 and the semiconductor device 20 is that the second semiconductor layer 240 of the semiconductor device 20 has a first through hole TH1 and a second through hole TH2.

[0105] Please refer to FIG. 3A to FIG. 3C In the present embodiment, the length SL2 of the second source region 242 and the length DL2 of the second drain region 246 are substantially equal to the length SL1 of the first source region 222 and the length DL1 of the first drain region 226, and the length of the second semiconductor layer 220 (the sum of the length SL2, the length CL2 and the length DL2) is substantially equal to the length of the first semiconductor layer 220 (the sum of the length SL1, the length CL1 and the length DL1).

[0106] The first through hole TH1 and the second through hole TH2 are respectively located at the second source region 242 and the second drain region 246 of the second semiconductor layer 240. The first through hole TH1 and the second through hole TH2 overlap the first source region 222 and the first drain region 226 of the first semiconductor layer 220 in the normal direction ND of the top surface of the substrate SB.

[0107] The first contact hole CH1 and the second contact hole CH2 penetrate the second gate dielectric layer 120 and the third gate dielectric layer 130. The first contact hole CH1 and the second contact hole CH2 overlap the first through hole TH1 and the second through hole TH2 in the normal direction ND of the top surface of the substrate SB.

[0108] The third contact hole CH3 and the fourth contact hole CH4 penetrate the fourth gate dielectric layer 140 and the protective layer 150. The third contact hole CH3 and the fourth contact hole CH4 overlap the first through hole TH1 and the second through hole TH2 in the normal direction ND of the top surface of the substrate SB, respectively. The first through hole TH1 is located between the first contact hole CH1 and the third contact hole CH3, and the second through hole TH2 is located between the second contact hole CH2 and the fourth contact hole CH4.

[0109] The source electrode 262 is filled into the first contact hole CH1, passes through the first through hole TH1 and is filled into the third contact hole CH3 to electrically connect the first source region 222 of the first semiconductor layer 220 and the second source region 242 of the second semiconductor layer 240. The drain electrode 264 is filled into the second contact hole CH2, passes through the second through hole TH2 and is filled into the fourth contact hole CH4 to electrically connect the first drain region 226 of the first semiconductor layer 220 and the second drain region 246 of the second semiconductor layer 240.

[0110] In the present embodiment, the width of the third contact hole CH3 and the width of the fourth contact hole CH4 are respectively greater than the width of the first through hole TH1 and the width of the second through hole TH2. Therefore, in addition to contacting the sidewalls of the first through hole TH1 and the sidewalls of the second through hole TH2, the source 262 and the drain 264 also contact a portion of the upper surface of the second semiconductor layer 240, thereby increasing the contact area between the source 262 and the second semiconductor layer 240 and the contact area between the drain 264 and the second semiconductor layer 240. In the present embodiment, the contact area between the source 262 and the second semiconductor layer 240 is annular, and the contact area between the drain 264 and the second semiconductor layer 240 is also annular.

[0111] In the present embodiment, the first contact hole CH1 overlaps with the third contact hole CH3, so the distance between the source 262 and the first channel region 224 is approximately equal to the distance between the source 262 and the second channel region 244. Similarly, the second contact hole CH2 overlaps with the fourth contact hole CH4, so the distance between the drain 264 and the first channel region 224 is approximately equal to the distance between the drain 264 and the second channel region 244. Thus, the current can be more evenly distributed to the first semiconductor layer 220 and the second semiconductor layer 240.

[0112] Based on the above, the semiconductor device 20 includes the first semiconductor layer 220 and the second semiconductor layer 240, thereby dispersing the current between the source 262 and the drain 264 and improving the negative effects caused by the current stress or the hot carrier effect. In addition, the driving voltage of the semiconductor device 20 can be smaller than that of the dual-gate thin film transistor or the single-gate thin film transistor, so the semiconductor device 20 can obtain better results in the PBTS test.

[0113] FIG. 4A to FIG. 4E yes FIG. 3A to FIG. 3C A cross-sectional schematic diagram of a method for manufacturing a semiconductor device 20 is shown.

[0114] Please refer to Figure 4A , continued Figure 2C The method of forming the third gate dielectric layer 130 includes forming a second nitride layer 132 on the second gate 230 and forming a second oxygen-containing dielectric layer 134 on the second nitride layer 132.

[0115] The second semiconductor material layer 240' is formed on the third gate dielectric layer 130. In the present embodiment, the second semiconductor material layer 240' has a first through hole TH1 and a second through hole TH2.

[0116] Please refer to Figure 4B , forming a fourth gate dielectric layer 140 on the second semiconductor material layer 240 ′. In this embodiment, the fourth gate dielectric layer 140 fills the first through hole TH1 and the second through hole TH2 .

[0117] A third gate 250 is formed on the fourth gate dielectric layer 140. Using the third gate 250 as a mask, a doping process P2 is performed on the second semiconductor material layer 240' to form a second semiconductor layer 240 including a second source region 242, a second channel region 244, and a second drain region 246, wherein the second channel region 244 is aligned with the third gate 250. In some embodiments, the doping process P2 includes a hydrogen plasma process, an ion implantation process, or other suitable processes. In some embodiments, hydrogen elements in the formed gate dielectric layer, the subsequently formed gate dielectric layer, and / or the protective layer can diffuse into the second semiconductor layer 240 during the process, thereby changing the hydrogen content in the second semiconductor layer 240.

[0118] In some embodiments, before forming the third gate 250, an etching process is performed to form a sixth contact hole penetrating the third gate dielectric layer 130 and the fourth gate dielectric layer 140 (see Figure 1C ), wherein the sixth contact hole exposes the second gate 230. Then, a third gate 250 is formed in the sixth contact hole to be electrically connected to the second gate 230.

[0119] Please refer to Figure 4C, a patterned photoresist layer PR is formed on the protective layer 150. The patterned photoresist layer PR includes a first opening OP1 and a second opening OP2, wherein the first opening OP1 and the second opening OP2 overlap the first through hole TH1 and the second through hole TH2 respectively in the normal direction ND of the top surface of the substrate SB. The width of the first opening OP1 is greater than the width of the first through hole TH1, and the width of the second opening OP2 is greater than the width of the second through hole TH2.

[0120] Please refer to Figure 4D , an etching process is performed on the protection layer 150, the fourth gate dielectric layer 140, the third gate dielectric layer 130 and the second gate dielectric layer 120 using the patterned photoresist layer PR as a mask. The first contact hole CH1, the second contact hole CH2, the third contact hole CH3 and the fourth contact hole CH4 can be formed together in the same etching process. In the present embodiment, since the width of the first opening OP1 and the width of the second opening OP2 are respectively greater than the width of the first through hole TH1 and the width of the second through hole TH2, the third contact hole CH3 and the fourth contact hole CH4 expose a portion of the upper surface of the second semiconductor layer 240. The second semiconductor layer 240 also serves as a mask for the etching process, so that the width of the first contact hole CH1 and the width of the second contact hole CH2 are respectively smaller than the width of the third contact hole CH3 and the width of the fourth contact hole CH4. The first semiconductor layer 220 is an etching stop layer for the etching process.

[0121] Please refer to Figure 4E , remove the patterned photoresist layer PR.

[0122] Finally, please return to Figure 3B , a source electrode 262 and a drain electrode 264 are formed on the protection layer 150 , and the source electrode 262 and the drain electrode 264 are filled into the first contact hole CH1 , the second contact hole CH2 , the third contact hole CH3 and the fourth contact hole CH4 . At this point, the semiconductor device 20 is substantially completed.

[0123] Figure 5A is a top view of a semiconductor device 30 according to an embodiment of the present invention. Figure 5B It is along Figure 5A A schematic cross-sectional view of line AA'. Figure 5C It is along Figure 5A It must be noted that: FIG. 5A to FIG. 5C The implementation examples are used FIG. 3A to FIG. 3C The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0124] FIG. 5A to FIG. 5C The semiconductor device 30 and FIG. 3A to FIG. 3C The main difference between the semiconductor device 20 and the semiconductor device 30 is that the second semiconductor layer 240 of the semiconductor device 30 covers a portion of the sidewall of the first contact hole CH1 and a portion of the sidewall of the second contact hole CH2.

[0125] Please refer to FIG. 5A to FIG. 5C , part of the second semiconductor layer 240 extends toward the substrate SB along the sidewall of the first contact hole CH1 at the first contact hole CH1, and part of the second semiconductor layer 240 extends toward the substrate SB along the sidewall of the second contact hole CH2 at the second contact hole CH2. The second semiconductor layer 240 is located between the source 262 and the third gate dielectric layer 130 and between the drain 264 and the third gate dielectric layer 130. In the present embodiment, the second semiconductor layer 240 does not extend beyond the bottom surface of the third gate dielectric layer 130, but the present invention is not limited thereto. In some embodiments, the second semiconductor layer 240 extends beyond the bottom surface of the third gate dielectric layer 130, but the second semiconductor layer 240 does not pass through the second gate dielectric layer 120.

[0126] In this embodiment, by adjusting the contact area between the source 262 and the first semiconductor layer 220, the contact area between the drain 264 and the first semiconductor layer 220, the contact area between the source 262 and the second semiconductor layer 240, and the contact area between the drain 264 and the second semiconductor layer 240, the current can be more evenly distributed to the first semiconductor layer 220 and the second semiconductor layer 240.

[0127] In the present embodiment, the first contact hole CH1 overlaps with the third contact hole CH3, so the distance between the source 262 and the first channel region 224 is approximately equal to the distance between the source 262 and the second channel region 244. Similarly, the second contact hole CH2 overlaps with the fourth contact hole CH4, so the distance between the drain 264 and the first channel region 224 is approximately equal to the distance between the drain 264 and the second channel region 244. Thus, the current can be more evenly distributed to the first semiconductor layer 220 and the second semiconductor layer 240.

[0128] Based on the above, the semiconductor device 30 includes the first semiconductor layer 220 and the second semiconductor layer 240, thereby dispersing the current between the source 262 and the drain 264 and improving the negative effects caused by the current stress or the hot carrier effect. In addition, the driving voltage of the semiconductor device 30 can be smaller than that of the dual-gate thin film transistor or the single-gate thin film transistor, so the semiconductor device 30 can obtain better results in the PBTS test.

[0129] 6A to 6H yes FIG. 5A to FIG. 5C A cross-sectional schematic diagram of a method for manufacturing a semiconductor device 30 is shown.

[0130] Please refer to Fig. 6A , continued Figure 2C The method of forming the third gate dielectric layer 130 includes forming a second nitride layer 132 on the second gate 230 and forming a second oxygen-containing dielectric layer 134 on the second nitride layer 132.

[0131] Please refer to Figure 6B , an etching process is performed to form a first opening CH1′ and a second opening CH2′ penetrating the third gate dielectric layer 130. In this embodiment, the first opening CH1′ and the second opening CH2′ do not penetrate the second gate dielectric layer 120. In this embodiment, the etching process stops at the second gate dielectric layer 120.

[0132] Please refer to Figure 6C , forming a second semiconductor material layer 240' on the third gate dielectric layer 130. The second semiconductor material layer 240' fills the first opening CH1' and the second opening CH2', and contacts the second gate dielectric layer 120. The second semiconductor material layer 240' has a first through hole TH1 and a second through hole TH2. The first through hole TH1 exposes a portion of the second gate dielectric layer 120 at the bottom of the first opening CH1'. The second through hole TH2 exposes a portion of the second gate dielectric layer 120 at the bottom of the second opening CH2'.

[0133] Please refer to Fig.6D , a fourth gate dielectric layer 140 is formed on the second semiconductor material layer 240 ′. The fourth gate dielectric layer 140 fills the first opening CH1 ′ and the second opening CH2 ′ and contacts the second gate dielectric layer 120 .

[0134] A third gate 250 is formed on the fourth gate dielectric layer 140. Using the third gate 250 as a mask, a doping process P2 is performed on the second semiconductor material layer 240' to form a second semiconductor layer 240 including a second source region 242, a second channel region 244, and a second drain region 246, wherein the second channel region 244 is aligned with the third gate 250. In some embodiments, the doping process P2 includes a hydrogen plasma process, an ion implantation process, or other suitable processes. In some embodiments, hydrogen elements in the formed gate dielectric layer, the subsequently formed gate dielectric layer, and / or the protective layer can diffuse into the second semiconductor layer 240 during the process, thereby changing the hydrogen content in the second semiconductor layer 240.

[0135] In some embodiments, before forming the third gate 250, an etching process is performed to form a sixth contact hole penetrating the third gate dielectric layer 130 and the fourth gate dielectric layer 140 (see Figure 1C), wherein the sixth contact hole exposes the second gate 230. Then, a third gate 250 is formed in the sixth contact hole to be electrically connected to the second gate 230.

[0136] Please refer to Fig. 6E , forming a protection layer 150 on the third gate 250 .

[0137] Please refer to Fig. 6F , a patterned photoresist layer PR is formed on the protective layer 150. The patterned photoresist layer PR includes a first opening OP1 and a second opening OP2, wherein the first opening OP1 and the second opening OP2 overlap the first through hole TH1 and the second through hole TH2 respectively in the normal direction ND of the top surface of the substrate SB. The width of the first opening OP1 is greater than the width of the first through hole TH1, and the width of the second opening OP2 is greater than the width of the second through hole TH2.

[0138] Please refer to Figure 6G , an etching process is performed on the protection layer 150, the fourth gate dielectric layer 140, the third gate dielectric layer 130 and the second gate dielectric layer 120 using the patterned photoresist layer PR as a mask. The first contact hole CH1, the second contact hole CH2, the third contact hole CH3 and the fourth contact hole CH4 can be formed together in the same etching process. In the present embodiment, since the width of the first opening OP1 and the width of the second opening OP2 are respectively greater than the width of the first through hole TH1 and the width of the second through hole TH2, the third contact hole CH3 and the fourth contact hole CH4 expose a portion of the upper surface of the second semiconductor layer 240. The second semiconductor layer 240 also serves as a mask for the etching process, so that the width of the first contact hole CH1 and the width of the second contact hole CH2 are respectively smaller than the width of the third contact hole CH3 and the width of the fourth contact hole CH4. The first semiconductor layer 220 is an etching stop layer for the etching process.

[0139] Please refer to Figure 6H , remove the patterned photoresist layer PR.

[0140] Finally, please return to Figure 5B , a source electrode 262 and a drain electrode 264 are formed on the protection layer 150 , and the source electrode 262 and the drain electrode 264 are filled into the first contact hole CH1 , the second contact hole CH2 , the third contact hole CH3 and the fourth contact hole CH4 . At this point, the semiconductor device 30 is substantially completed.

[0141] Fig. 7A is a top view of a semiconductor device 40 according to an embodiment of the present invention. Figure 7B It is along Fig. 7A A schematic cross-sectional view of line AA'. Figure 7C It is along Fig. 7AIt must be noted that: 7A to 7C The implementation examples are used Figures 1A to 1C The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0142] 7A to 7C The semiconductor device 40 and Figures 1A to 1C The main difference between the semiconductor device 10 and the semiconductor device 40 is that the source 262 and the drain 264 of the semiconductor device 40 contact two opposite outer sidewalls of the second semiconductor layer 240 .

[0143] Please refer to 7A to 7C , the first contact hole CH1 and the second contact hole CH2 penetrate the second gate dielectric layer 120 and the third gate dielectric layer 130. The first contact hole CH1 and the second contact hole CH2 are located below two opposite outer sidewalls of the second semiconductor layer 240. The third contact hole CH3 and the fourth contact hole CH4 penetrate the fourth gate dielectric layer 140 and the protective layer 150. The third contact hole CH3 and the fourth contact hole CH4 overlap the first contact hole CH1 and the second contact hole CH2, respectively. The width of the third contact hole CH3 and the width of the fourth contact hole CH4 are respectively greater than the width of the first contact hole CH1 and the width of the second contact hole CH2.

[0144] The source electrode 262 is filled into the first contact hole CH1 and the third contact hole CH3 to electrically connect the first source region 222 of the first semiconductor layer 220 and the second source region 242 of the second semiconductor layer 240. The drain electrode 264 is filled into the second contact hole CH2 and the fourth contact hole CH4 to electrically connect the first drain region 226 of the first semiconductor layer 220 and the second drain region 246 of the second semiconductor layer 240. The source electrode 262 and the drain electrode 264 contact two opposite outer sidewalls and the upper surface of the second semiconductor layer 240.

[0145] In the present embodiment, the first contact hole CH1 overlaps with the third contact hole CH3, so the distance between the source 262 and the first channel region 224 is approximately equal to the distance between the source 262 and the second channel region 244. Similarly, the second contact hole CH2 overlaps with the fourth contact hole CH4, so the distance between the drain 264 and the first channel region 224 is approximately equal to the distance between the drain 264 and the second channel region 244. Thus, the current can be more evenly distributed to the first semiconductor layer 220 and the second semiconductor layer 240.

[0146] Based on the above, the semiconductor device 40 includes the first semiconductor layer 220 and the second semiconductor layer 240, thereby dispersing the current between the source 262 and the drain 264 and improving the negative effects caused by the current stress or the hot carrier effect. In addition, the driving voltage of the semiconductor device 40 can be smaller than that of the dual-gate thin film transistor or the single-gate thin film transistor, so the semiconductor device 40 can obtain better results in the PBTS test.

[0147] Figure 8 yes 7A to 7C A cross-sectional schematic diagram of a method for manufacturing a semiconductor device 40 is shown.

[0148] Please refer to Figure 8 , continued Figure 2F , a patterning process is performed to form an insulating structure 100 having a first contact hole CH1, a second contact hole CH2, a third contact hole CH3, and a fourth contact hole CH4. The first contact hole CH1 and the second contact hole CH2 expose the first source region 222 and the first drain region 226 of the first semiconductor layer 220, respectively, and the third contact hole CH3 and the fourth contact hole CH4 expose the second source region 242 and the second drain region 246 of the second semiconductor layer 240, respectively. In some embodiments, the patterning process includes: forming a patterned photoresist layer (not shown) on the protection layer 150, and then performing an etching process on the protection layer 150, the fourth gate dielectric layer 140, the third gate dielectric layer 130, and the second gate dielectric layer 120 using the patterned photoresist layer as a mask, the second semiconductor layer 240 can be used as a mask for the etching process, and the first semiconductor layer 220 can be used as an etching stop layer for the etching process. In other words, the first contact hole CH1 , the second contact hole CH2 , the third contact hole CH3 , and the fourth contact hole CH4 may be formed together in the same etching process.

[0149] Finally, please return to Figure 7B , a source electrode 262 and a drain electrode 264 are formed on the protection layer 150 , and the source electrode 262 and the drain electrode 264 are filled into the first contact hole CH1 , the second contact hole CH2 , the third contact hole CH3 and the fourth contact hole CH4 . At this point, the semiconductor device 40 is substantially completed.

[0150] Fig. 9 is a schematic diagram of an equivalent circuit of a semiconductor device according to an embodiment of the present invention. For example, Fig. 9 For example Figures 1A to 1C The semiconductor device 10, FIG. 3A to FIG. 3C The semiconductor device 20, FIG. 5A to FIG. 5C The semiconductor device 30 or 7A to 7C Schematic diagram of an equivalent circuit of a semiconductor device 40.

[0151] Please refer to Fig. 9 , the equivalent circuit of the semiconductor device is substantially equal to two switching elements TFT1 and TFT2 connected together. The switching element TFT1 includes a gate G1, the switching element TFT2 includes a gate G3, and the switching element TFT1 and the switching element TFT2 share the gate G2. The switching element TFT1 and the switching element TFT2 share a source S, and the switching element TFT1 and the switching element TFT2 share a drain D. The current is distributed to the channel of the switching element TFT1 (e.g., the first semiconductor layer) and the channel of the switching element TFT2 (e.g., the second semiconductor layer), thereby improving the negative effects caused by current stress or hot carrier effects.

Claims

1. A semiconductor device comprising: a first gate, a second gate and a third gate; A first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer is located between the first gate and the second gate, the second gate is located between the first semiconductor layer and the second semiconductor layer, and the second semiconductor layer is located between the second gate and the third gate; A source electrode electrically connected to the first semiconductor layer and the second semiconductor layer; A drain electrode electrically connected to the first semiconductor layer and the second semiconductor layer, wherein the second semiconductor layer has a first through hole and a second through hole, the source electrode passes through the first through hole to electrically connect to the first semiconductor layer, and the drain electrode passes through the second through hole to electrically connect to the first semiconductor layer; as well as Insulation structure, including: A first gate dielectric layer is located between the first gate and the first semiconductor layer; A second gate dielectric layer is located between the first semiconductor layer and the second gate; A third gate dielectric layer is located between the second gate and the second semiconductor layer, wherein a first contact hole and a second contact hole penetrate the second gate dielectric layer and the third gate dielectric layer, and the first contact hole and the second contact hole overlap the first through hole and the second through hole respectively, and the source and the drain are filled in the first contact hole and the second contact hole respectively; and A fourth gate dielectric layer is located between the second semiconductor layer and the third gate, wherein a third contact hole and a fourth contact hole penetrate the fourth gate dielectric layer, and the third contact hole and the fourth contact hole overlap the first through hole and the second through hole respectively, the source and the drain are filled in the third contact hole and the fourth contact hole respectively, wherein the second semiconductor layer covers a portion of the side wall of the first contact hole and a portion of the side wall of the second contact hole. 2 . The semiconductor device as claimed in claim 1 , wherein the insulating structure covers the first gate, the second gate, the third gate, the first semiconductor layer and the second semiconductor layer. 3 . The semiconductor device as claimed in claim 1 , wherein a width of the third contact hole and a width of the fourth contact hole are respectively greater than a width of the first through hole and a width of the second through hole. 4 . The semiconductor device as claimed in claim 1 , wherein the second semiconductor layer is located between the source and the third gate dielectric layer and between the drain and the third gate dielectric layer. 5 . The semiconductor device as claimed in claim 1 , wherein the source and the drain contact sidewalls of the second semiconductor layer at the first contact hole.

6. The semiconductor device according to claim 5, further comprising: The insulating structure covers the first gate, the second gate, the third gate, the first semiconductor layer and the second semiconductor layer, wherein the first contact hole and the second contact hole are located below two opposite outer side walls of the second semiconductor layer. 7 . The semiconductor device as claimed in claim 6 , wherein a width of the third contact hole and a width of the fourth contact hole are respectively greater than a width of the first contact hole and a width of the second contact hole. 8 . The semiconductor device as claimed in claim 6 , wherein the source and the drain contact a sidewall and an upper surface of the second semiconductor layer at the first contact hole. 9 . The semiconductor device as claimed in claim 1 , wherein the first gate, the second gate and the third gate are electrically connected to each other. 10 . The semiconductor device as claimed in claim 1 , wherein the first semiconductor layer and the second semiconductor layer comprise the same material. 11 . The semiconductor device as claimed in claim 1 , wherein the first semiconductor layer and the second semiconductor layer comprise the same thickness.

12. The semiconductor device of claim 1 , wherein the first gate dielectric layer comprises a first nitride layer and a first oxygen-containing dielectric layer, wherein the first nitride layer contacts the first gate electrode and the first oxygen-containing dielectric layer contacts the first semiconductor layer; wherein the third gate dielectric layer comprises a second nitride layer and a second oxygen-containing dielectric layer, wherein the second nitride layer contacts the second gate electrode and the second oxygen-containing dielectric layer contacts the second semiconductor layer.

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