power supply clamping

Abstract

This application discloses a power clamping device. An ESD power clamping device includes: an ESD detection circuit; a control circuit coupled to the ESD detection circuit; a field-effect transistor (FET) coupled to the control circuit; and an impedance element coupled to the FET. The FET includes: a drain terminal coupled to a first power node; a gate terminal coupled to the control circuit; a source terminal coupled to a second power node via the impedance element; and a body terminal coupled to the second power node.

Description

Technical Field

[0001] This disclosure generally relates to power clamping. Background Technology

[0002] Electrostatic discharge (ESD) power clamping devices using bigFETs have demonstrated excellent ESD protection performance. However, current leakage in bigFETs limits their protection performance. As integrated circuit manufacturing processes shrink, this limitation will become even more critical to the performance of integrated circuits. Summary of the Invention

[0003] According to a first aspect of this disclosure, an electrostatic discharge (ESD) power clamping device is provided, comprising: an ESD detection circuit; a control circuit coupled to the ESD detection circuit; a field-effect transistor (FET) coupled to the control circuit; and an impedance element coupled to the FET, wherein the FET includes: a drain terminal coupled to a first power node; a gate terminal coupled to an output terminal of the control circuit; a source terminal coupled to a second power node via the impedance element; and a body terminal coupled to the second power node.

[0004] According to a second aspect of this disclosure, an electrostatic discharge (ESD) protection circuit is provided, comprising: a first protection circuit including an ESD power clamping device; and a second protection circuit including an impedance element coupled to the ESD power clamping device of the first protection circuit, wherein the ESD power clamping device of the first protection circuit includes: an ESD detection circuit; a control circuit coupled to the ESD detection circuit; and a field-effect transistor (FET) coupled between a first power node and a second power node, wherein the FET includes: a drain terminal coupled to the first power node; a gate terminal coupled to the output terminal of the control circuit; a source terminal coupled to the second power node via the impedance element of the second protection circuit; and a body terminal coupled to the second power node.

[0005] According to a third aspect of this disclosure, a method for operating an ESD protection circuit is provided, the ESD protection circuit including an ESD detection circuit, a control circuit, and a field-effect transistor (FET), the method comprising: providing a first power supply voltage to a first node of the ESD detection circuit of the ESD protection circuit, and providing a second power supply voltage to a second node of the ESD detection circuit; outputting a voltage from the ESD detection circuit to an input node of the control circuit of the ESD protection circuit; turning on or off the FET of the ESD protection circuit; and providing the second power supply voltage to a body terminal of the FET and a terminal of an impedance element coupled to the FET. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0007] Figure 1 This is a schematic diagram illustrating an integrated circuit including an exemplary ESD power clamping device according to some embodiments of the present disclosure.

[0008] Figure 2 This is a schematic cross-sectional view of a FET of an ESD power clamping device under a non-zero source-body voltage according to some embodiments of the present disclosure.

[0009] Figure 3 This is a schematic diagram illustrating an exemplary ESD power clamping device including a diode as an impedance element, according to some embodiments of the present disclosure.

[0010] Figure 4 This is a schematic diagram illustrating an exemplary ESD power clamping device comprising a combination of resistors and diodes as impedance elements, according to some embodiments of the present disclosure.

[0011] Figure 5 This is a schematic diagram illustrating an exemplary ESD power clamping device comprising a combination of inductors and diodes as impedance elements, according to some embodiments of the present disclosure.

[0012] Figure 6 This is a schematic diagram illustrating an exemplary ESD power clamping device including a resistor as an impedance element according to some embodiments of the present disclosure.

[0013] Figure 7 This is a flowchart illustrating a method for operating an ESD power clamping device according to some embodiments of the present disclosure.

[0014] Figure 8 This is a schematic diagram illustrating an exemplary ESD protection circuit according to some embodiments of the present disclosure, the exemplary ESD protection circuit including a first circuit having an ESD power clamping device and a second circuit having a diode.

[0015] Figure 9 This is a schematic diagram showing an ESD protection circuit including a voltage divider, a first circuit including a first power clamping device, and a second circuit including a second power clamping device.

[0016] Figure 10This is a flowchart illustrating a method for operating an ESD protection circuit according to some embodiments of the present disclosure, the ESD protection circuit including a first circuit having an ESD power clamping device and a second circuit having a diode.

[0017] Figure 11 This is a flowchart illustrating a method for operating an ESD protection circuit according to some embodiments of the present disclosure. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] The terms used in this specification generally have their ordinary meaning in the art and in the specific context in which each term is used. The use of examples in this specification, including examples of any terms discussed herein, is merely illustrative and in no way intended to limit the scope and meaning of this disclosure or any exemplary terminology. Similarly, this disclosure is not limited to the various embodiments given in this specification.

[0020] Although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, without departing from the scope of the embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0021] In this document, the term "coupling" may also be referred to as "electrical coupling," and the term "connection" may be referred to as "electrical connection." "Coupling" and "connection" may also be used to describe two or more elements cooperating or interacting with each other.

[0022] ESD power clamping devices using bigFETs offer excellent ESD protection performance. However, current leakage in bigFETs is not negligible. The embodiments described in this disclosure provide techniques for suppressing leakage current in power clamping devices without increasing device size and cost.

[0023] refer to Figure 1 , Figure 1 This is a schematic diagram illustrating an integrated circuit including an exemplary ESD power clamping device 100 according to some embodiments of the present disclosure. The ESD power clamping device 100 may be coupled to core circuitry 160 and provides protection to core circuitry 160 during an ESD event by shunting ESD current from the power domain to the ground domain. Since the focus of this disclosure is on the ESD power clamping device 100, core circuitry 160 will be omitted in the following figures.

[0024] refer to Figure 1 The ESD power clamping device 100 includes an ESD detection circuit 102. In some embodiments, the ESD detection circuit 102 may include a resistor 104 and a capacitor 106. The resistor 104 and capacitor 106 may be coupled together to form a resistance-capacitance (RC) time constant circuit. The ESD detection circuit 102 is coupled between a first power supply voltage VDD and a second power supply voltage VSS. In some embodiments, VDD may be any voltage suitable for the operation of the core circuit 160. VSS may be ground. The RC time constant circuit is not limited to a resistor and a capacitor as shown. The RC time constant circuit may include any suitable number of capacitors or capacitive devices. The RC time constant circuit may also include any suitable number of resistors or resistive devices.

[0025] ESD power clamping device 100 includes control circuitry 108. Control circuitry 108 includes input terminal 114 and output terminal 116. In some embodiments, control circuitry 108 may be an inverter including a P-channel metal-oxide-semiconductor (PMOS) transistor 110 and an N-channel metal-oxide-semiconductor (NMOS) transistor 112. The source terminal of PMOS transistor 110 may be coupled to the power supply voltage VDD. The drain terminal of PMOS transistor 110 may be coupled to the output terminal 116 of inverter 108. The source terminal of NMOS transistor 110 may be coupled to the power supply voltage VSS. The drain terminal of NMOS transistor 110 may be coupled to the output terminal 116 of inverter 108. Input terminal 114 of inverter 108 may be coupled to ESD detection circuitry 102.

[0026] ESD power clamping device 100 includes a field-effect transistor (FET) 118. The drain terminal of FET 118 can be coupled to ESD detection circuitry 102, control circuitry 108, and power supply voltage VDD. As described below, the source terminal of FET 118 can be coupled to the power supply voltage VSS via an impedance element. The gate terminal of FET 118 can be coupled to the output terminal 116 of control circuitry 108. The bulk terminal of FET 118 can be coupled to the power supply voltage VSS, as... Figure 1As shown in label 122.

[0027] In some embodiments, FET 118 may be a large field-effect transistor (bigFET). A bigFET may be an NMOS device (e.g., an NMOS transistor) with a large channel width to absorb ESD current. A bigFET may also be a PMOS device (e.g., a PMOS transistor) with a large channel width to absorb ESD current.

[0028] ESD power clamping device 100 includes an impedance element 120. One end of the impedance element 120 is coupled to the source terminal of FET 118, and the other end of the impedance element 120 is coupled to the power supply voltage VSS.

[0029] During normal operation without an ESD pulse, the supply voltage VDD can be coupled to the RC time constant circuit 102. Since there is no significant current flowing into or out of capacitor 106, the voltage state at input 114 of inverter 108 is high. Inverter 108 can then output a low voltage to the gate terminal of FET 118 via output 116, thereby turning off FET 118. With FET 118 off, the supply voltage VDD can ideally be supplied to the core circuitry 160 for operation.

[0030] During an ESD event, the voltage state at input 114 of the inverter is low. Inverter 108 can then output a high voltage to the gate terminal of FET 118 via output 116, thereby turning on FET 118. If an ESD pulse occurs in the core circuitry 160, the turned-on FET 118 can discharge the ESD pulse to the supply voltage VSS (e.g., ground). Resistor 104 and capacitor 106 in the ESD detection circuitry 102 can provide an RC time constant (e.g., a few microseconds) to maintain or sustain FET 118 on to discharge the ESD pulse to ground. In this embodiment, because impedance element 120 is positioned between the source terminal of FET 118 and the supply voltage VSS, a voltage drop occurs across impedance element 120. On the other hand, the body of FET 118 is coupled to the supply voltage VSS without an impedance element. Therefore, the voltage drop across impedance element 120 creates a voltage difference (VSB) between the source and body of FET 118. The voltage difference between the source and body of FET 118 will be referred to in this disclosure as the "source-body voltage". This source-body voltage VSB induces a body effect in FET 118, thereby suppressing leakage current in FET 118, as described below. Figure 2 Further discussion is needed.

[0031] refer to Figure 2 , Figure 2This is a schematic cross-sectional view of a FET 200 of an ESD power clamping device under a non-zero source-body voltage according to some embodiments of the present disclosure. In these exemplary embodiments, the FET 200 is an NMOS transistor. Figure 2 The NMOS transistor 200 in the middle can be Figure 1 FET 118 in the middle.

[0032] refer to Figure 2 FET 200 includes a drain terminal 202, a gate terminal 204, a source terminal 206, a body terminal 208, and a depletion region 212 between the source terminal 206 and the drain terminal 202. FET 200 can conduct current during an ESD event. Transistor 200 has a non-zero source-body voltage VSB 210 between the source terminal 206 and the body terminal 208. This source-body voltage creates an expanded depletion region 212 compared to the depletion region (not shown) of a FET with a zero source-body voltage. This expanded depletion region, in turn, increases the threshold voltage, and the increased threshold voltage suppresses source-drain leakage current. Figure 2 The suppressed source-drain leakage current Isoff 214 compared to the source-drain leakage current of a FET with zero source-body voltage is shown. Two contributions to quiescent current leakage in a transistor may exist: the body leakage current Iboff and the source-drain leakage current Isoff. The discussion in this disclosure focuses on the source-drain leakage current Isoff, but the effects of the disclosed embodiments are not limited to suppressing the source-drain leakage current Isoff.

[0033] As described above Figure 1 The subject of discussion Figure 2 The non-zero source-body voltage VSB 210 of transistor 200 is determined by the voltage set at the source terminal (e.g., Figure 2 An impedance element 120 is generated between the source terminal 206 of the FET in the power clamping device and the voltage source VSS (e.g., ground). By utilizing the impedance element between the source terminal of the FET and ground in the power clamping device, leakage current in the FET of the power clamping device is effectively suppressed, thereby improving the ESD protection performance of the power clamping device. Furthermore, by utilizing a simple circuit solution, rather than manufacturing or developing new devices, ESD protection can be provided without increasing the size or cost of the power clamping device.

[0034] Figure 2 Only the NMOS transistor is used as Figure 1 An example of a power clamping device, FET 118, is shown. However, FET 118 is not limited to NMOS transistors. FET 118 can be a PMOS transistor or any other type of transistor.

[0035] refer to Figure 3 , Figure 3 This is a schematic diagram illustrating an exemplary ESD power clamping device 300 according to some embodiments of the present disclosure. The ESD power clamping device 300 includes an ESD detection circuit 302. In some embodiments, the ESD detection circuit 302 may include a resistor 304 and a capacitor 306, the capacitor 306 being coupled to the resistor 304 to form an RC time constant circuit. The ESD detection circuit 302 is coupled between a first power supply voltage VDD and a second power supply voltage VSS. In some embodiments, VDD may be any voltage suitable for operation of a core circuit (not shown). VSS may be ground. The ESD detection circuit 302 is similar to... Figure 1 The ESD detection circuit 102 is described, and for simplicity, a detailed description of the ESD detection circuit 302 is omitted here. The ESD power clamping device 300 includes a control circuit 308, which includes a PMOS transistor 310 and an NMOS transistor 312 (to form an inverter), coupled to the input terminal 314 and the output terminal 316 of the ESD detection circuit 302. The control circuit 308 is similar to... Figure 1 The control circuit 108 is described in detail here.

[0036] refer to Figure 3 The ESD power clamping device 300 includes a FET 318 and a diode 320. The drain terminal of the FET 318 can be coupled to the ESD detection circuit 302, the control circuit 308, and the power supply voltage VDD. The gate terminal of the FET 318 can be coupled to the output terminal 316 of the control circuit 308. The source terminal of the FET 318 can be coupled to one terminal of the diode 320. The other terminal of the diode 320 can be coupled to the power supply voltage VSS. The body terminal of the FET 318 can be coupled to the power supply voltage VSS, as shown below. Figure 3 As shown by label 322 in the diagram. (And...) Figure 1 In comparison, diode 320 plays a role Figure 1 The impedance element 120 serves to generate the source-body voltage VSB for the FET 318 to suppress leakage current in the FET 318. Diode 320 can be any diode that provides the appropriate impedance required by the ESD power clamping device 300.

[0037] refer to Figure 4 , Figure 4This is a schematic diagram illustrating an exemplary ESD power clamping device 400 according to some embodiments of the present disclosure. The ESD power clamping device 400 includes an ESD detection circuit 402. In some embodiments, the ESD detection circuit 402 may include a resistor 404 and a capacitor 406, the capacitor 406 being coupled to the resistor 404 to form an RC time constant circuit. The ESD detection circuit 402 is coupled between a first power supply voltage VDD and a second power supply voltage VSS. In some embodiments, VDD may be any voltage suitable for operation of a core circuit (not shown). VSS may be ground. The ESD detection circuit 402 is similar to... Figure 1 The ESD detection circuit 102 is described in detail here, but a detailed description of the ESD detection circuit 402 is omitted. The ESD power clamping device 400 includes a control circuit 408, which includes a PMOS transistor 410 and an NMOS transistor 412 (to form an inverter), coupled to the input terminal 414 and the output terminal 416 of the ESD detection circuit 402. The control circuit 408 is similar to... Figure 1 The control circuit 108 is described in detail here, but the detailed description of the control circuit 408 is omitted.

[0038] refer to Figure 4 The ESD power clamping device 400 includes a FET 418, a resistor 424, and a diode 420. The drain terminal of the FET 418 can be coupled to the ESD detection circuit 402, the control circuit 408, and the power supply voltage VDD. The gate terminal of the FET 418 can be coupled to the output terminal 416 of the control circuit 408. The source terminal of the FET 418 can be coupled to one end of the resistor 424. The other end of the resistor 424 can be coupled to one terminal of the diode 420. The other terminal of the diode 420 can be coupled to the power supply voltage VSS. The body terminal of the FET 418 can be coupled to the power supply voltage VSS, as shown below. Figure 4 As shown by label 422 in the diagram. (And...) Figure 1 In comparison, the combination of resistor 424 and diode 420 plays a more effective role. Figure 1 The impedance element 120 serves to generate the source-body voltage VSB for the FET 418, thereby suppressing leakage current in the FET 418. Resistor 424 can be any resistor that provides the appropriate resistance required for the power clamping device 400. Diode 420 can be any diode that provides the appropriate impedance for the power clamping device 400.

[0039] refer to Figure 5 , Figure 5This is a schematic diagram illustrating an exemplary ESD power clamping device 500 according to some embodiments of the present disclosure. The ESD power clamping device 500 includes an ESD detection circuit 502. In some embodiments, the ESD detection circuit 502 may include a resistor 504 and a capacitor 506, the capacitor 506 being coupled to the resistor 504 to form an RC time constant circuit. The ESD detection circuit 502 is coupled between a first power supply voltage VDD and a second power supply voltage VSS. In some embodiments, VDD may be any voltage suitable for operation of a core circuit (not shown). VSS may be ground. The ESD detection circuit 502 is similar to... Figure 1 The ESD detection circuit 102 is described in detail here, but a detailed description of the ESD detection circuit 502 is omitted. The ESD power clamping device 500 includes a control circuit 508, which includes a PMOS transistor 510 and an NMOS transistor 512 (to form an inverter), coupled to the input terminal 514 and the output terminal 516 of the ESD detection circuit 502. The control circuit 508 is similar to... Figure 1 The control circuit 108 is described in detail here, but the detailed description of the control circuit 508 is omitted.

[0040] refer to Figure 5 The ESD power clamping device 500 includes a FET 518, an inductor 524, and a diode 520. The drain terminal of the FET 518 can be coupled to the ESD detection circuit 502, the control circuit 508, and the power supply voltage VDD. The gate terminal of the FET 518 can be coupled to the output terminal 516 of the control circuit 508. The source terminal of the FET 518 can be coupled to one end of the inductor 524. The other end of the inductor 524 can be coupled to one terminal of the diode 520. The other terminal of the diode 520 can be coupled to the power supply voltage VSS. The body terminal of the FET 518 can be coupled to the power supply voltage VSS, as shown below. Figure 5 As shown by label 522 in the diagram. (And...) Figure 1 In comparison, the combination of inductor 524 and diode 520 plays a more effective role. Figure 1 The impedance element 120 serves to generate the source-body voltage VSB for the FET 518, thereby suppressing leakage current in the FET 518. Inductor 524 can be any inductor that provides the appropriate inductance required for the ESD power clamping device 500. Diode 520 can be any diode that provides the appropriate impedance for the ESD power clamping device 500.

[0041] refer to Figure 6 , Figure 6This is a schematic diagram illustrating an exemplary ESD power clamping device 600 according to some embodiments of the present disclosure. The ESD power clamping device 600 includes an ESD detection circuit 602. In some embodiments, the ESD detection circuit 602 may include a resistor 604 and a capacitor 606, the capacitor 606 being coupled to the resistor 604 to form an RC time constant circuit. The ESD detection circuit 602 is coupled between a first power supply voltage VDD and a second power supply voltage VSS. In some embodiments, VDD may be any voltage suitable for operation of a core circuit (not shown). VSS may be ground. The ESD detection circuit 602 is similar to... Figure 1 The ESD detection circuit 102 is described in detail here, but a detailed description of the ESD detection circuit 602 is omitted. The ESD power clamping device 600 includes a control circuit 608, which includes a PMOS transistor 610 and an NMOS transistor 612 (to form an inverter), coupled to the input terminal 614 and the output terminal 616 of the ESD detection circuit 602. The control circuit 608 is similar to... Figure 1 The control circuit 108 is described in detail here, but the detailed description of the control circuit 608 is omitted.

[0042] refer to Figure 6 The ESD power clamping device 600 includes a FET 618 and a resistor 620. The drain terminal of the FET 618 can be coupled to the ESD detection circuit 602, the control circuit 608, and the power supply voltage VDD. The gate terminal of the FET 618 can be coupled to the output terminal 616 of the control circuit 608. The source terminal of the FET 618 can be coupled to one end of the resistor 620. The other end of the resistor 620 can be coupled to the power supply voltage VSS. The body terminal of the FET 618 can be coupled to the power supply voltage VSS, as shown below. Figure 6 As shown by reference numeral 622. (And...) Figure 1 In comparison, resistor 620 plays a role Figure 1 The impedance element 120 serves to generate the source-body voltage VSB for the FET 618, thereby suppressing leakage current in the FET 618. Resistor 620 can be any resistor that provides the appropriate resistance required by the ESD power clamping device 600.

[0043] refer to Figure 7 , Figure 7 This is a flowchart illustrating a method 700 for operating an ESD power clamping device according to some embodiments of the present disclosure. For a better understanding of the present disclosure, regarding... Figures 1 to 6 The embodiments shown discuss method 700, but are not limited thereto. Figure 7 As shown, in some embodiments, method 700 includes operations 710-740.

[0044] Method 700 includes operation 710, coupling an impedance element between a power node and the source terminal of a FET in an ESD power clamping device. The power node may be ground. Method 700 includes operation 720, coupling the body terminal of the FET in the ESD power clamping device to the power node. Operations 710 and 720 are performed to generate a source-body voltage between the source terminal and the body terminal of the FET in the ESD power clamping device. For example, as... Figures 3 to 6 As shown, the impedance element can be at least one of a diode, a resistor, or an inductor. The impedance element can also be a combination of at least one of a diode, a resistor, and an inductor. Figure 2 The advantages of generating a source-body voltage are illustrated. For example, the generated source-body voltage expands the depletion region between the source and drain of the FET in an ESD power clamping device, and the expanded depletion region in turn increases the threshold voltage, thereby suppressing the leakage current of the ESD power clamping device.

[0045] Method 700 includes operation 730, coupling the output of the ESD detection circuit of the ESD power clamping device to the input of the control circuit of the ESD power clamping device. For example, as Figure 1 As shown, the ESD detection circuit may include an RC time constant circuit, and the control circuit may be an inverter including PMOS transistors and NMOS transistors. Operation 730 is performed to provide an RC time constant to maintain the voltage state at the input of the inverter at a low or high level for a certain period of time.

[0046] Method 700 includes operation 740, coupling the output of the control circuitry of the ESD power clamp device to the gate terminal of the FET of the ESD power clamp device to turn the FET on or off. Operation 740 is performed to turn the FET of the ESD power clamp device on or off. A low-voltage state at the input of the inverter can output a high voltage to the gate terminal of the FET of the ESD power clamp device, thereby turning the FET on. The turned-on FET can discharge an ESD pulse to a power supply voltage node (e.g., ground). Conversely, a high-voltage state at the input of the inverter can output a low voltage to the gate terminal of the FET of the ESD power clamp device, thereby turning the FET off.

[0047] refer to Figure 8 , Figure 8 This is a schematic diagram illustrating an exemplary ESD protection circuit 800 according to some embodiments of the present disclosure. The ESD protection circuit 800 includes a first circuit having an ESD power clamping device 860 and a second circuit having a diode 820.

[0048] ESD power clamping device 860 includes ESD detection circuitry 802. In some embodiments, ESD detection circuitry 802 may include resistor 804 and capacitor 806, with capacitor 806 coupled to resistor 804 to form an RC time constant circuit. In some embodiments, the RC time constant circuit is not limited to a resistor and a capacitor. The RC time constant circuit may include any suitable number of capacitors or capacitive devices. The RC time constant circuit may also include any suitable number of resistors or resistive devices.

[0049] ESD power clamping device 860 includes control circuitry 808. Control circuitry 808 includes input terminal 814 and output terminal 816. In some embodiments, control circuitry 808 may be an inverter including a PMOS transistor 810 and an NMOS transistor 812. The source terminal of the PMOS transistor 810 may be coupled to the power supply voltage VDD. The drain terminal of the PMOS transistor 810 may be coupled to the output terminal 816 of the inverter 808. The source terminal of the NMOS transistor may be coupled to the power supply voltage VSS via a diode 820. The drain terminal of the NMOS transistor may be coupled to the output terminal 816 of the inverter 808. Input terminal 814 of the inverter 808 may be coupled to ESD detection circuitry 802.

[0050] ESD power clamping device 860 includes a FET 818. The drain terminal of FET 818 can be coupled to ESD detection circuit 802, control circuit 808, and power supply voltage VDD. The source terminal of FET 818 can be coupled to power supply voltage VSS through diode 820. The gate terminal of FET 818 can be coupled to the output terminal 816 of control circuit 808. The body terminal of FET 818 can be coupled to power supply voltage VSS, such as... Figure 8 As shown in label 822.

[0051] In some embodiments, FET 818 may be a bigFET. A bigFET may be an NMOS device (e.g., an NMOS transistor) with a large channel width to absorb ESD current. A bigFET may also be a PMOS device (e.g., a PMOS transistor) with a large channel width to absorb ESD current.

[0052] Diode 820 is coupled to the source terminal of FET 818 in ESD detection circuit 802, control circuit 808, and ESD power clamping device 860. The body terminal of FET 818 is coupled to the power supply voltage VSS. The voltage drop across diode 820 generates a source-body voltage between the source and body of FET 818 in ESD power clamping device 860. This source-body voltage widens the depletion region between the source and drain of FET 818, thus increasing the threshold voltage and suppressing leakage current in FET 818. Furthermore, diode 820 also serves as a second ESD power clamping device in ESD protection circuit 800 by providing a voltage drop. (See below...) Figure 9 This will help you better understand the function of diode 820.

[0053] refer to Figure 9 , Figure 9 This is a schematic diagram illustrating an ESD protection circuit 900. The ESD protection circuit 900 includes a first ESD power clamping device 900a, a second ESD power clamping device 900b, and a voltage divider 900c. The first ESD power clamping device 900a includes a resistor 906 and a capacitor 908, with the capacitor 908 coupled to the resistor 906 to form an RC time constant circuit. The first ESD power clamping device 900a includes a PMOS transistor 910 and an NMOS transistor 912, with the NMOS transistor 912 coupled to the PMOS transistor 910 to form an inverter. The first ESD power clamping device 900a includes a FET 914, which can be turned on or off by the output voltage of the inverter.

[0054] Similar to the first ESD power clamping device 900a, the second ESD power clamping device 900b includes a resistor 916 and a capacitor 918, with the capacitor 918 coupled to the resistor 916 to form an RC time constant circuit. The second ESD power clamping device 900b includes a PMOS transistor 920 and an NMOS transistor 922, with the NMOS transistor 922 coupled to the PMOS transistor 920 to form an inverter. The second ESD power clamping device 900b includes a FET 924, which can be turned on or off by the output voltage of the inverter. The voltage divider 900c includes resistors 902 and 904 connected in series.

[0055] and Figure 9 Compared to the ESD protection circuit 900, Figure 8The ESD protection circuit 800 can be formed by replacing the second ESD power clamping device with a diode 820 and removing the voltage divider 900c. By removing the voltage divider 900c, unnecessary current dissipation of resistors 902 and 904 is avoided, thereby preventing additional power consumption of the ESD protection circuit 900. Furthermore, the ESD power clamping device 860 will only turn on when an electrostatic discharge occurs in the circuit. Moreover, by removing the voltage divider 900c and replacing the second ESD power clamping device 900b with a diode 820, ESD protection can be provided with a smaller footprint, thereby reducing the overall circuit size. Furthermore, as described above, the diode 820 generates a voltage difference between the source and body of the FET in the first ESD protection circuit 900a, thereby suppressing current leakage in the first ESD protection circuit 900a.

[0056] The aforementioned advantages of the ESD protection circuit 800 can be better understood through a concrete example. In this example, assume that the first ESD power clamping device 900a can operate at 1.2V. Therefore, if the first ESD power clamping device 900a is used alone in an application requiring a 1.8V operating voltage, the first ESD power clamping device 900a may be damaged. However, when combined with diode 820, such as... Figure 8 As shown, diode 820 can provide a voltage drop of 0.7V, and ESD protection circuit 800 can operate at a working voltage of up to 1.9V. In other words, ESD protection circuit 800 can be safely used in the aforementioned applications requiring a 1.8V working voltage.

[0057] Figure 8 The ESD protection circuit 800 is only an exemplary embodiment. In some other embodiments, diode 820 may be replaced by multiple diodes. In some other embodiments, diode 820 may be replaced by a combination of diode and resistor or inductor.

[0058] refer to Figure 10 , Figure 10 This is a flowchart illustrating a method 1000 for operating an ESD protection device according to some embodiments of the present disclosure. For a better understanding of this disclosure, regarding... Figure 8 The illustrated embodiments discuss method 1000, but are not limited thereto. For example... Figure 10 As shown, in some embodiments, method 1000 includes operations 1010-1040.

[0059] Method 1000 includes operation 1010, coupling a second ESD protection circuit, including an impedance element, between a first ESD protection circuit and a power node, such that the impedance element is coupled to the source terminal of a FET in the first ESD protection circuit. The power node may be ground. Method 1000 includes operation 1020, coupling the body terminal of the FET in the first ESD protection circuit to the power node. Operations 1010 and 1020 allow for the generation of a source-body voltage for the FET in the first ESD protection circuit. For example, as... Figure 8 As shown, the impedance element can be a diode. However, the choice of impedance element is not limited to this. In some embodiments, the impedance element can be multiple diodes. In some embodiments, the impedance element can be a combination of a diode and a resistor or inductor. As described above, comparison Figure 8 ESD protection circuit 800 and Figure 9 The ESD protection circuit 900 can be understood as having the advantages of operation of 1010 and 1020.

[0060] Method 1000 includes operation 1030, coupling the output of the ESD detection circuit of the first ESD protection circuit to the input of the control circuit of the first ESD protection circuit. For example, as Figure 8 As shown, the ESD detection circuit may include an RC time constant circuit, and the control circuit may be an inverter including PMOS transistors and NMOS transistors. Operation 1030 is performed to provide an RC time constant to maintain the voltage state at the input of the inverter at a low or high level for a certain period of time.

[0061] Method 1000 includes operation 1040, coupling the output of the control circuit of a first ESD protection circuit to the gate terminal of the FET of the first ESD protection circuit to turn the FET on or off. Operation 1040 is performed to turn the FET of the first ESD protection circuit on or off. A low-voltage state at the input of the inverter can output a high voltage to the gate of the FET, thereby turning the FET on. The turned-on FET can discharge an ESD pulse to a power supply voltage node (e.g., ground). Conversely, a high-voltage state at the input of the inverter can output a low voltage to the gate of the FET, thereby turning the FET off.

[0062] refer to Figure 11 , Figure 11 This is a flowchart illustrating a method 1100 for operating an ESD protection circuit according to some embodiments of the present disclosure. For a better understanding of the present disclosure, regarding... Figures 1 to 10 The illustrated embodiment discusses method 1100, but is not limited thereto. For example... Figure 11 As shown, in some embodiments, method 1100 includes operations 1110-1140.

[0063] Method 1100 includes operation 1110, providing a first power supply voltage to a first node of the ESD detection circuit of the ESD protection circuit, and providing a second power supply voltage to a second node of the ESD detection circuit of the ESD protection circuit. For example, as Figure 1 As shown, a first power supply voltage VDD is provided to node 124 of the ESD detection circuit 102 of the ESD power clamping device 100, and a second power supply voltage VSS is provided to node 126 of the ESD detection circuit 102 of the ESD power clamping device 100. In some embodiments, VDD may be suitable for the core circuitry (e.g., Figure 1 The core circuit 160) operates under any voltage. VSS can be ground voltage. In some embodiments, the ESD detection circuit can be an RC time constant circuit including resistors and capacitors, for example, Figure 1 The ESD detection circuit 102 is provided. However, the RC time constant circuit is not limited to a resistor and a capacitor as shown in the figure. The RC time constant circuit can include any suitable number of capacitors or capacitive devices. The RC time constant circuit can also include any suitable number of resistors or resistive devices.

[0064] Method 1100 includes operation 1120, which outputs voltage from the ESD detection circuit to the input node of the control circuitry of the ESD protection circuit. For example, as Figure 1 As shown, during normal operation without an ESD pulse, since there is no significant current flowing into or out of the capacitor 106 of the ESD detection circuit 102, a high voltage is output from the ESD detection circuit 102 to the input node 114 of the control circuit 108 of the ESD power clamping device 100. Conversely, during an ESD event, a low voltage is output from the ESD detection circuit 102 to the input node 114 of the control circuit 108 of the ESD power clamping device 100. The control circuit of the ESD protection circuit can be an inverter circuit, for example, Figure 1 The inverter 108.

[0065] Method 1100 includes operation 1130, turning off or on the FET of the ESD protection circuit. For example, such as Figure 1As shown, during normal operation without an ESD pulse, the voltage at input 114 of inverter 108 is high, and a low voltage is output from inverter 108 to the gate terminal of FET 118 via output 116, turning off FET 118. With FET 118 off, the supply voltage VDD can ideally be supplied to the core circuitry 160 for operation. On the other hand, during an ESD event, the voltage at input 114 of inverter 108 is low, and a high voltage is output from inverter 108 to the gate terminal of FET 118 via output 116, turning on FET 118. If an ESD pulse occurs in the core circuitry 160, the turned-on FET 118 can discharge the ESD pulse to the supply voltage VSS (e.g., ground).

[0066] Method 1100 includes operation 1140, providing a second power supply voltage to the body terminal of the FET and the terminals of the impedance element of the FET. For example, as Figure 1 As shown, the power supply voltage VSS is supplied to the body terminal (denoted as 122) of FET 118. The power supply voltage VSS is also supplied to the terminal of impedance element 120. Because impedance element 120 is positioned between the source terminal of FET 118 and the power supply voltage VSS, a voltage drop occurs across impedance element 120. On the other hand, the body of FET 118 is coupled to the power supply voltage VSS without an impedance element. The voltage drop across impedance element 120 generates a non-zero source-body voltage VSB. This source-body voltage VSB induces a body effect in FET 118, thereby suppressing leakage current in FET 118.

[0067] The above description includes exemplary operations, but these operations are not necessarily performed in the order shown. Operations may be added, substituted, rearranged, and / or eliminated as appropriate without departing from the spirit and scope of this disclosure.

[0068] In some embodiments, an ESD power clamping device is disclosed. The ESD power clamping device includes: an ESD detection circuit; a control circuit coupled to the ESD detection circuit; a field-effect transistor (FET) coupled to the control circuit; and an impedance element coupled to the FET. The FET includes: a drain terminal coupled to a first power node; a gate terminal coupled to the output of the control circuit; a source terminal coupled to a second power node via the impedance element; and a body terminal coupled to the second power node.

[0069] In some embodiments, an ESD protection circuit is disclosed. The ESD protection circuit includes: a first protection circuit including an ESD power clamping device; and a second protection circuit including an impedance element coupled to the ESD power clamping device of the first protection circuit. The ESD power clamping device of the first protection circuit includes: an ESD detection circuit; a control circuit coupled to the ESD detection circuit; and a FET coupled between a first power node and a second power node. The FET includes: a drain terminal coupled to the first power node; a gate terminal coupled to the output of the control circuit; a source terminal coupled to the second power node via the impedance element of the second protection circuit; and a body terminal coupled to the second power node.

[0070] In some embodiments, a method for operating an ESD protection circuit is also disclosed. The ESD protection circuit includes a FET coupled between a first power node and a second power node. The method includes generating a source-body voltage between the source terminal and the body terminal of the FET; and providing a voltage state to the gate terminal of the FET to turn the FET on or off.

[0071] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0072] Example

[0073] Example 1. An electrostatic discharge (ESD) power clamping device, comprising: an ESD detection circuit; a control circuit coupled to the ESD detection circuit; a field-effect transistor (FET) coupled to the control circuit; and an impedance element coupled to the FET, wherein the FET includes: a drain terminal coupled to a first power node; a gate terminal coupled to an output terminal of the control circuit; a source terminal coupled to a second power node via the impedance element; and a body terminal coupled to the second power node.

[0074] Example 2. The ESD power clamping device according to Example 1, wherein the second power node is ground.

[0075] Example 3. The ESD power clamping device according to Example 1, wherein the ESD detection circuit includes a resistor and a capacitive device forming a resistor-capacitor (RC) circuit.

[0076] Example 4. The ESD power clamping device according to Example 1, wherein the control circuitry includes a PMOS transistor and an NMOS transistor forming an inverter.

[0077] Example 5. The ESD power clamping device according to Example 1, wherein the impedance element includes at least one of a diode, a resistor, or an inductor.

[0078] Example 6. The ESD power clamping device according to Example 1, wherein the impedance element comprises a diode and a resistor connected in series.

[0079] Example 7. The ESD power clamping device according to Example 1, wherein the impedance element comprises a diode and an inductor connected in series.

[0080] Example 8. An electrostatic discharge (ESD) protection circuit, comprising: a first protection circuit including an ESD power clamping device; and a second protection circuit including an impedance element coupled to the ESD power clamping device of the first protection circuit, wherein the ESD power clamping device of the first protection circuit includes: an ESD detection circuit; a control circuit coupled to the ESD detection circuit; and a field-effect transistor (FET) coupled between a first power node and a second power node, wherein the FET includes: a drain terminal coupled to the first power node; a gate terminal coupled to the output of the control circuit; a source terminal coupled to the second power node via the impedance element of the second protection circuit; and a body terminal coupled to the second power node.

[0081] Example 9. The ESD protection circuit according to Example 8, wherein the second power node is ground.

[0082] Example 10. The ESD protection circuit according to Example 8, wherein the ESD detection circuit includes a resistor and a capacitive device forming a resistor-capacitor (RC) circuit.

[0083] Example 11. An ESD protection circuit according to Example 8, wherein the control circuit includes a PMOS transistor and an NMOS transistor forming an inverter.

[0084] Example 12. The ESD protection circuit according to Example 8, wherein the impedance element includes at least one of a diode, a resistor, or an inductor.

[0085] Example 13. An ESD protection circuit according to Example 8, wherein the impedance element comprises a combination of diodes, resistors and inductors.

[0086] Example 14. The ESD protection circuit according to Example 8, wherein the impedance element is also coupled to the ESD detection circuit and the control circuit.

[0087] Example 15. A method for operating an ESD protection circuit, the ESD protection circuit including an ESD detection circuit, a control circuit, and a field-effect transistor (FET), the method comprising: providing a first power supply voltage to a first node of the ESD detection circuit of the ESD protection circuit, and providing a second power supply voltage to a second node of the ESD detection circuit; outputting a voltage from the ESD detection circuit to an input node of the control circuit of the ESD protection circuit; turning on or off the FET of the ESD protection circuit; and providing the second power supply voltage to a body terminal of the FET and a terminal of an impedance element coupled to the FET.

[0088] Example 16. The method according to Example 15, wherein the drain terminal of the FET is coupled to the first power supply voltage, and the source terminal of the FET is coupled to the second power supply voltage via the impedance element.

[0089] Example 17. The method according to Example 15, wherein the second power supply voltage is ground voltage.

[0090] Example 18. The method according to Example 15, wherein the ESD detection circuit includes a resistor and a capacitor forming a resistor-capacitor (RC) circuit, and a first power supply voltage is provided to the resistor terminal of the ESD detection circuit, and a second power supply voltage is provided to the capacitor terminal of the ESD detection circuit.

[0091] Example 19. The method according to Example 15, wherein the control circuit includes a PMOS transistor and an NMOS transistor forming an inverter, and the method further includes: providing a first power supply voltage to the source terminal of the PMOS transistor; and providing a second power supply voltage to the source terminal of the NMOS transistor.

[0092] Example 20. The method according to Example 15, wherein the FET of the ESD protection circuit is turned off and on by an output voltage output from the control circuit of the ESD protection circuit.

Claims

1. An electrostatic discharge (ESD) power clamping device, comprising: ESD detection circuit; The control circuit is coupled to the ESD detection circuit; A field-effect transistor (FET) is coupled to the control circuit. as well as An impedance element is provided, one end of which is coupled to the ESD detection circuit, the control circuit, and the FET, and the other end of which is coupled to the power supply voltage VSS. The FET includes: The drain terminal is coupled to the first power node; The gate terminal is coupled to the output terminal of the control circuit. The source terminal is coupled to the second power node via the impedance element; and The main terminal is coupled to the second power node.

2. The ESD power clamping device according to claim 1, wherein, The second power node is ground.

3. The ESD power clamping device according to claim 1, wherein, The ESD detection circuit includes resistors and capacitive devices that form a resistor-capacitor (RC) circuit.

4. The ESD power clamping device according to claim 1, wherein, The control circuit includes a PMOS transistor and an NMOS transistor that form an inverter.

5. The ESD power clamping device according to claim 1, wherein, The impedance element includes at least one of a diode, a resistor, or an inductor.

6. The ESD power clamping device according to claim 1, wherein, The impedance element includes a diode and a resistor connected in series.

7. The ESD power clamping device according to claim 1, wherein, The impedance element includes a diode and an inductor connected in series.

8. An electrostatic discharge (ESD) protection circuit, comprising: The first protection circuit includes an ESD power clamping device; as well as The second protection circuit includes impedance elements. The ESD power clamping device of the first protection circuit includes: ESD detection circuit; Control circuit, coupled to the ESD detection circuit; and A field-effect transistor (FET) coupled between a first power node and a second power node, wherein the FET comprises: The drain terminal is coupled to the first power node; The gate terminal is coupled to the output terminal of the control circuit. The source terminal is coupled to the second power node via the impedance element of the second protection circuit; and The main terminal is coupled to the second power node. One end of the impedance element is coupled to the ESD detection circuit, the control circuit, and the FET, and the other end of the impedance element is coupled to the power supply voltage VSS.

9. The ESD protection circuit according to claim 8, wherein, The second power node is ground.

10. The ESD protection circuit according to claim 8, wherein, The ESD detection circuit includes resistors and capacitive devices that form a resistor-capacitor (RC) circuit.

11. The ESD protection circuit according to claim 8, wherein, The control circuit includes a PMOS transistor and an NMOS transistor that form an inverter.

12. The ESD protection circuit according to claim 8, wherein, The impedance element includes at least one of a diode, a resistor, or an inductor.

13. The ESD protection circuit according to claim 8, wherein, The impedance element includes a combination of diodes, resistors, and inductors.

14. The ESD protection circuit according to claim 8, wherein, The impedance element is also coupled to the ESD detection circuit and the control circuit.

15. A method for operating an ESD protection circuit, the ESD protection circuit comprising an ESD detection circuit, a control circuit, and a field-effect transistor (FET), the method comprising: A first power supply voltage is provided to the first node of the ESD detection circuit of the ESD protection circuit, and a second power supply voltage is provided to the second node of the ESD detection circuit. The voltage is output from the ESD detection circuit to the input node of the control circuit of the ESD protection circuit; Turn the FET of the ESD protection circuit on or off; as well as The second power supply voltage is provided to the main terminals of the FET and the terminals of the impedance element, wherein one end of the impedance element is coupled to the ESD detection circuit, the control circuit, and the FET, and the other end of the impedance element is coupled to the power supply voltage VSS.

16. The method according to claim 15, wherein, The drain terminal of the FET is coupled to the first power supply voltage, and the source terminal of the FET is coupled to the second power supply voltage via the impedance element.

17. The method according to claim 15, wherein, The second power supply voltage is the ground voltage.

18. The method according to claim 15, wherein, The ESD detection circuit includes a resistor and a capacitor forming a resistor-capacitor (RC) circuit, and a first power supply voltage is provided to the resistor terminal of the ESD detection circuit, and a second power supply voltage is provided to the capacitor terminal of the ESD detection circuit.

19. The method according to claim 15, wherein, The control circuit includes a PMOS transistor and an NMOS transistor forming an inverter, and the method further includes: The first power supply voltage is supplied to the source terminal of the PMOS transistor; and The second power supply voltage is supplied to the source terminal of the NMOS transistor.

20. The method of claim 15, wherein, The FET of the ESD protection circuit is turned off and on by the output voltage output from the control circuit of the ESD protection circuit.

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