Interleaved signal generation circuit

Abstract

An embodiment of the present invention provides an interlaced signal generating circuit, comprising: an interlaced pulse generating circuit, used to generate a first pulse signal according to a first control signal, and to generate a second pulse signal according to a second control signal, the first control signal and the second control signal are anti-phase signals, and the first pulse signal and the second pulse signal are interlaced pulse signals; a delayed signal output circuit, comprising G signal output circuits, G being an integer greater than or equal to 2; non-first-stage signal output circuits all receive the delayed output signal output by the previous-stage signal output circuit as the input signal of the current-stage signal output circuit, and the first-stage signal output circuit receives the initial input signal as the input signal of the first-stage signal output circuit; the embodiment of the present invention generates a first pulse signal and a second pulse signal with adjustable periods, and generates a delay signal with controllable delay according to the first pulse signal and the second pulse signal, and the circuit layout area is small and the power consumption of the circuit is low.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor circuit design, and in particular to an interleaved signal generating circuit. Background Art

[0002] In semiconductor circuit design, staggered signals are often used. Staggered signals refer to signals generated with a fixed delay at each interval.

[0003] For synchronous signals, clock signals are usually used to generate equally spaced interleaved signals; for asynchronous signals, delay cells are inserted to generate the required equally spaced interleaved signals, and the delay between signals can be achieved by inserting corresponding delay cells as required.

[0004] However, the inventors have discovered that when using synchronous signals to generate equally spaced interleaved signals, the delay between the equally spaced interleaved signals must be an integer multiple of the clock period, and the delay between the equally spaced interleaved signals is poorly controllable; and when using asynchronous signals to generate equally spaced interleaved signals, although the delay between signals is well controllable, it will significantly increase the area of ​​the circuit layout and the power consumption of the circuit. Summary of the invention

[0005] An embodiment of the present invention provides an interleaved signal generating circuit to generate a first pulse signal and a second pulse signal with adjustable periods, and to generate a delay signal with controllable delay according to the first pulse signal and the second pulse signal, and the circuit layout area is small and the power consumption of the circuit is low.

[0006] To solve the above technical problems, an embodiment of the present invention provides an interlaced signal generating circuit, comprising: an interlaced pulse generating circuit, used to generate a first pulse signal according to a first control signal, and to generate a second pulse signal according to a second control signal, the first control signal and the second control signal are anti-phase signals, and the first pulse signal and the second pulse signal are interlaced pulse signals; a delayed signal output circuit, comprising G signal output circuits, G is an integer greater than or equal to 2, the signal output circuit is used to receive an input signal, a first pulse signal and a second pulse signal, and output a delayed output signal; wherein, non-first-stage signal output circuits all receive the delayed output signal output by the previous-stage signal output circuit as the input signal of the current-stage signal output circuit, and the first-stage signal output circuit receives the initial input signal as the input signal of the first-stage signal output circuit; the rising edge of the delayed output signal generated by the signal output circuit has a first delay with the rising edge of the delayed output signal output by the previous-stage signal output circuit or the initial input signal; the falling edge of the delayed output signal generated by the signal output circuit has a second delay with the falling edge of the delayed output signal output by the previous-stage signal output circuit or the initial input signal.

[0007] Compared with the related art, a first oscillation signal is generated according to a control signal, that is, when the control signal is at an effective level, a first oscillation signal with a certain period is generated; a second oscillation signal is generated based on the first oscillation signal according to a magnification selection signal, that is, based on the magnification selection signal, the period of the first oscillation signal is changed to generate a corresponding second oscillation signal; then the second oscillation signal is used as a signal source to generate a pulse signal, and the pulse period of the generated pulse signal is the same as the oscillation period of the second oscillation signal; in the process of generating the pulse signal, if the magnification selection signal changes, the amplitude of the period of the first oscillation signal is adjusted to change, so that the period of the generated second oscillation signal changes , thereby generating a first pulse signal and a second pulse signal with adjustable periods; and generating a delay signal with controllable delay based on the first pulse signal and the second pulse signal, wherein the delay signal has a first delay on the rising edge and a second delay on the falling edge relative to the input signal; the first delay is the pulse period of the first pulse signal, and the second delay is the pulse period of the second pulse signal, so the delay time of the delay signal can be adjusted by adjusting the pulse periods of the first pulse signal and the second pulse signal; at the same time, the delay time of the delay signal does not need to connect more delay units, thereby simplifying the circuit structure, making the circuit layout area small, and the circuit power consumption small.

[0008] In addition, the pulse periods of the first pulse signal and the second pulse signal are equal. By controlling the pulse period of the first pulse signal to be consistent with the pulse period of the second pulse signal, the delay time of the rising edge and the falling edge of the generated delay signal is ensured to be consistent, thereby ensuring that the delay signal is a delay of the input signal.

[0009] In addition, the staggered pulse generating circuit includes: a signal generating module for generating a first control signal and a second control signal according to an activation signal; a first pulse generating unit for generating a first pulse signal according to the first control signal; and a second pulse generating unit for generating a second pulse signal according to the second control signal.

[0010] In addition, the signal generating module includes: a reset unit, receiving a first reset signal and an activation signal, and generating a first control signal based on the first reset signal and the activation signal; and a reverse unit, receiving a first control signal, and generating a second control signal based on the first control signal.

[0011] In addition, the signal generating module also includes: a reset signal generating unit, which is used to generate a second reset signal based on the first reset signal and the first control signal, so that when the first reset signal is in a reset state, the second reset signal is also in a reset state, and when the first reset signal is in a non-reset state, the second reset signal generates a reset narrow pulse based on the changing edge of the first control signal.

[0012] In addition, the first pulse generating unit includes: an oscillation module, which receives a first control signal and generates a first oscillation signal according to the first control signal; a period adjustment module, which receives the first oscillation signal and a multiplier selection signal and outputs a second oscillation signal, and the period of the second oscillation signal is the period after the first oscillation signal is adjusted based on the multiplier selection signal; a pulse conversion module, which receives the second oscillation signal and outputs a pulse signal, the pulse of the first pulse signal is generated based on the signal change edge of the second oscillation signal, and the pulse period of the first pulse signal is the same as the oscillation period of the second oscillation signal.

[0013] In addition, the second pulse generating unit has the same circuit structure as the first pulse generating unit.

[0014] In addition, the period adjustment module includes: a delay unit, which receives the first oscillation signal and generates an oscillation adjustment signal based on the first oscillation signal, and the period of the oscillation adjustment signal is different from the period of the first oscillation signal; a selection unit, which receives a multiplier selection signal and selects the first oscillation signal or the oscillation adjustment signal as the second oscillation signal based on the multiplier selection signal.

[0015] In addition, the delay unit includes E delay sub-units connected in series, the oscillation adjustment signal includes E delay signals, E is a positive integer; the first-level delay sub-unit is used to generate a first delay signal according to the first oscillation signal, and input the first delay signal into the second-level delay sub-unit; the F-th level delay sub-unit is used to generate an F-th delay signal according to the F-1-th delay signal, where F is less than or equal to E and a positive integer greater than or equal to 2.

[0016] In addition, the selection unit includes: a multiplier selector, the multiplier selector includes a first selection input terminal, a second selection input terminal, a selection signal terminal and a selection output terminal, the first selection input terminal and the second selection input terminal are respectively used to receive one of the oscillation adjustment signals or the first oscillation signal, the selection signal terminal is used to receive the multiplier selection signal, and the selection output terminal is used to output the second oscillation signal.

[0017] In addition, the oscillation module includes: an oscillation unit and a trigger unit connected to the oscillation unit; the trigger unit is used to receive a reset signal and a first control signal, and trigger the oscillation unit based on the reset signal and the first control signal; after the oscillation unit is triggered, it is used to generate a first oscillation signal according to the first control signal.

[0018] In addition, the oscillation unit includes: a ring oscillator formed by A inverters connected in series, where A is a positive odd number.

[0019] In addition, the oscillation module also includes: a first inverter group, including B inverters connected in series, where B is a positive even number; a first selection unit, used to receive a first selection signal and, based on the first selection signal, connect the first inverter group in series between adjacent inverters in the ring oscillator.

[0020] In addition, the pulse conversion module includes: a pulse converter, which is used to receive the second oscillation signal and generate a first pulse signal based on the second oscillation signal.

[0021] In addition, the signal output circuit includes: a first control module, receiving a first pulse signal and an input signal, and outputting a first adjustment signal, the first preset edge of the first adjustment signal has a first delay relative to the rising edge of the input signal, and the first delay is the pulse period of the first pulse signal; a second control module, receiving a second pulse signal and an input signal, and outputting a second adjustment signal, the second preset edge of the second adjustment signal has a second delay relative to the falling edge of the input signal, and the second delay is the pulse period of the second pulse signal; a signal output module, receiving the first adjustment signal and the second adjustment signal, and outputting a delayed output signal, the rising edge of the delayed output signal is generated based on the first preset edge of the first adjustment signal, and the falling edge of the delayed output signal is generated based on the second preset edge of the second adjustment signal.

[0022] In addition, the signal output module includes: a first receiving unit, receiving the first pulse signal and the first adjustment signal, and generating a first pulse control signal when the first adjustment signal is at a valid level, and the pulse phase of the first pulse control signal is the same as the pulse phase of the first pulse signal; a second receiving unit, receiving the second pulse signal and the second adjustment signal, and generating a second pulse control signal when the second adjustment signal is at a valid level, and the pulse phase of the second pulse control signal is the same as the pulse phase of the second pulse signal; a latch unit, receiving the first pulse control signal and the second pulse control signal, and generating a delayed output signal.

[0023] In addition, the first receiving unit is also used to receive a first control signal. The first receiving unit is used to generate a first pulse control signal according to the first pulse signal during a period when the first adjustment signal and the first control signal are at a valid level.

[0024] In addition, the second receiving unit is further used to receive a second control signal. The second receiving unit is used to generate a second pulse control signal according to the second pulse signal during a period when the second adjustment signal and the second control signal are at a valid level.

[0025] In addition, the delayed signal output circuit also includes: an initial signal output circuit, including a first control module, a second control module and a signal output module; the first control module is used to receive a first pulse signal and a first power supply signal, and generate the first adjustment signal according to the first pulse signal and the first power supply signal; the second control module is used to receive a second pulse signal and a second power supply signal, and generate the second adjustment signal according to the second pulse signal and the second power supply signal; the signal output module is used to generate the initial input signal according to the first adjustment signal and the second adjustment signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 and Figure 2 A schematic diagram of the structure of an interleaved pulse generating circuit provided in an embodiment of the present invention;

[0027] Figure 3 A specific circuit diagram of a signal generating module provided by an embodiment of the present invention;

[0028] Figure 4 and Figure 5 A schematic diagram of the structure of a pulse generating circuit provided by an embodiment of the present invention;

[0029] Figure 6 A specific circuit diagram of an oscillation module provided by an embodiment of the present invention;

[0030] Figure 7 A schematic diagram of the structure of a delay unit provided in an embodiment of the present invention;

[0031] Figure 8 A schematic diagram of the structure of a selection unit provided in an embodiment of the present invention;

[0032] Fig. 9 and Fig.10 A circuit diagram of a period adjustment module provided in an embodiment of the present invention;

[0033] Fig.11 A schematic diagram of the timing of signals in a pulse generating circuit provided by an embodiment of the present invention;

[0034] Fig.12 A schematic diagram of the timing of signals in the staggered pulse generating circuit provided by an embodiment of the present invention;

[0035] Fig.13 A schematic diagram of the structure of a signal output circuit provided by an embodiment of the present invention;

[0036] Fig.14 A specific circuit diagram of a first control module provided by an embodiment of the present invention;

[0037] Fig.15A specific circuit diagram of a second control module provided by an embodiment of the present invention;

[0038] Fig.16 A schematic diagram of the structure of a signal output module provided by an embodiment of the present invention;

[0039] Fig.17 and Fig.18 A specific circuit diagram of a signal output module provided by an embodiment of the present invention;

[0040] Fig.19 A schematic diagram of the timing of signals in a signal output circuit provided by an embodiment of the present invention;

[0041] Fig. 20 and Fig.21 A schematic diagram of the structure of a delayed signal output circuit provided by an embodiment of the present invention;

[0042] Fig. 22 A specific circuit diagram of a delayed signal output circuit provided by an embodiment of the present invention;

[0043] Fig.23 A specific circuit diagram of a signal output circuit in a delayed signal output circuit provided in an embodiment of the present invention;

[0044] Fig.24 A schematic diagram of the timing of signals in a delayed signal output circuit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0045] When using synchronous signals to generate equally spaced interleaved signals, the delay between equally spaced interleaved signals must be an integer multiple of the clock period, and the controllability of the delay between equally spaced interleaved signals is poor; when using asynchronous signals to generate equally spaced interleaved signals, although the delay between signals is well controllable, it will significantly increase the area of ​​the circuit layout and the power consumption of the circuit.

[0046] To solve the above problems, an embodiment of the present invention provides an interlaced signal generating circuit, comprising: an interlaced pulse generating circuit, used to generate a first pulse signal according to a first control signal, and to generate a second pulse signal according to a second control signal, the first control signal and the second control signal are anti-phase signals, and the first pulse signal and the second pulse signal are interlaced pulse signals; a delayed signal output circuit, comprising G signal output circuits, G is an integer greater than or equal to 2, the signal output circuit is used to receive an input signal, a first pulse signal and a second pulse signal, and output a delayed output signal; wherein non-first-stage signal output circuits all receive the delayed output signal output by the previous-stage signal output circuit as the input signal of the current-stage signal output circuit, and the first-stage signal output circuit receives the initial input signal as the input signal of the first-stage signal output circuit; the rising edge of the delayed output signal generated by the signal output circuit has a first delay with the rising edge of the delayed output signal output by the previous-stage signal output circuit or the initial input signal; the falling edge of the delayed output signal generated by the signal output circuit has a second delay with the falling edge of the delayed output signal output by the previous-stage signal output circuit or the initial input signal.

[0047] To make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. However, it will be appreciated by those skilled in the art that in the embodiments of the present invention, many technical details are proposed in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can be implemented. The division of the following embodiments is for the convenience of description and should not constitute any limitation on the specific implementation of the present invention. The various embodiments can be combined with each other and quoted from each other without contradiction.

[0048] Figure 1 and Figure 2 A schematic diagram of the structure of an interleaved pulse generating circuit provided in an embodiment of the present invention, Figure 3 A specific circuit diagram of a signal generating module provided in an embodiment of the present invention, Figure 4 and Figure 5 A schematic diagram of the structure of a pulse generating circuit provided in an embodiment of the present invention, Figure 6 A specific circuit diagram of an oscillation module provided in an embodiment of the present invention, Figure 7 A schematic diagram of the structure of a delay unit provided in an embodiment of the present invention, Figure 8 A schematic diagram of the structure of a selection unit provided in an embodiment of the present invention, Fig. 9 and Fig.10 A circuit diagram of a period adjustment module provided in an embodiment of the present invention, Fig.11 A schematic diagram of the timing of signals in a pulse generating circuit provided in an embodiment of the present invention, Fig.12 A schematic diagram of the timing of signals in the staggered pulse generating circuit provided in an embodiment of the present invention, Fig.13 A schematic diagram of the structure of a signal output circuit provided by an embodiment of the present invention, Fig.14 A specific circuit diagram of the first control module provided in an embodiment of the present invention, Fig.15 A specific circuit diagram of the second control module provided in an embodiment of the present invention, Fig.16 A schematic diagram of the structure of a signal output module provided in an embodiment of the present invention, Fig.17 and Fig.18 A specific circuit diagram of a signal output module provided in an embodiment of the present invention, Fig.19 A schematic diagram of the timing of signals in a signal output circuit provided in an embodiment of the present invention, Fig. 20 and Fig.21 A schematic diagram of the structure of a delayed signal output circuit provided by an embodiment of the present invention, Fig. 22 A specific circuit diagram of a delayed signal output circuit provided by an embodiment of the present invention, Fig.23 A specific circuit diagram of the signal output circuit in the delayed signal output circuit provided in this embodiment, Fig.24 This is a schematic diagram of the timing of signals in the delayed signal output circuit provided by the embodiment of the present invention. The interleaved signal generating circuit provided by the present embodiment is further described in detail below in conjunction with the accompanying drawings.

[0049] An interleaved signal generating circuit, comprising:

[0050] The interlaced pulse generating circuit is used to generate a first pulse signal ActClk according to a first control signal ActEn, and to generate a second pulse signal PreClk according to a second control signal PreEn, wherein the first control signal ActEn and the second control signal PreEn are inverted signals, and the first pulse signal ActClk and the second pulse signal PreClk are interlaced pulse signals. The interlaced pulse signals referred to in this embodiment represent pulse signals (first pulse signal ActClk and second pulse signal PreClk) generated according to inverted signals (first control signal ActEn and second control signal PreEn), and may also be pulse signals that are respectively valid during different periods.

[0051] The delayed signal output circuit includes G signal output circuits, where G is an integer greater than or equal to 2. The signal output circuit is used to receive an input signal, a first pulse signal ActClk and a second pulse signal PreClk, and output a delayed output signal.

[0052] Among them, non-first-stage signal output circuits all receive the delayed output signal output by the previous-stage signal output circuit as the input signal of the current-stage signal output circuit, and the first-stage signal output circuit receives the initial input signal as the input signal of the first-stage signal output circuit; the rising edge of the delayed output signal generated by the signal output circuit has a first delay with the rising edge of the delayed output signal output by the previous-stage signal output circuit; the falling edge of the delayed output signal generated by the signal output circuit has a second delay with the falling edge of the delayed output signal output by the previous-stage signal output circuit.

[0053] In this embodiment, the pulse period of the first pulse signal ActClk is t1, the pulse period of the second pulse signal PreClk is t2, and the pulse period of the first pulse signal ActClk is equal to the pulse period of the second pulse signal PreClk; in other embodiments, the pulse periods of the first pulse signal and the second pulse signal may be different.

[0054] Specifically, refer to Figure 1 The interleaved pulse generating circuit 300 includes: a signal generating module 303, which is used to generate a first control signal ActEn and a second control signal PreEn according to an activation signal Active, wherein the first control signal ActEn and the second control signal PreEn are inverted signals. The activation signal Active is an activation instruction input from the outside, and the signal generating module 303 is used to generate the first control signal ActEn and the second control signal PreEn, which are inverted signals to each other, according to the external activation instruction.

[0055] More specifically, refer to Figure 2 , the signal generating module 303 comprises:

[0056] The reset unit 313 receives the first reset signal fnActEn and the activation signal Active, and generates a first control signal ActEn based on the first reset signal fnActEn and the activation signal Active.

[0057] The first reset signal fnActEn is an externally input reset instruction, which is used to reset the reset unit 313; specifically, after the reset unit 313 is reset, if the activation signal Active received by the reset unit 313 is at a valid level, the reset unit 313 generates the first control signal ActEn.

[0058] The inverting unit 323 receives the first control signal ActEn and generates a second control signal PreEn based on the first control signal ActEn.

[0059] In this embodiment, the signal generating module 303 also includes: a reset signal generating unit 333, which is used to generate a second reset signal fnPreEn based on the first reset signal fnActEn and the first control signal ActEn, so that when the first reset signal fnActEn is in a reset state, the second reset signal fnPreEn is also in a reset state, and when the first reset signal fnActEn is in a non-reset state, the second reset signal fnPreEn generates a reset narrow pulse based on the changing edge of the first control signal ActEn.

[0060] In this embodiment, the signal generating module 303 further includes: a selection signal generating unit 343, which is used to receive the selection signal fnAdjDly and generate a selection signal group based on the selection signal fnAdjDly, the selection signal group including the selection signal fnAdjDly and the inverted selection signal fnAdjDlyN, and the selection signal fnAdjDly and the inverted selection signal fnAdjDlyN are inverted signals.

[0061] It should be noted that, in this embodiment, the selection signal fnAdjDly includes a rate selection signal fnAdjDlyx, a first selection signal fnAdjDly1 and a second selection signal fnAdjDly2 for adjusting the pulse generating circuit 100 .

[0062] In one example, refer to Figure 3 The reset unit 313 includes a reset NAND gate 403 and a reset inverter 404. The reset inverter 404 is connected to the output end of the reset NAND gate 403. The reset NAND gate 403 is used to receive the first reset signal fnActEn and the activation signal Active.

[0063] The inverting unit 323 includes an output inverter 405 connected to the reset unit 313 and configured to generate the second control signal PreEn according to the first control signal ActEn.

[0064] The reset signal generating unit 333 includes a pulse conversion device 406, which is used to detect the changing edge (such as the rising edge) of the first control signal ActEn and generate a pulse control signal; an output NAND gate 407 and an output inverter 408. The output NAND gate 407 is also used to receive the first reset signal fnActEn, at which time the output inverter 408 outputs the second reset signal fnPreEn.

[0065] The selection signal generating unit 343 includes: a first selection inverter 401 and a second selection inverter 402 connected in series, wherein the output end of the first selection inverter 401 is connected to the input end of the second selection inverter 402, and is used to generate a selection signal group according to the selection signal fnAdjDly.

[0066] Continue to refer Figure 2 , the interleaved pulse generating circuit 300 also includes: a first pulse generating unit 301 and a second pulse generating unit 302; the first pulse generating unit 301 specifically includes a pulse generating circuit for generating a first pulse signal ActClk according to a first control signal ActEn; the second pulse generating unit 302 specifically includes a pulse generating circuit for generating a second pulse signal PreClk according to a second control signal PreEn; the first pulse signal ActClk and the second pulse signal PreClk are interleaved pulse signals.

[0067] In this embodiment, the second pulse generating unit 302 has the same circuit structure as the first pulse generating unit 301. This embodiment is described with reference to the pulse generating circuit 100 of the first pulse generating unit 301, wherein the first control signal ActEn and the second control signal PreEn belong to the control signal RasEn; the first reset signal fnActEn and the second reset signal fnPreEn belong to the reset signal fnRasEn.

[0068] refer to Figure 4 The first pulse generating unit 301 includes a pulse unit circuit 100, including: an oscillation module 101, which receives a control signal RasEn and generates a first oscillation signal Osc1 according to the control signal RasEn; specifically, when the control signal RasEn is at a valid level, the oscillation module 101 generates the first oscillation signal Osc1; in this embodiment, it is assumed that the period of the first oscillation signal Osc1 is T.

[0069] In one example, when the control signal RasEn is received and the control signal RasEn is at an effective level, the oscillation module 101 starts to oscillate to generate the first oscillation signal Osc1 .

[0070] Further, refer to Figure 5 The oscillation module 101 includes an oscillation unit 111 and a trigger unit 121 connected to the oscillation unit 111; the trigger unit 121 is used to receive a reset signal fnRasEn and a control signal RasEn, and trigger the oscillation unit 111 based on the reset signal fnRasEn and the control signal RasEn; after the oscillation unit 111 is triggered, a first oscillation signal Osc1 is generated according to the control signal RasEn.

[0071] It should be noted that in the description of “triggering the oscillation unit 111 based on the reset signal fnRasEn and the control signal RasEn”, the meaning of “based on” includes but is not limited to: when the reset signal fnRasEn is in a non-reset state and the control signal RasEn is at a valid level, the trigger unit 121 triggers the oscillation unit 111.

[0072] The reset signal fnRasEn is an externally input reset instruction for resetting the trigger unit 121; specifically, after the trigger unit 121 is reset, if the control signal RasEn received by the trigger unit 121 is at a valid level, the trigger unit 121 triggers the oscillation unit 111 to enable the oscillation unit 111 to generate the first oscillation signal Osc1.

[0073] In one example, refer to Figure 6 , the oscillation unit 111 includes a ring oscillator formed by A inverters connected in series, where A is a positive odd number; A can be 5, 7, 9, 11, etc. In this embodiment, A=7, i.e., a ring oscillator formed by 7 inverters connected in series, is used as an example for illustration, which does not constitute a limitation of this embodiment. In specific applications, the number of inverters in the ring oscillator can be selected according to actual needs. The trigger unit 121 includes a first NAND gate 211 and a second NAND gate 212, wherein the output end of the first NAND gate 211 is connected to an input end of the second NAND gate 212, and an input end of the first NAND gate 211 and an output end of the second NAND gate 212 are used to access the ring oscillator; one of the first NAND gate 211 and the second NAND gate 212 is used to receive the control signal RasEn, and the other is used to receive the reset signal fnRasEn; it should be noted that, Figure 3 The first NAND gate 211 is used to receive the control signal RasEn, and the second NAND gate 212 is used to receive the reset signal fnRasEn. This does not constitute a limitation to this embodiment. In other embodiments, the second NAND gate may receive the control signal, and the first NAND gate may receive the reset signal.

[0074] In this embodiment, the oscillation module 101 further includes: a first inverter group 215, including B inverters connected in series, where B is a positive even number; B can be 2, 4, 6, etc. In this embodiment, B=2, i.e., the first inverter group 215 formed by two inverters connected in series is used as an example for illustration, which does not constitute a limitation of this embodiment. In specific applications, the number of inverters in the first inverter group 215 can be selected according to actual needs. A first selection unit (not shown) is used to receive a first selection signal fnAdjDly1, and based on the first selection signal fnAdjDly1, connect the first inverter group 215 in series between adjacent inverters in the ring oscillator.

[0075] Specifically, the purpose of having B inverters in the first inverter group 215 is to ensure that the total number of inverters in the ring oscillator is an odd number; specifically, the first selection unit (not shown) includes a first selector 214, which is used to select the first branch or the second branch according to the first selection signal fnAdjDly1 and the reverse first selection signal fnAdjDly1N; wherein the first branch serves as a connection circuit of adjacent inverters in the ring oscillator, and the second branch connects the first inverter group 215 in series to the connection circuit of the adjacent inverters of the ring oscillator; the first inverter group 2 The purpose of connecting the first inverter group 215 to the ring oscillator is to increase the number of inverters in the ring oscillator, thereby increasing the period of the first oscillation signal Osc1 generated by the oscillation unit 111. In this embodiment, it is assumed that after adding the inverters of the first inverter group 215, the generated first oscillation signal Osc1 is 1.2T. Since the connection of the first inverter group 215 to the ring oscillator is controlled by the first selection signal fnAdjDly1, the period of the first oscillation signal Osc1 generated by the oscillation unit 111 can be adjusted by the externally input first selection signal fnAdjDly1.

[0076] In this embodiment, the oscillation module 101 further includes: a second inverter group 217, including C inverters connected in series, where C is a positive even number; C can be 2, 4, 6, etc. In this embodiment, C=4, i.e., a second inverter group 217 formed by 4 inverters connected in series, is used as an example for illustration, which does not constitute a limitation of this embodiment. In specific applications, the number of inverters in the second inverter group 217 can be selected according to actual needs. A second selection unit (not shown) is used to receive a second selection signal fnAdjDly2, and based on the second selection signal fnAdjDly2, connect the second inverter group 217 in series between adjacent inverters in the ring oscillator.

[0077] Specifically, the purpose of having C inverters in the second inverter group 217 is to ensure that the total number of inverters in the ring oscillator is an odd number; specifically, the second selection unit (not shown) includes a second selector 216, which is used to select the third branch or the fourth branch according to the second selection signal fnAdjDly2 and the reverse second selection signal fnAdjDly2N; wherein the third branch serves as a connection circuit of adjacent inverters in the ring oscillator, and the fourth branch connects the second inverter group 217 in series to the connection circuit of the adjacent inverters of the ring oscillator; the second inverter group 2 The purpose of connecting 17 to the ring oscillator is to increase the number of inverters in the ring oscillator, thereby increasing the period of the first oscillation signal Osc1 generated by the oscillation unit 111. In this embodiment, it is assumed that after adding the inverter of the second inverter group 217, the generated first oscillation signal Osc1 is 1.4T; since the connection of the second inverter group 217 to the ring oscillator is controlled by the second selection signal fnAdjDly2, the period of the first oscillation signal Osc1 generated by the oscillation unit 111 can be adjusted by the externally input second selection signal fnAdjDly2.

[0078] In this embodiment, B and C can be set to any positive even number. In specific applications, the values ​​of B and C can be reasonably set according to the required changes in the first oscillation signal Osc1 generated by the oscillation unit 111. In addition, this embodiment describes the implementation method of two inverter groups. On the basis of this embodiment, the implementation scheme of continuing to add a third inverter group and a fourth inverter group should all fall within the protection scope of this application.

[0079] In addition, by simultaneously connecting the first inverter group 215 and the second inverter group 217 to the ring oscillator, the period of the first oscillation signal Osc1 can be changed by different amplitudes; at this time, the periodic table 1 of the first oscillation signal Osc1 generated according to the difference between the first selection signal fnAdjDly1 and the second selection signal fnAdjDly2 is shown in:

[0080] Table 1 Osc1 periodic table

[0081]

[0082]

[0083] Continue to refer Figure 4The pulse generating circuit 100 includes: a period adjustment module 102, which receives the first oscillation signal Osc1 and the multiplication factor selection signal fnAdjDlyx, and outputs a second oscillation signal Osc2. The period of the second oscillation signal Osc2 is the period of the first oscillation signal Osc1 adjusted based on the multiplication factor selection signal fnAdjDlyx. The multiplication factor selection signal fnAdjDlyx is an externally input selection instruction for adjusting the period of the second oscillation signal Osc2. That is, the pulse generating circuit can adjust the period of the second oscillation signal Osc2 generated by the period adjustment module 102 through the externally input multiplication factor selection signal fnAdjDlyx.

[0084] In one example, the first oscillation signal Osc1 can be used to generate the oscillation adjustment signal OscT, and then the first oscillation signal Osc1 is selected as the second oscillation signal Osc2 for output according to the magnification selection signal fnAdjDlyx, or the oscillation adjustment signal OscT is selected as the second oscillation signal Osc2 for output. It is also possible to determine whether the oscillation adjustment signal OscT needs to be generated according to the magnification selection signal fnAdjDlyx, that is, the second oscillation signal Osc2 is output by first determining and then generating.

[0085] refer to Figure 5 The period adjustment module 102 includes: a delay unit 112, which receives the first oscillation signal Osc1 and generates an oscillation adjustment signal OscT based on the first oscillation signal Osc1, and the period of the oscillation adjustment signal OscT is different from the period of the first oscillation signal Osc1; a selection unit 122, which receives the multiplication selection signal fnAdjDlyx and selects the first oscillation signal Osc1 or the oscillation adjustment signal OscT as the second oscillation signal Osc2 based on the multiplication selection signal fnAdjDlyx.

[0086] In one example, refer to Figure 7 The delay unit 112 includes: a D flip-flop 201, the D flip-flop includes an input terminal D, clock terminals Clk and ClkN, a reset terminal RN and an output terminal Q, the clock terminals Clk and ClkN are used to receive the first oscillation signal Osc1 and the reverse first oscillation signal Osc1N, the reset terminal RN is used to receive the reset signal fnRasEn, the output terminal Q is used to trigger the inverter 202 in series and is connected to the input terminal D, and is used to output the oscillation adjustment signal OscT. Those skilled in the art will know that the period of the oscillation adjustment signal OscT output at this time is twice the period of the first oscillation signal Osc1.

[0087] refer to Figure 8The selection unit 122 includes a ratio selector 203, which includes a first selection input terminal, a second selection input terminal, a selection signal terminal and a selection output terminal. The first selection input terminal and the second selection input terminal are respectively used to receive the first oscillation signal Osc1 and the oscillation adjustment signal OscT, the selection signal terminal is used to receive the ratio selection signal fnAdjDlyx and the reverse ratio selection signal fnAdjDlyxN, and the selection output terminal is used to output the second oscillation signal Osc2. The period of the oscillation signal can be greatly changed by the ratio selection signal fnAdjDlyx. In this embodiment, the first selection input terminal is used to receive the first oscillation signal Osc1, and the second selection input terminal is used to receive the oscillation adjustment signal OscT. In other embodiments, the first selection input terminal may receive the oscillation adjustment signal OscT, and the second selection input terminal may receive the first oscillation signal Osc1.

[0088] At this time, the period of the second oscillation signal Osc2 generated according to the first selection signal fnAdjDly1, the second selection signal fnAdjDly2 and the magnification selection signal fnAdjDlyx is shown in Table 2:

[0089] Table 2 Periodic table of Osc2

[0090] fnAdjDlyx fnAdjDly1 fnAdjDly2 Osc2 cycle 0 0 0 T 0 1 0 1.2T 0 0 1 1.4T 0 1 1 1.6T 1 0 0 2T 1 1 0 2.4T 1 0 1 2.8T 1 1 1 3.2T

[0091] In this embodiment, the delay unit 112 includes E delay sub-units connected in series, the oscillation adjustment signal OscT includes E delay signals, E is a positive integer; the first-stage delay sub-unit is used to generate a first delay signal Osc11 according to the first oscillation signal Osc1, and input the first delay signal Osc11 into the second-stage delay sub-unit; the F-th-stage delay sub-unit is used to generate an F-th delay signal Osc1F according to the F-1-th-stage delay signal Osc1F-1, where F is a positive integer less than or equal to E and greater than or equal to 2.

[0092] Specifically, the F-th level delay subunit includes: a D flip-flop, the D flip-flop includes an input terminal, a clock terminal, a reset terminal and an output terminal, the clock terminal and the clock terminal are used to receive the F-1st delay signal Osc1F-1 and the inverted F-1st delay signal Osc1F-1N, the reset terminal is used to receive the reset signal, the output terminal is used to trigger the inverter in series and is connected to the input terminal, and is used to output the F-th delay signal Osc1F. Those skilled in the art will know that the period of the F-th delay signal Osc1F output at this time is twice the period of the F-1st delay signal Osc1F-1.

[0093] refer to Fig. 9The delay unit 112 includes three delay sub-units connected in series, namely a first-stage delay sub-unit 221, a second-stage delay sub-unit 223 and a third-stage delay sub-unit 225; wherein the first-stage delay sub-unit 221 is used to generate a first delay signal Osc11 according to the first oscillation signal Osc1, and the period of the first delay signal Osc11 is twice the period of the first oscillation signal Osc1; the second-stage delay sub-unit 223 is used to generate a second delay signal Osc12 according to the first delay signal Osc11, and the period of the second delay signal Osc12 is twice the period of the first delay signal Osc11; the third-stage delay sub-unit 225 is used to generate a third delay signal Osc13 according to the second delay signal Osc12, and the period of the third delay signal Osc13 is twice the period of the second delay signal Osc12.

[0094] In an example, the selection unit 122 selects the first oscillation signal Osc1 or the oscillation adjustment signal OscT as the second oscillation signal Osc2 based on the magnification selection signal fnAdjDlyx, including: selecting the E-1th delayed signal Osc1E-1 or the Eth delayed signal Osc1E as the second oscillation signal Osc2 based on the magnification selection signal fnAdjDlyx.

[0095] In this embodiment, the selection unit 122 selects the first oscillation signal Osc1 or the oscillation adjustment signal OscT as the second oscillation signal Osc2 based on the magnification selection signal fnAdjDlyx, including: selecting the second delayed signal Osc12 or the third delayed signal Osc13 as the second oscillation signal Osc2 based on the magnification selection signal fnAdjDlyx. The first-stage delay unit 221 and the second-stage delay sub-unit 223 are used to expand the period of the output second oscillation signal Osc2.

[0096] At this time, the period of the second oscillation signal Osc2 generated according to the first selection signal fnAdjDly1, the second selection signal fnAdjDly2 and the magnification selection signal fnAdjDlyx is shown in Table 3:

[0097] Table 3 Periodic table of Osc2

[0098]

[0099]

[0100] In another example, the selection unit 122 includes E selection subunits connected in series, and the rate selection signal fnAdjDlyx includes a sub-rate selection signal corresponding to each selection subunit; the first-level selection subunit is used to select the first oscillation signal Osc1 or the first delay signal Osc11 according to the corresponding sub-rate selection signal and input it into the second-level selection subunit; the F-th-level selection subunit is used to select the output signal of the F-1-th-level selection subunit or the F-th delay signal Osc1F according to the corresponding sub-rate selection signal and input it into the F+1-th-level selection subunit; the E-th-level selection subunit is used to select the E-1-th-level selection subunit according to the corresponding sub-rate selection signal. The output signal or the oscillation adjustment signal OscT is used as the second oscillation signal Osc2, where F is a positive integer less than E and greater than or equal to 2, that is, the first selection input terminal and the second selection input terminal of the selection unit 122 are respectively used to receive one of the oscillation adjustment signals (the first delay signal Osc11, the second delay signal Osc12...the Fth delay signal Osc1F) or the first oscillation signal Osc1, and select one of the oscillation adjustment signals (the first delay signal Osc11, the second delay signal Osc12...the Fth delay signal Osc1F) or one of the first oscillation signal Osc1 as the second oscillation signal Osc2 according to the multiplication factor selection signal.

[0101] Specifically, the F-th level selection subunit includes: a multiplier selector, the multiplier selector includes a first selection input terminal, a second selection input terminal, a selection signal terminal and a selection output terminal, the first selection input terminal and the second selection input terminal are respectively used to receive the output signal of the F-1th level selection subunit and the Fth delay signal Osc1F, the selection signal terminal is used to receive the corresponding sub-multiplier selection signal, and the selection output terminal is used to output the output signal of the F-1th level selection subunit or the Fth delay signal Osc1F; in this embodiment, the first selection input terminal is used to receive the output signal of the F-1th level selection subunit, and the second selection input terminal receives the Fth delay signal Osc1F; in other embodiments, the first selection input terminal may receive the Fth delay signal Osc1F, and the second selection input terminal may receive the output signal of the F-1th level selection subunit.

[0102] refer to Fig.10, the selection unit 122 includes three selection subunits connected in series, namely, a first-stage selection subunit 227, a second-stage selection subunit 228, and a third-stage selection subunit 229; wherein, the first-stage selection subunit 227 is used to select the first oscillation signal Osc1 or the first delay signal Osc11 to be input to the second-stage selection subunit 228, the second-stage selection subunit 228 is used to select the output signal of the first-stage selection subunit 227 or the second delay signal Osc12 to be input to the third-stage selection subunit 229, and the third-stage selection subunit 229 is used to select the output signal of the second-stage selection subunit 228 or the third delay signal Osc13 as the oscillation adjustment signal OscT. By connecting multiple selection subunits in series, more variation selections of the second oscillation signal Osc2 period are achieved.

[0103] It should be noted that, in the specific application process, the rate selection signal fnAdjDlyx, the first selection signal fnAdjDly1 and the second selection signal fnAdjDly2 can be realized by a multi-bit binary number, that is, the selection signal is a multi-bit binary number, one bit is used as the rate selection signal fnAdjDlyx, one bit is used as the first selection signal fnAdjDly1, and one bit is used as the second selection signal fnAdjDly2.

[0104] Continue to refer Figure 4 The pulse generating circuit 100 includes: a pulse conversion module 103, which receives the second oscillation signal Osc2 and outputs a pulse signal OscClk, wherein the pulse of the pulse signal OscClk is generated based on the rising edge or the falling edge of the second oscillation signal, and the pulse period of the pulse signal OscClk is the same as the oscillation period of the second oscillation signal.

[0105] Specifically, refer to Figure 5 The pulse conversion module 103 includes: a pulse converter 113, which is used to receive the second oscillation signal Osc2 and generate a pulse signal OscClk based on the second oscillation signal Osc2.

[0106] In one example, when the pulse converter 113 detects the rising edge of the second oscillation signal Osc2, it outputs a narrow upward pulse. The output end of the pulse converter 113 can also pass through a series inverter to output a narrow downward pulse. In another example, when the pulse converter 113 detects the rising edge of the second oscillation signal Osc2, it outputs a narrow downward pulse. The output end of the pulse converter 113 can also pass through a series inverter to output a narrow upward pulse. In addition, in this embodiment, the pulse converter 113 works based on the rising edge of the second oscillation signal Osc2. In other embodiments, the pulse converter can also work based on the falling edge of the second oscillation signal.

[0107] It should be noted that in the description of “generating the pulse signal OscClk based on the second oscillation signal Osc2”, the meaning of “based on” includes but is not limited to: detecting the rising edge of the second oscillation signal Osc2, or detecting that the second oscillation signal Osc2 changes from a low level to a high level (high level to a low level) and then generating a narrow pulse of the pulse signal OscClk.

[0108] It should be noted that, in the present embodiment, the pulse signal OscClk is generated based on the rising edge of the second oscillation signal Osc2 , and in other embodiments, the pulse signal may also be generated based on the falling edge of the second oscillation signal.

[0109] refer to Fig.11 When the control signal RasEn is at the effective level, the oscillation module 101 generates the first oscillation signal Osc1 with a period of T, and the period adjustment module 102 adjusts the period of the second oscillation signal Osc2 (Osc2′) according to the magnification selection signal fnAdjDlyx.

[0110] Specifically, if the multiplier selection signal fnAdjDlyx is changed during the period when the control signal RasEn is at the effective level, the second oscillation signal Osc2 generated at this time has a period change. Assuming that the period changes from T to 2T, the pulse period in the pulse signal OscClk generated at this time also changes from T to 2T; if the multiplier selection signal fnAdjDlyx is changed before the control signal RasEn is at the effective level, the second oscillation signal Osc2′ generated at this time does not have a period change, and the pulse period in the generated pulse signal OscClk′ also does not have a change in the pulse period.

[0111] refer to Fig.12 , when the activation signal Active is at an effective level, the generated first control signal ActEn is at an effective level; the first pulse generating unit 301 is used to generate a first oscillation signal Osc1 with a period of T and a second oscillation signal Osc2 with a period of 2T according to the first control signal ActEn; in the present embodiment, the second oscillation signal Osc2 has the same period as the first oscillation signal Osc1, and the first pulse signal ActClk is generated based on the rising edge of the second oscillation signal Osc2. The second pulse generating unit 302 is used to generate a first oscillation signal Osc1″ with a period of T and a second oscillation signal Osc2″ with a period of 2T according to the second control signal PreEn; in the present embodiment, the second oscillation signal Osc2″ has the same period as the first oscillation signal Osc1″, and the second pulse signal PreClk is generated based on the rising edge of the second oscillation signal Osc2″. The first pulse signal ActClk and the second pulse signal PreClk generated at this time are staggered pulse signals.

[0112] Specifically, the delayed signal output circuit includes: G signal output circuits 500, G is an integer greater than or equal to 2, the signal output circuit is used to receive an input signal, a first pulse signal ActClk and a second pulse signal PreClk, and output a delayed output signal; wherein, non-first-stage signal output circuits all receive the delayed output signal output by the previous-stage signal output circuit as the input signal of the current-stage signal output circuit, and the first-stage signal output circuit receives the initial input signal as the input signal of the first-stage signal output circuit; the rising edge of the delayed output signal generated by the signal output circuit has a first delay with the rising edge of the delayed output signal output by the previous-stage signal output circuit or the initial input signal; the falling delay of the delayed output signal generated by the signal output circuit has a second delay with the falling edge of the delayed output signal output by the previous-stage signal output circuit or the initial input signal.

[0113] Specifically, refer to Fig.13 The signal output circuit 500 includes: a first control module 501, which receives a first pulse signal ActClk and an input signal ActBnk0, and outputs a first adjustment signal ActLat, wherein a first preset edge of the first adjustment signal ActLat has a first delay relative to a rising edge of the input signal ActBnk0, and the first delay is a pulse period of the first pulse signal ActClk.

[0114] In one example, the rising edge or falling edge of the first pulse signal ActClk can be used to sample the input signal ActBnk0 and then output the first adjustment signal ActLat; or the rising edge or falling edge of the first pulse signal ActClk can be detected and then the input signal ActBnk0 can be outputted with delay, thereby obtaining the first adjustment signal ActLat.

[0115] In this embodiment, the first preset edge is taken as a rising edge as an example for illustration; specifically, the input signal ActBnk0 is an external input signal (compared to the signal output circuit 500), and the signal output circuit 500 is used to generate a delayed output signal ActBnk1 according to the input signal ActBnk0; wherein, the rising edge of the delayed output signal ActBnk1 is generated based on the rising edge of the first adjustment signal ActLat, and the rising edge of the first adjustment signal ActLat has a first delay with the rising edge of the input signal ActBnk0; that is, the rising edge of the delayed output signal ActBnk1 has a first delay with the rising edge of the input signal ActBnk0, and the first delay is the pulse period of the first pulse signal ActClk, from which it can be known that the externally input first pulse signal ActClk is used to adjust the delay of the rising edge of the delayed output signal ActBnk1. It should be noted that in other embodiments, the first preset edge can also be a falling edge.

[0116] It should be noted that in the description of “the rising edge of the delayed output signal ActBnk1 is generated based on the first preset edge of the first adjustment signal ActLat”, the meaning of “based on” includes but is not limited to: the rising edge of the delayed output signal ActBnk1 is generated upon detecting the first preset edge of the first adjustment signal ActLat, or the rising edge of the delayed output signal ActBnk1 is generated after detecting that the first adjustment signal ActLat changes from a low level to a high level (a high level to a low level).

[0117] In one example, refer to Fig.14 The first control module 501 includes a first D flip-flop 511, a clock end for receiving a first pulse signal ActClk, a reset end for receiving a first reset signal fnActEn, an input end for receiving an input signal ActBnk0, and an output end for outputting a first adjustment signal ActLat.

[0118] Continue to refer Fig.13 The signal output circuit 500 also includes: a second control module 502, which receives the second pulse signal PreClk and the input signal ActBnk0, and outputs a second adjustment signal PreLat, wherein the second preset edge of the second adjustment signal PreLat has a second delay relative to the falling edge of the input signal ActBnk0, and the second delay is the pulse period of the second pulse signal PreClk.

[0119] In this embodiment, the second preset edge is taken as a rising edge for example; specifically, the falling edge of the delayed output signal ActBnk1 is generated based on the rising edge of the second adjustment signal PreLat, and the rising edge of the second adjustment signal PreLat and the falling edge of the input signal ActBnk0 have a second delay; that is, the falling edge of the delayed output signal ActBnk1 and the falling edge of the input signal ActBnk0 have a second delay, and the second delay is the pulse period of the second pulse signal PreClk, so it can be known that the externally input second pulse signal PreClk is used to adjust the delay of the falling edge of the delayed output signal ActBnk1. It should be noted that in other embodiments, the second preset edge can also be a falling edge.

[0120] It should be noted that in the description of “the falling edge of the delayed output signal ActBnk1 is generated based on the second preset edge of the second adjustment signal PreLat”, the meaning of “based on” includes but is not limited to: the falling edge of the delayed output signal ActBnk1 is generated when the second preset edge of the second adjustment signal PreLat is detected, or the falling edge of the delayed output signal ActBnk1 is generated after the second adjustment signal PreLat is detected to change from a low level to a high level (a high level to a low level).

[0121] In one example, refer to Fig.15 The second control module 502 includes a second D flip-flop 512, a clock end for receiving a second pulse signal PreClk, a reset end for receiving a second reset signal fnPreEn, an input end for receiving an input signal ActBnk0, and an output end connected in series with an inverter to output a second adjustment signal PreLat.

[0122] In addition, in the present embodiment, one of the pulses of the first pulse signal ActClk is aligned with the rising edge of the input signal ActBnk0, and one of the pulses of the second pulse signal PreClk is aligned with the falling edge of the input signal ActBnk0. It should be noted that the "alignment" described here is not necessarily a perfect alignment under ideal conditions, and may include slight differences in the rising edge / falling edge due to factors such as circuit delay. By aligning one of the pulses of the first pulse signal ActClk with the rising edge of the input signal ActBnk0, the accuracy of the first delay between the first signal edge of the first adjustment signal ActLat and the rising edge of the input signal ActBnk0 is ensured; by aligning one of the pulses of the second pulse signal PreClk with the falling edge of the input signal ActBnk0, the accuracy of the second delay between the second signal edge of the second adjustment signal PreLat and the falling edge of the input signal ActBnk0 is ensured.

[0123] Continue to refer Fig.13 The signal output circuit 500 also includes: a signal output module 503, which receives the first adjustment signal ActLat and the second adjustment signal PreLat, and outputs a delayed output signal ActBnk1, wherein the rising edge of the delayed output signal ActBnk1 is generated based on the first preset edge of the first adjustment signal ActLat, and the falling edge of the delayed output signal ActBnk1 is generated based on the second preset edge of the second adjustment signal PreLat.

[0124] Specifically, refer to Fig.16 The signal output module 503 includes: a first receiving unit 513, receiving the first pulse signal ActClk and the first adjustment signal ActLat, and generating a first pulse control signal ActN when the first adjustment signal ActLat is at an effective level, wherein the pulse phase of the first pulse control signal ActN is the same as the pulse phase of the first pulse signal ActClk; a second receiving unit 523, receiving the second pulse signal PreClk and the second adjustment signal PreLat, and generating a second pulse control signal PreN when the second adjustment signal PreLat is at an effective level, wherein the pulse phase of the second pulse control signal PreN is the same as the pulse phase of the second pulse signal PreClk; a latch unit 533, receiving the first pulse control signal ActN and the second pulse control signal PreN, and delaying the output signal ActBnk1.

[0125] In one example, when the first adjustment signal ActLat is detected to be at an effective level, a first pulse control signal ActN is generated based on the inverter through the first pulse signal ActClk; when the second adjustment signal PreLat is detected to be at an effective level, a second pulse control signal PreN is generated based on the inverter through the second pulse signal PreClk.

[0126] In one example, refer to Fig.17 The first receiving unit 513 includes a first receiving NAND gate 601, which includes a first input terminal, a second input terminal and a first output terminal, wherein the first input terminal is used to receive the first adjustment signal ActLat, the second input terminal is used to receive the first pulse signal ActClk, and the first output terminal is used to output the first pulse control signal ActN. The second receiving unit 523 includes a second receiving NAND gate 602, which includes a third input terminal, a fourth input terminal and a second output terminal, wherein the third input terminal is used to receive the second adjustment signal PreLat, the fourth input terminal is used to receive the second pulse signal PreClk, and the second output terminal is used to output the second pulse control signal PreN. The latch unit 533 includes a latch 603, which includes a fifth input terminal, a sixth input terminal and a third output terminal, wherein the fifth input terminal is used to receive the first pulse control signal ActN, the sixth input terminal is used to receive the second pulse control signal PreN, and the third output terminal is used to output the delayed output signal ActBnk1.

[0127] The latch unit 603 is configured as follows: when the first pulse control signal ActN and the second pulse control signal PreN are at different levels, the delayed output signal ActBnk1 and the second pulse control signal PreN are at the same level; when the first pulse control signal ActN and the second pulse control signal PreN are at high levels, the latch unit 603 maintains the state.

[0128] Specifically, when the first pulse signal ActN and the second pulse control signal PreN are at a high level, the latch unit 603 maintains the state; when the first pulse control signal ActN is at a high level and the second pulse signal control signal PreN is at a low level, the latch unit 603 is at a low level; when the first pulse control signal ActN is at a low level and the second pulse signal control signal PreN is at a high level, the latch unit 603 is at a high level.

[0129] In another example, the first receiving unit 513 is further used to receive the first control signal ActEn, and the first receiving unit 513 is used to generate the first pulse control signal ActN according to the first pulse signal ActClk during the period when the first adjustment signal ActLat and the first control signal ActEn are at the effective level. The second receiving unit 523 is further used to receive the second control signal PreEn, and the second receiving unit 523 is used to generate the second pulse control signal PreN according to the second pulse signal PreClk during the period when the second adjustment signal PreLat and the second control signal PreEn are at the effective level.

[0130] refer to Fig.18 , the first receiving NAND gate 601 is also used to receive the first control signal ActEn, and the first receiving NAND gate 601 generates the first pulse control signal ActN according to the first clock signal ActClk, the first control signal ActEn and the first adjustment signal ActLat. The second receiving NAND gate 602 is also used to receive the second control signal PreEn, and the second receiving NAND gate 602 generates the second pulse control signal PreN according to the second clock signal PreClk, the second control signal PreEn and the second adjustment signal PreLat. Among them, the first control signal ActEn and the second control signal PreEn are inverted signals, the first pulse signal ActClk exists during the period when the first control signal ActEn is at an effective level, and the second pulse signal PreClk exists during the period when the second control signal PreEn is at an effective level. The first receiving NAND gate 601 and the second receiving NAND gate receive the first control signal ActEn and the second control signal PreEn respectively, so as to ensure the stability of the output of the first receiving NAND gate 601 and the second receiving NAND gate 602.

[0131] Furthermore, the first pulse signal ActClk and the second pulse signal PreClk are staggered pulse signals, that is, pulse signals generated according to inverted signals; in the present embodiment, the first pulse signal ActClk exists during the period when the first control signal ActEn is at a valid level, and the start pulse of the first pulse signal ActClk is aligned with the rising edge of the first control signal ActEn; the second pulse signal PreClk exists during the period when the second control signal PreEn is at a valid level, and the start pulse of the second pulse signal PreClk is aligned with the rising edge of the second control signal PreEn; it should be noted that the "alignment" described here is not necessarily a perfect alignment under ideal conditions, and may include slight differences in the rising / falling edges due to factors such as circuit delays.

[0132] In one example, refer to Fig.19, the input signal ActBnk0, the first pulse signal ActClk and the second pulse signal PreClk are external input signals; it is assumed that the period of the first pulse signal ActClk is t1, and the period of the second pulse signal PreClk is t2. Fig.15 , the first adjustment signal ActLat is generated based on the input signal ActBnk0 and the first pulse signal ActClk. When the first pulse signal ActClk is at a high level, the next state of the first adjustment signal ActLat is the current state of the input signal ActBnk0, resulting in a first delay between the rising edge of the first adjustment signal ActLat and the rising edge of the input signal ActBnk0. The first delay is the period of the first pulse signal ActClk, that is, the delay between the rising edge of the first adjustment signal ActLat and the rising edge of the input signal ActBnk0 is t1. Fig.16 , the second adjustment signal PreLat is generated based on the input signal ActBnk0 and the second pulse signal PreClk. When the second pulse signal PreClk is at a high level, the next state of the second adjustment signal PreLat is the current state of the input signal ActBnk0, resulting in a second delay between the rising edge of the second adjustment signal PreLat and the falling edge of the input signal ActBnk0. The second delay is the period of the second pulse signal PreClk, that is, the delay between the rising edge of the second adjustment signal PreLat and the falling edge of the input signal ActBnk0 is t2. Combined Fig.18 In order to ensure the stability of the output of the first receiving NAND gate 601 and the second receiving NAND gate 602, the first receiving NAND gate 601 is also used to receive the first control signal ActEn, and the second receiving NAND gate 602 is also used to receive the second control signal PreEn, and the first control signal ActEn and the second control signal PreEn are inverted signals. At this time, the first receiving NAND gate 601 and the second receiving NAND gate 602 respectively generate the first pulse control signal ActN and the second pulse control signal PreN. The latch unit 603 generates a delayed output signal ActBnk1 according to the first pulse control signal ActN and the second pulse control signal PreN. The rising edge of the delayed output signal ActBnk1 has a first delay with the rising edge of the input signal ActBnk0, and the first delay is the pulse period t1 of the first pulse signal ActClk; the falling edge of the delayed output signal ActBnk1 has a second delay with the falling edge of the input signal ActBnk0, and the second delay is the pulse period t2 of the second pulse signal PreClk. In this embodiment, the pulse periods of the first pulse signal ActClk and the second pulse signal PreClk are equal, that is, the signal change edge of the delayed output signal ActBnk1 is delayed by the same time relative to the signal change edge of the input signal ActBnk0.

[0133] It should be noted that Figure 7 The timing diagrams of the given signals are only used to interpret the circuit functions of the signal output circuit 500 provided in this embodiment, and do not constitute a limitation of this embodiment; in other embodiments, a corresponding delayed input signal can be generated according to other input signals; in addition, the input signal may also be inconsistent with the first control signal.

[0134] It should be noted that, in other embodiments, the signal output circuit further includes an even number of inverters, and the inverters are connected in series with the output end of the signal output module to enhance the driving capability of the signal output circuit.

[0135] refer to Fig. 20 In this embodiment, the delayed signal output circuit 700 includes 7 of the above-mentioned signal output circuits 500 as an example for specific description, which does not constitute a limitation of this embodiment, specifically, a first-level signal output circuit 701, a second-level signal output circuit 702, a third-level signal output circuit 703, a fourth-level signal output circuit 704, a fifth-level signal output circuit 705, a sixth-level signal output circuit 706, and a seventh-level signal output circuit 707. In other embodiments, the delayed signal output circuit includes more than or equal to 2 signal output circuits.

[0136] Specifically, the first-stage signal output circuit 701 generates a first-stage delayed output signal ActBnk1 according to the initial input signal ActBnk0, the first pulse signal ActClk and the second pulse signal PreClk. The rising edge of the first-stage delayed output signal ActBnk1 has a first delay relative to the rising edge of the initial input signal ActBnk0, and the first delay is the pulse period t1 of the first pulse signal ActClk; the falling edge of the first-stage delayed output signal ActBnk1 has a second delay relative to the falling edge of the initial input signal ActBnk0, and the second delay is the pulse period t2 of the second pulse signal PreClk.

[0137] The second-stage signal output circuit 702 generates a second-stage delayed output signal ActBnk2 according to the first-stage delayed output signal ActBnk1, the first pulse signal ActClk and the second pulse signal PreClk. The rising edge of the second-stage delayed output signal ActBnk2 has a first delay relative to the first-stage delayed output signal ActBnk1; the falling edge of the second-stage delayed output signal ActBnk2 has a second delay relative to the first-stage delayed output signal ActBnk1.

[0138] The third-level signal output circuit 703 generates a third-level delayed output signal ActBnk3 according to the second-level delayed output signal ActBnk2, the first pulse signal ActClk and the second pulse signal PreClk. The rising edge of the third-level delayed output signal ActBnk3 has a first delay relative to the second-level delayed output signal ActBnk2; the falling edge of the third-level delayed output signal ActBnk3 has a second delay relative to the second-level delayed output signal ActBnk2.

[0139] The fourth-level signal output circuit 704 generates a fourth-level delayed output signal ActBnk4 according to the third-level delayed output signal ActBnk3, the first pulse signal ActClk and the second pulse signal PreClk. The rising edge of the fourth-level delayed output signal ActBnk4 has a first delay relative to the third-level delayed output signal ActBnk3; the falling edge of the fourth-level delayed output signal ActBnk4 has a second delay relative to the third-level delayed output signal ActBnk3.

[0140] The fifth-level signal output circuit 705 generates a fifth-level delayed output signal ActBnk5 according to the fourth-level delayed output signal ActBnk4, the first pulse signal ActClk and the second pulse signal PreClk. The rising edge of the fifth-level delayed output signal ActBnk5 has a first delay relative to the fourth-level delayed output signal ActBnk4; the falling edge of the fifth-level delayed output signal ActBnk5 has a second delay relative to the fourth-level delayed output signal ActBnk4.

[0141] The sixth-level signal output circuit 706 generates a sixth-level delayed output signal ActBnk6 according to the fifth-level delayed output signal ActBnk5, the first pulse signal ActClk and the second pulse signal PreClk. The rising edge of the sixth-level delayed output signal ActBnk6 has a first delay relative to the fifth-level delayed output signal ActBnk5; the falling edge of the sixth-level delayed output signal ActBnk6 has a second delay relative to the fifth-level delayed output signal ActBnk5.

[0142] The seventh-level signal output circuit 707 generates a seventh-level delayed output signal ActBnk7 according to the sixth-level delayed output signal ActBnk6, the first pulse signal ActClk and the second pulse signal PreClk. The rising edge of the seventh-level delayed output signal ActBnk7 has a first delay relative to the sixth-level delayed output signal ActBnk6; the falling edge of the seventh-level delayed output signal ActBnk7 has a second delay relative to the sixth-level delayed output signal ActBnk6.

[0143] refer to Fig.21More specifically, in this embodiment, the first control module of the signal output circuit is also used to receive the first control signal ActEn, and the second control module of the signal output circuit is also used to receive the second control signal PreEn, wherein the first pulse signal ActClk and the second pulse signal PreClk are inverted signals; each level of the signal output circuit is used to generate a delayed output signal of the current level according to the first control signal ActEn, the second control signal PreEn, the first pulse signal ActClk, the second pulse signal PreClk and the delayed output signal output by the previous level of the signal output circuit, and by receiving the first control signal ActEn and the second control signal PreEn, the stability of the output of the signal output circuit is ensured.

[0144] Continue to refer Fig.21 In this embodiment, the delayed signal output circuit 700 further includes: an initial signal output circuit 710, including a first control module, a second control module and a signal output module; the first control module is used to receive the first pulse signal ActClk and the first power signal Vdd, and generate a first adjustment signal (not shown) according to the first pulse signal ActClk and the first power signal Vdd; the second control module of the output signal output circuit is used to receive the second pulse signal PreClk and the second power signal Vss and generate a second adjustment signal (not shown) according to the second pulse signal PreClk and the second power signal Vss; the signal output module is used to generate the initial input signal according to the first adjustment signal (not shown) and the second adjustment signal (not shown). The delayed output signal of the initial signal output circuit generated according to the first power signal Vdd and the second power signal Vss, that is, the initial input signal ActBnk0 output by the initial output circuit 710 according to the initial signal can avoid the delay caused by the circuit elements of the signal output circuit compared with the input signal ActBnk0 directly input from the outside. The circuit of the initial signal output circuit 710 here may be consistent with the signal output circuit described above, and will not be described in detail here, but this embodiment is not limited to this.

[0145] In one example, refer to Fig. 22 and Fig.23, the figure takes the delayed signal output circuit 700 composed of four signal output circuits as an example for introduction. The first clock terminal ActClk of the signal output circuit is used to receive the first pulse signal ActClk; the second clock terminal PreClk of the signal output circuit is used to receive the second pulse signal PreClk; the first control terminal ActEn of the signal output circuit is used to receive the first control signal ActEn; the second control terminal PreEn of the signal output circuit is used to receive the second control signal PreEn; the signal output terminal ActBnk of the signal output circuit is used to output the delayed output signal of the current stage; the signal output circuit also includes a first signal terminal ActEnPre and a second signal terminal PreEnPre (a signal input terminal of the signal output circuit), combined with Fig.23 The first signal terminal ActEnPre of the initial signal output circuit is used to receive the first power signal Vdd, and the second signal terminal PreEnPre of the initial signal output circuit is used to receive the second power signal Vss; the first signal terminal ActEnPre and the second signal terminal PreEnPre of other signal output circuits are used to receive the delayed output signal output by the previous stage signal output circuit.

[0146] refer to Fig.21 and Fig.24 The first-level signal output circuit 701 generates a first-level delayed output signal ActBnk1 according to the initial input signal ActBnk0, the second-level signal output circuit 702 generates a second-level delayed output signal ActBnk2 according to the first-level delayed output signal ActBnk1, the third-level signal output circuit 703 generates a third-level delayed output signal ActBnk3 according to the second-level delayed output signal ActBnk2, the fourth-level signal output circuit 704 generates a fourth-level delayed output signal ActBnk4 (not shown) according to the third-level delayed output signal ActBnk3, the fifth-level signal output circuit 705 generates a fifth-level delayed output signal ActBnk5 (not shown) according to the fourth-level delayed output signal ActBnk4, the sixth-level signal output circuit 706 generates a sixth-level delayed output signal ActBnk6 (not shown) according to the fifth-level delayed output signal ActBnk5, and the seventh-level signal output circuit 707 generates a seventh-level delayed output signal ActBnk7 (not shown) according to the sixth-level delayed output signal ActBnk6.

[0147] Compared with the related art, a first oscillation signal is generated according to a control signal, that is, when the control signal is at an effective level, a first oscillation signal with a certain period is generated; a second oscillation signal is generated based on the first oscillation signal according to a magnification selection signal, that is, based on the magnification selection signal, the period of the first oscillation signal is changed to generate a corresponding second oscillation signal; then the second oscillation signal is used as a signal source to generate a pulse signal, and the pulse period of the generated pulse signal is the same as the oscillation period of the second oscillation signal; in the process of generating the pulse signal, if the magnification selection signal changes, the amplitude of the period of the first oscillation signal is adjusted to change, so that the period of the generated second oscillation signal changes ization, thereby generating a first pulse signal and a second pulse signal with adjustable periods; and generating a delay signal with controllable delay according to the first pulse signal and the second pulse signal, wherein the delay signal has a first delay on the rising edge and a second delay on the falling edge relative to the input signal; the first delay is the pulse period of the first pulse signal, and the second delay is the pulse period of the second pulse signal, so the delay time of the delay signal can be adjusted by adjusting the pulse periods of the first pulse signal and the second pulse signal; at the same time, the delay time of the delay signal does not need to connect more delay units, thereby simplifying the circuit structure, making the circuit layout area small and the circuit power consumption low.

[0148] It is worth mentioning that all units involved in this embodiment are logical units. In practical applications, a logical unit may be a physical unit, or a part of a physical unit, or may be implemented as a combination of multiple physical units. In addition, in order to highlight the innovative part of the present invention, this embodiment does not introduce units that are not closely related to solving the technical problem proposed by the present invention, but this does not mean that there are no other units in this embodiment.

[0149] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present invention, and that in actual applications, various changes may be made in form and detail without departing from the spirit and scope of the present invention.

Claims

1. An interleaved signal generating circuit, characterized in that: include: An interlaced pulse generating circuit, used for generating a first pulse signal according to a first control signal, and generating a second pulse signal according to a second control signal, wherein the first control signal and the second control signal are anti-phase signals, and the first pulse signal and the second pulse signal are interlaced pulse signals; wherein the first pulse signal and the second pulse signal are valid in different time periods, and the first pulse signal has a plurality of pulses in its valid time period, and the second pulse signal has a plurality of pulses in its valid time period; A delayed signal output circuit, comprising G signal output circuits, where G is an integer greater than or equal to 2, and the signal output circuit is used to receive an input signal, the first pulse signal, and the second pulse signal, and output a delayed output signal; Among them, the non-first-stage signal output circuits all receive the delayed output signal output by the previous-stage signal output circuit as the input signal of the current-stage signal output circuit, and the first-stage signal output circuit receives the initial input signal as the input signal of the first-stage signal output circuit; The rising edge of the delayed output signal generated by the signal output circuit has a first delay with the rising edge of the delayed output signal output by the previous-stage signal output circuit or the initial input signal, and the first delay is the pulse period of the first pulse signal; the falling edge of the delayed output signal generated by the signal output circuit has a second delay with the falling edge of the delayed output signal output by the previous-stage signal output circuit or the initial input signal, and the second delay is the pulse period of the second pulse signal.

2. The interleaved signal generating circuit according to claim 1, characterized in that: The pulse periods of the first pulse signal and the second pulse signal are equal.

3. The interleaved signal generating circuit according to claim 1, characterized in that: The staggered pulse generating circuit comprises: a signal generating module, configured to generate the first control signal and the second control signal according to an activation signal; A first pulse generating unit, configured to generate the first pulse signal according to the first control signal; The second pulse generating unit is used to generate the second pulse signal according to the second control signal.

4. The interleaved signal generating circuit according to claim 3, characterized in that: The signal generating module comprises: a reset unit, receiving a first reset signal and the activation signal, and generating the first control signal based on the first reset signal and the activation signal; The inverting unit receives the first control signal and generates the second control signal based on the first control signal.

5. The interleaved signal generating circuit according to claim 4, characterized in that: The signal generating module also includes: a reset signal generating unit, which is used to generate a second reset signal according to the first reset signal and the first control signal, so that when the first reset signal is in a reset state, the second reset signal is also in a reset state, and when the first reset signal is in a non-reset state, the second reset signal generates a reset narrow pulse based on the changing edge of the first control signal.

6. The interleaved signal generating circuit according to claim 3, characterized in that: The first pulse generating unit comprises: an oscillation module, receiving a first control signal and generating a first oscillation signal according to the first control signal; a period adjustment module, receiving the first oscillation signal and a magnification selection signal, and outputting a second oscillation signal, wherein the period of the second oscillation signal is the period of the first oscillation signal after being adjusted based on the magnification selection signal; A pulse conversion module receives the second oscillation signal and outputs a pulse signal, wherein the pulse of the first pulse signal is generated based on the signal change edge of the second oscillation signal, and the pulse period of the first pulse signal is the same as the oscillation period of the second oscillation signal.

7. The interleaved signal generating circuit according to claim 6, characterized in that: The second pulse generating unit has the same circuit structure as the first pulse generating unit.

8. The interleaved signal generating circuit according to claim 6, characterized in that: The cycle adjustment module includes: a delay unit, receiving the first oscillation signal, and generating an oscillation adjustment signal based on the first oscillation signal, wherein a period of the oscillation adjustment signal is different from a period of the first oscillation signal; The selection unit receives the magnification selection signal and selects the first oscillation signal or the oscillation adjustment signal as the second oscillation signal based on the magnification selection signal.

9. The interleaved signal generating circuit according to claim 8, characterized in that: The delay unit includes E delay sub-units connected in series, the oscillation adjustment signal includes E delay signals, and E is a positive integer; A first-stage delay subunit, configured to generate a first delay signal according to the first oscillation signal, and input the first delay signal into a second-stage delay subunit; The Fth delay subunit is used to generate an Fth delay signal according to the F-1th delay signal, where F is a positive integer less than or equal to E and greater than or equal to 2.

10. The interleaved signal generating circuit according to claim 9, characterized in that: The selection unit includes: a multiplier selector, which includes a first selection input terminal, a second selection input terminal, a selection signal terminal and a selection output terminal, wherein the first selection input terminal and the second selection input terminal are respectively used to receive one of the oscillation adjustment signals or the first oscillation signal, the selection signal terminal is used to receive the multiplier selection signal, and the selection output terminal is used to output the second oscillation signal.

11. The interleaved signal generating circuit according to claim 6, characterized in that: The oscillation module comprises: An oscillating unit and a triggering unit connected to the oscillating unit; The trigger unit is configured to receive a reset signal and the first control signal, and trigger the oscillation unit based on the reset signal and the first control signal; After being triggered, the oscillation unit is used to generate the first oscillation signal according to the first control signal.

12. The interleaved signal generating circuit according to claim 11, characterized in that: The oscillation unit comprises: a ring oscillator formed by A inverters connected in series, wherein A is a positive odd number.

13. The interleaved signal generating circuit according to claim 12, characterized in that: The oscillation module further comprises: A first inverter group includes B inverters connected in series, where B is a positive even number; The first selection unit is used to receive a first selection signal and, based on the first selection signal, connect the first inverter group in series between adjacent inverters in the ring oscillator.

14. The interleaved signal generating circuit according to claim 6, characterized in that: The pulse conversion module includes: a pulse converter, configured to receive the second oscillation signal and generate the first pulse signal based on the second oscillation signal.

15. The interleaved signal generating circuit according to claim 1, characterized in that: The signal output circuit comprises: a first control module, receiving the first pulse signal and the input signal, and outputting a first adjustment signal, wherein a first preset edge of the first adjustment signal has a first delay relative to a rising edge of the input signal; a second control module, receiving the second pulse signal and the input signal, and outputting a second adjustment signal, wherein a second preset edge of the second adjustment signal has a second delay relative to a falling edge of the input signal; A signal output module receives the first adjustment signal and the second adjustment signal, and outputs a delayed output signal, wherein a rising edge of the delayed output signal is generated based on a first preset edge of the first adjustment signal, and a falling edge of the delayed output signal is generated based on a second preset edge of the second adjustment signal.

16. The interleaved signal generating circuit according to claim 15, characterized in that: The signal output module comprises: a first receiving unit, receiving the first pulse signal and the first adjustment signal, and generating a first pulse control signal during a period when the first adjustment signal is at a valid level, wherein a pulse phase of the first pulse control signal is the same as a pulse phase of the first pulse signal; a second receiving unit, receiving the second pulse signal and the second adjustment signal, and generating a second pulse control signal during a period when the second adjustment signal is at a valid level, wherein a pulse phase of the second pulse control signal is the same as a pulse phase of the second pulse signal; A latch unit receives the first pulse control signal and the second pulse control signal, and generates the delayed output signal.

17. The interleaved signal generating circuit according to claim 16, characterized in that: The first receiving unit is further configured to receive a first control signal, and the first receiving unit is configured to generate the first pulse control signal according to the first pulse signal during a period in which the first adjustment signal and the first control signal are at valid levels.

18. The interleaved signal generating circuit according to claim 16, characterized in that: The second receiving unit is further configured to receive a second control signal, and the second receiving unit is configured to generate the second pulse control signal according to the second pulse signal during a period in which the second adjustment signal and the second control signal are at valid levels.

19. The interleaved signal generating circuit according to claim 1, characterized in that: The delay signal output circuit also includes: An initial signal output circuit comprises a first control module, a second control module and a signal output module; The first control module is used to receive a first pulse signal and a first power signal, and generate a first adjustment signal according to the first pulse signal and the first power signal; The second control module is used to receive a second pulse signal and a second power signal, and generate a second adjustment signal according to the second pulse signal and the second power signal; The signal output module is used to generate the initial input signal according to the first adjustment signal and the second adjustment signal.

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