A phase locking method, apparatus, device and storage medium

Abstract

The application discloses a phase locking method and device, equipment and a storage medium, wherein the method comprises the following steps: acquiring a phase difference between an input signal and a feedback signal of a digital phase-locked loop; in the case that the phase difference is greater than a phase difference threshold, adjusting a phase value of the feedback signal based on the phase difference, so as to reduce the phase difference between the input signal and the feedback signal; and compensating an output signal of the digital phase-locked loop based on the phase difference, so as to realize phase locking.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of electronics, and relate to but are not limited to a phase locking method, device, equipment and storage medium. BACKGROUND

[0002] In a Time Division Duplex (TDD) system communication device, a 4G / 5G indoor Building Base band Unit (BBU) device needs to connect a Global Positioning System (GPS) clock source and the like to perform time synchronization, so as to guarantee uplink and downlink time slot alignment of the system.

[0003] In the case of using a 1 second pulse (PPS) synchronization signal generated by a GPS clock source and the like, a Digital Phase-Locked Loop (DPLL) is usually used to perform frequency locking, so as to generate a clock frequency point, phase de-bouncing and phase locking required by a single board. Here, the DPLL is a phase-locked loop formed by using digital signal processing technology and a digital circuit.

[0004] In the case of using the DPLL to perform phase locking, since a Numerically Controlled Oscillator (NCO) in the DPLL freely oscillates to generate an initial 1PPS signal or a 1PPS signal is lost for a long time, and there is a large phase difference between the 1PPS signal input by the signal source, the DPLL locking time is very long (the bandwidth of the loop filter is usually at least less than 1 / 20 of the frequency of the phase discriminator, and the bandwidth of the loop filter cannot be greater than 50mH when tracking 1PPS, and the loop bandwidth is small and the tracking is slow). Thus, the use requirement of a user for the output clock of the DPLL cannot be met.

[0005] In the prior art, the rising edge of the 1PPS signal at the input end of the DPLL is used as a reset signal, and the output signal and the feedback signal of the DPLL are reset at the same time, so that the 1PPS phase of the output signal and the input signal is aligned, but during the reset period, there is no 1PPS output at the output end, and the problem of losing seconds exists. SUMMARY

[0006] In view of this, embodiments of the present application provide a phase locking method, device, equipment and storage medium.

[0007] The technical scheme of the embodiments of the present application is implemented as follows:

[0008] In a first aspect, an embodiment of the present application provides a phase locking method, which comprises: obtaining a phase difference between an input signal and a feedback signal of a digital phase-locked loop; in a case where the phase difference is determined to be greater than a phase difference threshold, adjusting a phase value of the feedback signal based on the phase difference, so as to reduce the phase difference between the input signal and the feedback signal; and compensating an output signal of the digital phase-locked loop based on the phase difference, so as to realize phase locking.

[0009] In a second aspect, an embodiment of the present application provides a phase locking device, which comprises: an obtaining module, configured to obtain a phase difference between an input signal and a feedback signal of a digital phase-locked loop; a first adjusting module, configured to, in a case where the phase difference is determined to be greater than a phase difference threshold, adjust a phase value of the feedback signal based on the phase difference, so as to reduce the phase difference between the input signal and the feedback signal; and a compensating module, configured to compensate an output signal of the digital phase-locked loop based on the phase difference, so as to realize phase locking.

[0010] In a third aspect, an embodiment of the present application provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program capable of running on the processor, and the processor realizes the above method when executing the program.

[0011] In a fourth aspect, an embodiment of the present application provides a storage medium, which stores executable instructions for causing a processor to execute the above method.

[0012] In the embodiment of the present application, first, a phase difference between an input signal and a feedback signal of a digital phase-locked loop is obtained; then, in a case where the phase difference is determined to be greater than a phase difference threshold, a phase value of the feedback signal is adjusted based on the phase difference, so as to reduce the phase difference between the input signal and the feedback signal; and an output signal of the digital phase-locked loop is compensated based on the phase difference, so as to realize phase locking. In this way, in a case where the phase difference is determined to be greater than the phase difference threshold, the phase difference can be directly compensated in a digital domain based on the phase difference between the input signal and the feedback signal, and the phase can be locked quickly. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 A schematic diagram of a DPLL architecture provided by an embodiment of the present application;

[0014] Figure 2 An implementation flowchart of a phase locking method provided by an embodiment of the present application;

[0015] Figure 3 An implementation flowchart of a method for aligning a phase of an output signal with a phase of an input signal provided by an embodiment of the present application;

[0016] Figure 4An implementation flowchart of a phase locking method provided by an embodiment of the present application is shown in the figure.

[0017] Figure 5 An assembly structure diagram of a phase locking device provided by an embodiment of the present application is shown in the figure.

[0018] Figure 6 A hardware entity diagram of an electronic device provided by an embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0019] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the specific technical solutions of the embodiments of the present application will be further described in detail below with reference to the accompanying drawings of the embodiments of the present application. The following embodiments are used to illustrate the present application, but are not used to limit the scope of the present application.

[0020] In the following description, “some embodiments” are described, which describe a subset of all possible embodiments, but it can be understood that “some embodiments” can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0021] In the following description, the terms “first\second\third” are only to distinguish similar objects, and do not represent a specific order of the objects. It can be understood that “first\second\third” can be interchanged in a specific order or sequence as allowed, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application, and are not intended to limit the present application.

[0023] Figure 1 An implementation flowchart of a phase locking method provided by an embodiment of the present application is shown in the figure. Figure 1 As shown in the figure, the DPLL includes a digital phase discriminator 11, a loop filter (Digital Loop Filter, DLF) 12, a digital control oscillator (Digital Control Oscillator, NCO) 13, a first divider 14 and a second divider 15, wherein,

[0024] Phase detector 11, also known as sampling phase detector, is used to compare the phase of input signal and the phase of voltage controlled oscillator output signal (feedback signal), and the output voltage is a function of the phase difference between the two signals. Phase detector is a key component in phase-locked loop, and the form of digital phase detector can be divided into: zero-crossing sampling phase detector, flip-flop type digital phase detector, lead-lag type digital phase detector and Nyquist rate sampling phase detector.

[0025] Loop filter 12 plays a role of restraining input noise in the loop, and adjusts the correction speed of the loop.

[0026] Digital control oscillator 13, also known as digital clock, is in the same position in the digital loop as the voltage controlled oscillator in the analog phase-locked loop. The output of digital control oscillator is a pulse sequence, and the period of the output pulse sequence is controlled by the correction signal sent by the digital loop filter. The control feature is that the correction signal obtained at the previous sampling time will change the pulse time position at the next sampling time.

[0027] First frequency divider 14 and second frequency divider 15 are both used to divide the oscillation signal output by digital control oscillator 13.

[0028] In the implementation process, first, the phase difference between the input signal of phase detector 11 in the digital phase detector (input signal) and the feedback signal (feedback signal) is obtained; then, the phase value of the feedback signal is adjusted in the value domain based on the phase difference, so as to realize the fast locking of the phase of the digital phase detector, and at the same time, the output port signal (output signal) of the corresponding first frequency divider 14 is processed in advance or delayed, so as to realize the phase synchronization of the input signal and the output signal.

[0029] The advantage of using the digital phase-locked loop to lock the phase of the signal is that the phase is locked quickly, and no seconds are lost in the fast locking process.

[0030] The embodiment of the present application provides a data phase-locked loop, which comprises:

[0031] A phase detector is configured to obtain a phase difference between an input signal and a feedback signal of the digital phase-locked loop.

[0032] Here, the phase detector can first obtain the phase of the input signal and the phase of the feedback signal output by the voltage controlled oscillator, and then determine the phase difference between the input signal and the feedback signal.

[0033] A processor is configured to adjust a phase value of the feedback signal based on the phase difference to reduce the phase difference between the input signal and the feedback signal, when the phase difference is greater than a phase difference threshold.

[0034] Here, the processor can be a processor connected with the digital phase-locked loop, which is used to process various different signals in the digital phase-locked loop.

[0035] The phase difference threshold value can be set by a user according to actual needs, and in a case where it is determined that the phase difference is greater than the phase difference threshold value, the phase value of the feedback signal can be adjusted in the numerical domain based on the phase difference to reduce the phase difference between the input signal and the feedback signal, so as to realize fast locking of the digital phase-locked loop.

[0036] The processor is further configured to compensate an output signal of the digital phase-locked loop based on the phase difference to realize phase locking.

[0037] In the implementation process, while the phase value of the feedback signal is adjusted based on the phase difference, the output signal of the digital phase-locked loop is compensated based on the phase difference to realize phase synchronization of the input signal and the output signal.

[0038] In the embodiments of the present application, the phase detector is configured to obtain a phase difference between an input signal and a feedback signal of the digital phase-locked loop; the processor is configured to, in a case where it is determined that the phase difference is greater than a phase difference threshold value, adjust a phase value of the feedback signal based on the phase difference to reduce the phase difference between the input signal and the feedback signal; and compensate an output signal of the digital phase-locked loop based on the phase difference to realize phase locking. In this way, in the case where it is determined that the phase difference is greater than the phase difference threshold value, the phase difference can be directly compensated in the digital domain based on the phase difference between the input signal and the feedback signal, and the phase can be quickly locked.

[0039] In some embodiments, the above-mentioned digital phase-locked loop further comprises:

[0040] The first register is configured to provide phase register service for the feedback signal.

[0041] Here, the first register can be a register configured to provide phase register service for the feedback signal.

[0042] The processor is further configured to, in a case where it is determined that the phase difference is greater than a phase difference threshold value, register the phase difference to the first register.

[0043] In the implementation process, the first register is configured to register the phase difference between the input signal and the feedback signal to compensate the phase difference to the feedback signal in time, reduce the phase difference between the input signal and the feedback signal of the phase detector, and realize fast locking of the phase of the digital phase-locked loop.

[0044] The second register is configured to provide phase register service for the output signal.

[0045] Here, the second register can be a register configured to provide phase register service for the output signal.

[0046] In some embodiments, the second register and the first register can share one register, and the functions of the first register and the second register are respectively realized by setting different storage spaces in the register.

[0047] In some embodiments, the second register and the first register can be different registers.

[0048] The processor is further configured to, in a case where the phase difference is greater than a phase difference threshold, register the phase difference to the second register.

[0049] In the implementation process, the phase difference can be registered to the second register at the same time when the phase difference is registered to the first register, so as to compensate the output signal of the digital phase-locked loop based on the phase difference.

[0050] In the embodiments of the present application, the first register and the second register can be arranged in the digital phase-locked loop, and are respectively used to provide phase registration services for the feedback signal and the output signal, so as to compensate the phase difference to the feedback signal in time, reduce the phase difference between the input signal and the feedback signal of the phase detector, realize the fast locking of the phase of the digital phase-locked loop, and compensate the output signal of the digital phase-locked loop based on the phase difference, so as to realize the phase synchronization of the input signal and the output signal.

[0051] The embodiments of the present application provide a phase locking method, as shown in Figure 2 The method comprises the following steps.

[0052] In step S210, the phase difference between the input signal and the feedback signal of the digital phase-locked loop is obtained.

[0053] Here, as shown in Figure 1 The phase of the input signal and the phase of the feedback signal of the digital phase-locked loop can be obtained by using the phase detector 11 in the digital phase-locked loop, and then the phase difference can be determined based on the phase of the input signal and the phase of the feedback signal.

[0054] In step S220, in a case where the phase difference is greater than a phase difference threshold, the phase value of the feedback signal is adjusted based on the phase difference, so as to reduce the phase difference between the input signal and the feedback signal.

[0055] In step S230, the output signal of the digital phase-locked loop is compensated based on the phase difference, so as to realize phase locking.

[0056] In the implementation process, the step S220 and the step S230 are not distinguished by the execution sequence, and can be executed simultaneously. In this way, after the step S220 and the step S230 are executed, the phase difference between the two input signals (the input signal and the feedback signal) of the phase detector can be reduced, and the phase of the digital phase-locked loop is quickly locked. At the same time, according to the phase difference value compensated at the feedback end, the corresponding output signal is processed in advance or delayed, and the phase synchronization of the input signal and the output signal is realized.

[0057] In the embodiment of the present application, first, the phase difference between the input signal and the feedback signal of the digital phase-locked loop is obtained. Then, in the case where the phase difference is greater than the phase difference threshold, the phase value of the feedback signal is adjusted based on the phase difference, so as to reduce the phase difference between the input signal and the feedback signal. The output signal of the digital phase-locked loop is compensated based on the phase difference, so as to realize phase locking. In this way, in the case where the phase difference is greater than the phase difference threshold, the phase difference can be directly compensated in the digital domain based on the phase difference between the input signal and the feedback signal, and the phase is quickly locked.

[0058] In some embodiments, the above step S220 “in the case where the phase difference is greater than the phase difference threshold, the phase value of the feedback signal of the digital phase-locked loop is adjusted based on the phase difference, so as to reduce the phase difference between the input signal and the feedback signal” can be realized by the following process:

[0059] In the case where the phase difference is greater than the phase difference threshold, the phase difference is stored in the first register of the digital phase-locked loop, so as to compensate the phase difference between the input signal and the feedback signal, wherein the first register provides phase register service for the feedback signal.

[0060] Here, the first register is used to provide phase register service for the feedback signal, and register the phase difference between the input signal and the feedback signal.

[0061] In the implementation process, the feedback signal is compensated by obtaining the phase difference from the first register, so as to reduce the phase difference between the input signal and the feedback signal of the phase detector.

[0062] In the embodiment of the present application, the first register is used to store the phase difference, and realize the phase compensation of the feedback signal.

[0063] In some embodiments, the above step S230 “the output signal of the digital phase-locked loop is compensated based on the phase difference, so as to realize phase locking” can be realized by the following process:

[0064] store the phase difference in a second register of the digital phase-locked loop to compensate the output signal based on the phase difference, align the phase of the output signal with the phase of the input signal, and achieve phase lock, wherein the second register provides phase register service for the output signal.

[0065] Here, the second register is configured to provide phase register service for the output signal; and the phase difference between the input signal and the feedback signal is stored in the second register.

[0066] In some embodiments, the second register and the first register can share one register, and the functions of the first register and the second register are realized by setting different storage spaces in the register.

[0067] In some embodiments, the second register and the first register can be different registers.

[0068] In the implementation process, the phase of the output signal is aligned with the phase of the input signal by obtaining the phase difference compensation output signal from the second register.

[0069] In the embodiments of the present application, the phase difference is stored in the second register to compensate the phase of the output signal, align the phase of the output signal with the phase of the input signal, and achieve phase lock.

[0070] In some embodiments, the above step S230 of compensating the output signal of the digital phase-locked loop based on the phase difference to achieve phase lock can be implemented by the following steps:

[0071] Step 231, determining the time delay relationship between the time delay of the output signal and the time delay of the input signal based on the phase difference;

[0072] Step 232, aligning the phase of the output signal with the phase of the input signal based on the time delay relationship to achieve phase lock.

[0073] In the embodiments of the present application, the time delay relationship between the time delay of the output signal and the time delay of the input signal is first determined based on the phase difference; and then the phase alignment of the output signal and the input signal can be achieved based on the time delay relationship.

[0074] In some embodiments, as shown in Figure 3 The above step 232 of aligning the phase of the output signal with the phase of the input signal based on the time delay relationship to achieve phase lock can be implemented by the following steps:

[0075] Step S310, determining the advance period of the output signal based on the phase difference in the case that the time delay of the output signal is greater than the time delay of the input signal based on the time delay relationship;

[0076] Step S320, outputting the output signal based on the advance period, aligning the phase of the output signal with the phase of the input signal, and realizing phase locking.

[0077] In the implementation process, when it is determined that the time delay of the output signal is greater than the time delay of the input signal, it can be determined that the output signal needs to be output in advance based on the advance period, so that the phase of the output signal is aligned with the phase of the input signal, and phase locking is realized.

[0078] Step S330, in a case where it is determined based on the time delay relationship that the time delay of the output signal is less than the time delay of the input signal, determining a delay period of the output signal based on the phase difference;

[0079] Step S340, outputting the output signal based on the delay period, aligning the phase of the output signal with the phase of the input signal, and realizing phase locking.

[0080] In the implementation process, when it is determined that the time delay of the output signal is less than the time delay of the input signal, it can be determined that the output signal needs to be output in delay based on the delay period, so that the phase of the output signal is aligned with the phase of the input signal, and phase locking is realized.

[0081] In the embodiment of the application, first, the advance period or the delay period of the output signal is determined based on the phase difference, and then the phase of the output signal is aligned with the phase of the input signal based on the advance period or the delay period, and phase locking is realized.

[0082] Figure 4 A phase locking method provided in the embodiment of the application, as shown in Figure 4 includes the following steps:

[0083] Step S410, obtaining a phase difference between an input signal and a feedback signal of the digital phase-locked loop;

[0084] Step S420, in a case where it is determined that the phase difference is greater than a phase difference threshold, adjusting a phase value of the feedback signal based on the phase difference, so as to reduce the phase difference between the input signal and the feedback signal;

[0085] Step S430, compensating an output signal of the digital phase-locked loop based on the phase difference, so as to realize phase locking;

[0086] Step S440, in a case where it is determined that the phase difference is less than the phase difference threshold, determining a first adjustment voltage based on the phase difference;

[0087] In the implementation process, the user can adjust the phase difference threshold based on actual use requirements, and in the case where it is determined that the phase difference is less than the phase difference threshold, the first adjustment voltage can be determined based on the phase difference.

[0088] Step S450, filtering out the high-frequency component of the first adjustment voltage to obtain a second adjustment voltage.

[0089] In the implementation process, as shown in the figure, the loop filter 12 of the digital phase-locked loop can filter out the high-frequency component of the first adjustment voltage to obtain the second adjustment voltage. Figure 1

[0090] Step S460, adjusting the output signal based on the second adjustment voltage to achieve phase locking.

[0091] In the implementation process, as shown in the figure, the digital control oscillator 13 of the digital phase-locked loop can obtain the second adjustment voltage based on the loop filter 12, and then adjust the output signal based on the second adjustment voltage to achieve phase locking. Figure 1

[0092] The digital control oscillator 13 can also adjust the feedback signal based on the second adjustment voltage to achieve phase alignment of the feedback signal and the input signal.

[0093] In the embodiments of the present application, in the case where it is determined that the phase difference is less than the phase difference threshold, the first adjustment voltage is determined based on the phase difference; the high-frequency component of the first adjustment voltage is filtered out to obtain the second adjustment voltage; and the output signal is adjusted based on the second adjustment voltage to achieve phase locking. In this way, in the case where the phase difference is small, the second adjustment voltage for adjusting the phase of the output signal can be used to achieve phase alignment of the output signal and the input signal.

[0094] Based on the foregoing embodiments, the embodiments of the present application provide a phase locking device, which includes various modules, each module includes various sub-modules, each sub-module includes units, and can be implemented by a processor in an electronic device; of course, it can also be implemented by a specific logic circuit; in the implementation process, the processor can be a central processing unit (CPU), a microprocessor unit (MPU), a digital signal processor (DSP), or a field programmable gate array (FPGA).

[0095] Figure 5 The composition structure diagram of the phase locking device provided by the embodiments of the present application is shown in the figure. Figure 5 The device 500 includes: ​​

[0096] The first obtaining module 510 is configured to obtain a phase difference between an input signal and a feedback signal of the digital phase-locked loop.

[0097] The first adjusting module 520 is configured to, in a case where the phase difference is greater than a phase difference threshold, adjust a phase value of the feedback signal based on the phase difference, so as to reduce the phase difference between the input signal and the feedback signal.

[0098] The compensation module 530 is configured to compensate an output signal of the digital phase-locked loop based on the phase difference, so as to achieve phase locking.

[0099] In some embodiments, the first adjusting module 520 is further configured to, in a case where the phase difference is greater than a phase difference threshold, store the phase difference in a first register of the digital phase-locked loop, so as to compensate the phase difference between the input signal and the feedback signal, wherein the first register provides a phase register service for the feedback signal.

[0100] In some embodiments, the compensation module 530 is further configured to store the phase difference in a second register of the digital phase-locked loop, so as to compensate the output signal, align the phase of the output signal with the phase of the input signal, and achieve phase locking, wherein the second register provides a phase register service for the output signal.

[0101] In some embodiments, the compensation module 530 includes a determination sub-module and an alignment sub-module, wherein the determination sub-module is configured to determine a time delay relationship between a time delay of the output signal and a time delay of the input signal based on the phase difference; and the alignment sub-module is configured to align the phase of the output signal with the phase of the input signal based on the time delay relationship, so as to achieve phase locking.

[0102] In some embodiments, the alignment sub-module includes a first determination unit, a first alignment unit, a second determination unit, and a second alignment unit, wherein the first determination unit is configured to, in a case where the time delay of the output signal is greater than the time delay of the input signal based on the time delay relationship, determine an advance period of the output signal based on the phase difference; the first alignment unit is configured to output the output signal based on the advance period, align the phase of the output signal with the phase of the input signal, and achieve phase locking; the second determination unit is configured to, in a case where the time delay of the output signal is less than the time delay of the input signal based on the time delay relationship, determine a delay period of the output signal based on the phase difference; and the second alignment unit is configured to output the output signal based on the delay period, align the phase of the output signal with the phase of the input signal, and achieve phase locking.

[0103] In some embodiments, the apparatus further comprises a determining module, a filtering module and a second adjusting module, wherein the determining module is configured to determine a first adjusting voltage based on the phase difference when the phase difference is less than the phase difference threshold; the filtering module is configured to filter out high frequency components of the first adjusting voltage to obtain a second adjusting voltage; and the second adjusting module is configured to adjust the output signal based on the second adjusting voltage to achieve phase locking.

[0104] The above description of the apparatus embodiments is similar to the description of the above method embodiments, and has similar beneficial effects as the method embodiments. For technical details not disclosed in the apparatus embodiments of the present application, please refer to the description of the method embodiments of the present application for understanding.

[0105] It should be noted that, in the embodiments of the present application, if the above method is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the embodiments of the present application can be embodied in the form of a software product, and the computer software product is stored in a storage medium, and includes several instructions for causing an electronic device (which can be a mobile phone, a tablet computer, a notebook computer, a desktop computer, etc.) to execute all or part of the methods described in the embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a magnetic disk or an optical disk, and various storage media that can store program codes. Thus, the embodiments of the present application are not limited to any specific hardware and software combination.

[0106] Correspondingly, the embodiments of the present application provide a storage medium having a computer program stored thereon, and the computer program is executed by a processor to implement the steps of the phase locking method provided in the above embodiments.

[0107] Correspondingly, the embodiments of the present application provide an electronic device, Figure 6 A hardware entity schematic diagram of the electronic device provided in the embodiments of the present application is shown in FIG. 6, which includes a memory 601 and a processor 602, the memory 601 stores a computer program executable on the processor 602, and the processor 602 implements the steps of the phase locking method provided in the above embodiments when executing the program. Figure 6

[0108] ​The memory 601 is configured to store instructions and applications executable by the processor 602, and can also cache data (for example, image data, audio data, voice communication data, and video communication data) to be processed by the processor 602 and modules in the electronic device 600, and can be implemented by FLASH or random access memory (RAM).

[0109] It should be noted that the above description of the storage medium and device embodiments is similar to the description of the above method embodiments, and has similar beneficial effects as the method embodiments. For technical details not disclosed in the storage medium and device embodiments of the present application, please refer to the description of the method embodiments of the present application for understanding.

[0110] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the sequence number of each process does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above sequence number of the embodiments of the present application is only for description, not representing the advantages and disadvantages of the embodiments.

[0111] It should be noted that in this document, the term "comprising" or "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0112] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other manners. The above described device embodiments are merely exemplary. For example, the division of the units is only a logical function division. There can be another division manner for the actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed coupling, or direct coupling or communication connection between the components can be indirect coupling or communication connection through some interfaces, devices, or units, and can be electrical, mechanical, or in other forms.

[0113] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units; they can be located in one place, or distributed on multiple network units; and some or all of the units can be selected according to actual needs to achieve the purpose of the embodiments.

[0114] In addition, each functional unit in each embodiment of the present application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be realized in the form of hardware or in the form of hardware plus software functional units.

[0115] Those of ordinary skill in the art can understand that all or part of the steps of the above-mentioned method embodiments can be completed by a program instructing related hardware, and the aforementioned program can be stored in a computer readable storage medium, and when the program is executed, the steps of the method embodiments are executed; and the aforementioned storage medium includes mobile storage devices, read only memory (ROM), magnetic discs or optical discs, and various storage media that can store program codes.

[0116] Alternatively, the integrated units of the present application, if implemented in the form of software functional modules and sold or used as independent products, can also be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the embodiments of the present application can be embodied in the form of a software product, and the computer software product is stored in a storage medium, and includes several instructions for causing an electronic device (which can be a mobile phone, a tablet computer, a notebook computer, a desktop computer, etc.) to execute all or part of the methods described in the embodiments of the present application. The aforementioned storage medium includes mobile storage devices, ROM, magnetic discs or optical discs, and various storage media that can store program codes.

[0117] The methods disclosed in the several method embodiments provided by the present application can be combined arbitrarily without conflict to obtain new method embodiments.

[0118] The features disclosed in the several product embodiments provided by the present application can be combined arbitrarily without conflict to obtain new product embodiments.

[0119] The features disclosed in the several method or device embodiments provided by the present application can be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

[0120] The above merely provides a method for implementing the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A phase locking method characterized by, The method comprises: acquiring a phase difference between an input signal and a feedback signal of a digital phase-locked loop; in a case where it is determined that the phase difference is greater than a phase difference threshold, adjusting a phase value of the feedback signal based on the phase difference to reduce the phase difference between the input signal and the feedback signal; determining a time delay relationship between a time delay of an output signal of the digital phase-locked loop and a time delay of the input signal based on the phase difference; aligning a phase of the output signal with a phase of the input signal based on the time delay relationship to achieve phase locking.

2. The method of claim 1, wherein the adjusting, in a case where it is determined that the phase difference is greater than a phase difference threshold, a phase value of a feedback signal of the digital phase-locked loop based on the phase difference to reduce a phase difference between an input signal and the feedback signal of the digital phase-locked loop comprises: in a case where it is determined that the phase difference is greater than a phase difference threshold, storing the phase difference in a first register of the digital phase-locked loop to adjust the phase value of the feedback signal of the digital phase-locked loop based on the phase difference, wherein the first register provides phase register service for the feedback signal.

3. The method of claim 1, wherein the aligning, based on the time delay relationship, a phase of the output signal with a phase of the input signal to achieve phase locking comprises: storing the phase difference in a second register of the digital phase-locked loop to align the phase of the output signal with the phase of the input signal based on the time delay relationship determined based on the phase difference to achieve phase locking, wherein the second register provides phase register service for the output signal.

4. The method of claim 1, wherein the aligning, based on the time delay relationship, a phase of the output signal with a phase of the input signal to achieve phase locking comprises: in a case where it is determined that a time delay of the output signal is greater than a time delay of the input signal based on the time delay relationship, determining an advance period of the output signal based on the phase difference; outputting the output signal based on the advance period to align the phase of the output signal with the phase of the input signal to achieve phase locking; in a case where it is determined that a time delay of the output signal is less than a time delay of the input signal based on the time delay relationship, determining a delay period of the output signal based on the phase difference; outputting the output signal based on the delay period to align the phase of the output signal with the phase of the input signal to achieve phase locking.

5. The method of any one of claims 1 to 4, further comprising: in a case where it is determined that the phase difference is less than the phase difference threshold, determining a first adjustment voltage based on the phase difference; filtering out high-frequency components of the first adjustment voltage to obtain a second adjustment voltage; adjusting the output signal based on the second adjustment voltage to achieve phase locking.

6. A digital phase-locked loop, comprising: a phase discriminator configured to acquire a phase difference between an input signal and a feedback signal of the digital phase-locked loop; a processor configured to, in a case where it is determined that the phase difference is greater than a phase difference threshold, adjust a phase value of the feedback signal based on the phase difference to reduce the phase difference between the input signal and the feedback signal. determine a time delay relationship between a time delay of an output signal of the digital phase-locked loop and a time delay of the input signal based on the phase difference; align a phase of the output signal with a phase of the input signal based on the time delay relationship to achieve phase locking.

7. The digital phase-locked loop of claim 6, further comprising: a first register configured to provide phase register service for the feedback signal; the processor is further configured to register the phase difference to the first register if the phase difference is greater than a phase difference threshold; a second register configured to provide phase register service for the output signal; the processor is further configured to register the phase difference to the second register if the phase difference is greater than a phase difference threshold.

8. A phase locking apparatus, the apparatus comprising: an obtaining module configured to obtain a phase difference between an input signal and a feedback signal of a digital phase-locked loop; a first adjusting module configured to adjust a phase value of the feedback signal based on the phase difference to reduce the phase difference between the input signal and the feedback signal if the phase difference is greater than a phase difference threshold; a compensating module configured to determine a time delay relationship between a time delay of an output signal of the digital phase-locked loop and a time delay of the input signal based on the phase difference; align a phase of the output signal with a phase of the input signal based on the time delay relationship to achieve phase locking.

9. An electronic device, comprising a memory and a processor, the memory storing a computer program capable of running on the processor, the processor implementing steps in the method of any one of claims 1 to 6 when executing the program.

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