Analog-to-digital conversion circuit, converter, control method, integrated circuit and smart device

Abstract

The application provides an analog-to-digital conversion circuit, a converter, a control method, an integrated circuit and a smart device. The analog-to-digital conversion circuit comprises: a weighting capacitor network comprising at least one first switch and a plurality of first capacitors; each first switch is used for conducting or disconnecting the connection between a part of the first capacitors and another part of the first capacitors; each first capacitor is used for storing electric charges, so that an analog voltage is output at an output end of the weighting capacitor network according to the electric charges stored in each first capacitor; a switch network is used for controlling the polarity of the electric charges stored in each first capacitor according to a digital control signal, so as to control the analog voltage output at the output end of the weighting capacitor network; and a comparator is connected to the output end of the weighting capacitor network. The analog-to-digital converter provided by one or more technical solutions in the embodiments of the application can realize variable resolution and conversion rate, and has the technical effects of simple structure, without consuming more area and power consumption.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to analog-to-digital conversion circuits, converters, control methods, integrated circuits, and smart devices. Background Technology

[0002] Currently, common SARADCs (Approximation Register Analog Digital Converters) typically incorporate a capacitor-based digital-to-analog converter (DAC). The advantages of a capacitor-based DAC are: 1. The accuracy of the output voltage depends only on the ratio of the capacitances of the individual capacitors, and not on their individual capacitances; 2. The stable output voltage is unaffected by the internal resistance of the switch and the reference voltage source, thus reducing the requirements for the switching circuit and the reference voltage source; 3. The capacitor network does not consume power in steady state.

[0003] The disadvantage of using a capacitor-based DAC in an ADC is that when high output accuracy is required, the DAC needs to have a higher bit depth, which requires more capacitors. However, more capacitors will result in a lower ADC conversion rate. Summary of the Invention

[0004] In view of this, embodiments of this application provide analog-to-digital conversion circuits, converters, control methods, integrated circuits, and smart devices to solve the problem that ADCs cannot simultaneously achieve high accuracy and conversion speed.

[0005] According to one aspect of this application, an analog-to-digital converter circuit is provided, comprising: a weighted capacitor network, the weighted capacitor network including at least one first switch and a plurality of first capacitors; each first switch being used to turn on or off the connection between a portion of the first capacitors and another portion of the first capacitors; each first capacitor being used to store charge so that the output terminal of the weighted capacitor network outputs an analog voltage according to the charge stored in each first capacitor; a switch network being used to control the polarity of the charge stored in each first capacitor according to a digital control signal so as to control the analog voltage output from the output terminal of the weighted capacitor network; and a comparator connected to the output terminal of the weighted capacitor network.

[0006] In some implementations, the first terminal of the first switch is connected to the first plate of all the first capacitors in the first set, and the second terminal of the first switch is connected to the first plate of all the first capacitors in the second set; the capacitance value of any one of the first capacitors in the first set is less than the capacitance value of any one of the first capacitors in the second set; and the first plates of all the first capacitors in the first set are connected to the output terminal.

[0007] In some implementations, the switch network includes a plurality of second switches; all the second switches in the switch network correspond one-to-one with all the first capacitors, and each second switch is connected to the second plate of a corresponding first capacitor.

[0008] In some implementations, the analog-to-digital conversion circuit further includes a third switch, one end of which is used to connect to a common-mode voltage, and the other end of which is connected to the output terminal.

[0009] In some implementations, one end of the fourth switch is used to connect to the common-mode voltage or input voltage, and the other end of the fourth switch is connected to the input of the comparator.

[0010] According to another aspect of this application, a converter is provided, comprising the analog-to-digital conversion circuit of any of the above-described embodiments and a logic control circuit, wherein the logic control circuit is used to control the on / off state of all switches in the analog-to-digital conversion circuit.

[0011] In some implementations, the converter includes a successive approximation analog-to-digital converter, or a pipelined-successive approximation hybrid analog-to-digital converter, or an incremental-successive approximation hybrid analog-to-digital converter, or a Σ-Δ-successive approximation hybrid analog-to-digital converter.

[0012] According to another aspect of this application, a control method for a converter is provided. The converter includes a weighted capacitor network, a switching network, and a comparator. The weighted capacitor network includes at least one first switch and a plurality of first capacitors. Each first switch is used to turn on or off the connection between a portion of the first capacitors and another portion of the first capacitors. Each first capacitor is used to store charge, so that the output terminal of the weighted capacitor network outputs an analog voltage according to the charge stored in each first capacitor. The switching network is used to control the polarity of the charge stored in each first capacitor according to a digital control signal, so as to control the analog voltage output by the output terminal of the weighted capacitor network. A comparator is connected to the output terminal of the weighted capacitor network. The method includes:

[0013] At least one first switch in the control capacitor network is open, or all first switches are closed.

[0014] A control switch network is used to control the polarity of the charge stored in each first capacitor, thereby controlling the analog voltage output at the output terminal of the weighted capacitor network.

[0015] According to another aspect of this application, an integrated circuit is provided, including any of the above-described analog-to-digital conversion circuits or any of the above-described converters.

[0016] According to another aspect of this application, a smart device is provided, comprising any of the aforementioned integrated circuits.

[0017] One or more technical solutions provided in the embodiments of this application can achieve variable resolution and conversion rate, and have a simple structure without consuming more area and power consumption. Attached Figure Description

[0018] Further details, features, and advantages of this application are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0019] Figure 1 A block diagram of an analog-to-digital converter circuit according to an exemplary embodiment of this application is shown;

[0020] Figure 2 A block diagram of another analog-to-digital converter circuit according to an exemplary embodiment of this application is shown;

[0021] Figure 3 A block diagram of yet another analog-to-digital converter circuit according to an exemplary embodiment of this application is shown;

[0022] Figure 4 A block diagram of yet another analog-to-digital converter circuit according to an exemplary embodiment of this application is shown;

[0023] Figure 5 A block diagram of yet another analog-to-digital converter circuit according to an exemplary embodiment of this application is shown;

[0024] Figure 6 A block diagram of a SAR ADC according to an exemplary embodiment of this application is shown;

[0025] Figure 7 A schematic flowchart of a method for converting a voltage under test into a digital quantity using a SAR ADC successive approximation according to an exemplary embodiment of this application is shown.

[0026] Figure 8 A block diagram of a single-ended SAR ADC according to an exemplary embodiment of this application is shown;

[0027] Figure 9 A differential SAR ADC structure diagram according to an exemplary embodiment of this application is shown;

[0028] Figure 10 A flowchart of a control method for a converter according to an exemplary embodiment of this application is shown. Detailed Implementation

[0029] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While some embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this application. It should be understood that the drawings and embodiments of this application are for illustrative purposes only and are not intended to limit the scope of protection of this application.

[0030] It should be understood that the steps described in the method embodiments of this application may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this application is not limited in this respect.

[0031] The term "comprising" and its variations as used herein are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the following description. It should be noted that the concepts of "first", "second", etc., mentioned in this application are used only to distinguish different devices, modules, or units, and are not intended to limit the order of functions performed by these devices, modules, or units or their interdependencies.

[0032] It should be noted that the terms "a" and "a plurality of" used in this application are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0033] The names of the messages or information exchanged between multiple devices in the embodiments of this application are for illustrative purposes only and are not intended to limit the scope of these messages or information.

[0034] The following description of the scheme of this application is with reference to the accompanying drawings:

[0035] Figure 1A block diagram of an analog-to-digital converter circuit according to an exemplary embodiment of this application is shown. The circuit includes a weighted capacitor network 10, a switch network 20, and a comparator 30. The weighted capacitor network 10 includes at least one first switch 11 and a plurality of first capacitors 12; each first switch 11 is used to turn on or off the connection between a portion of the first capacitors 12 and another portion of the first capacitors 12; each first capacitor 12 is used to store charge so that the output terminal 13 of the weighted capacitor network 10 outputs an analog voltage according to the charge stored in each first capacitor 12; the switch network 20 is used to control the polarity of the charge stored in each first capacitor 12 according to a digital control signal to control the analog voltage output from the output terminal 13 of the weighted capacitor network 10; and the comparator 30 is connected to the output terminal of the weighted capacitor network.

[0036] The analog-to-digital converter (ADC) circuit of this application includes a weighted capacitor network 10 comprising multiple first capacitors 12. Each capacitor in the weighted capacitor network 10 corresponds to 1 bit of precision. The more capacitors in the weighted capacitor network 10, the higher the precision of the ADC circuit. For example, the weighted capacitor network 10 of an 8-bit precision ADC circuit includes 8 capacitors. Different capacitors correspond to different bits, and the capacitance value of the capacitor at the higher bit is twice the capacitance value of the capacitor at the lower bit. To achieve higher precision, the capacitance values ​​are exponentially amplified. For example, in a 14-bit precision ADC circuit, the capacitance value of the capacitor corresponding to the highest bit is twice the capacitance value of the lowest bit. 13 In practical applications, the analog-to-digital conversion circuit may also include redundant capacitors. The capacitance value of the redundant capacitors may be equal to the capacitance value of the lowest-order capacitor or equal to the capacitance values ​​of other lower-order capacitors. This application does not limit whether to provide redundant capacitors or the capacitance value of the redundant capacitors.

[0037] Switching network 20 controls the charge stored in each capacitor of the weighted capacitor network 10. When a capacitor is connected to a reference power supply, it can be charged, storing a charge corresponding to its capacitance value. The voltage output of the weighted capacitor network 10 is related to the charge stored in all the capacitors. Therefore, an external control signal can control the opening and closing of the switches in the switching network 20 to control the analog voltage output of the weighted capacitor network 10, which is the analog voltage output by the entire analog-to-digital converter circuit.

[0038] In practical applications, the conversion speed of the analog-to-digital converter (ADC) is related to the total capacitance value of the weighted capacitor network 10. Therefore, controlling the number of capacitors used for conversion can change the conversion speed of the ADC. In this application, a first switch 11 is used to control whether some capacitors are used for conversion. For example, the weighted capacitor network 10 includes 14 capacitors (weighted capacitors). The first switch 11 can switch the number of capacitors used for conversion between 8 and 14, thereby controlling the accuracy of the ADC between 8 bits and 14 bits. Thus, the required conversion accuracy and conversion speed can be flexibly selected as needed.

[0039] Optionally, there can be one or more first switches 11. When there are multiple first switches 11, there can be more options for accuracy and switching speed, enabling more flexible control over accuracy and voltage switching speed.

[0040] Figure 2 A block diagram of another analog-to-digital converter circuit according to an exemplary embodiment of this application is shown. In one embodiment, the capacitors in the weighted capacitor network 10 are divided into two parts. The first plates of the capacitors 121 in the first part are all connected to node a, and the first plate of the capacitors 122 in the second part is connected to node b. A first switch 11 is located between node a and node b. Node a is connected to the output terminal 13 of the weighted capacitor network 10. When higher accuracy is not required, the first switch 11 can be opened to improve the conversion speed; in this case, only the capacitors 121 in the first part are used for conversion. When higher accuracy is required, the first switch 11 can be closed; in this case, both the capacitors 121 and 122 in the first part are used for conversion. The capacitors in the first part 121 can be higher-order capacitors, and the capacitors in the second part 122 can be lower-order capacitors. The first plate can be either the upper plate or the lower plate; this application does not limit this.

[0041] Figure 3 A block diagram of another analog-to-digital converter circuit according to an exemplary embodiment of this application is shown. In one embodiment, the capacitors in the weighted capacitor network 10 are divided into three parts. The first plates of the capacitors 121 in the first part are all connected to node a, and node a is connected to the output terminal 13 of the weighted capacitor network 10. The first plates of the capacitors 122 in the second part are connected to node b. The first plates of the capacitors 123 in the third part are all connected to node c. A first switch 11(a) is located between node a and node b, and another first switch 11(b) is located between node b and node c. Node a is connected to the output terminal 13. When lower accuracy is required, to improve the conversion speed, the first switch 11(a) can be opened, and only the capacitors in the first part are used for conversion. When medium accuracy is required, the other first switch 11(b) can be opened, and the first switch 11(a) can be closed, and the capacitors in the first, second, and third parts are all used for conversion. When higher accuracy is required, one first switch 11(a) and the other first switch 11(b) can be closed, and the capacitors in the first, second, and third parts are all used for conversion.

[0042] In this embodiment, the weighted capacitor network 10 of the analog-to-digital converter circuit can be divided into at least two parts. When high accuracy of the output voltage is required, all capacitors in the first switch are used to ensure output accuracy. When high voltage conversion speed is required, only a portion of the capacitors are used to ensure high voltage conversion speed. Therefore, the switching via the first switch enables the analog-to-digital converter circuit to achieve both high accuracy and high conversion speed.

[0043] In some embodiments, the first terminal of the first switch 11 is connected to the first plate of all the first capacitors 12 in the first set, and the second terminal of the first switch 11 is connected to the first plate of all the first capacitors 12 in the second set; the capacitance of any one of the first capacitors 12 in the first set is less than the capacitance of any one of the first capacitors 12 in the second set; and the first plates of all the first capacitors 12 in the first set are connected to the output terminal 13.

[0044] In practical applications, each first capacitor 12 corresponds to a different weight (i.e., precision). All first capacitors 12 are arranged in order of their weights, and can be divided into two sets: a first set and a second set. The capacitors in the first set have smaller capacitance values, while all capacitors in the second set have larger capacitance values. A first switch controls whether the first plates of all capacitors in the second set are connected to the first plates of all capacitors in the first set. When connected, the capacitance value of the full-capacitor network of the analog-to-digital converter circuit is larger, the speed is slower, and the precision is higher; when disconnected, the speed is faster, and the precision is lower.

[0045] As some embodiments, the switch network 20 also includes a plurality of second switches, all of which are connected in a one-to-one correspondence with all the first capacitors 12, and each second switch is connected to the second plate of a corresponding first capacitor 12. The second plate is the opposite plate to the first plate. For example, if the first plate is the upper plate, then the second plate is the lower plate; if the first plate is the lower plate, then the second plate is the upper plate.

[0046] Figure 4 A block diagram of another analog-to-digital converter circuit according to an exemplary embodiment of the present application is shown. As some embodiments, it also includes a third switch 40, one end of which is used to connect to a common-mode voltage, and the other end of which is connected to the output terminal 13 of the weighted capacitor network 10, that is, to the input terminal of the comparator 30.

[0047] As an example, taking a weighted capacitor network 10 including a first switch 11 as an example, the first switch 11 divides the weighted capacitor network 10 into two parts. The first plates of all capacitors in the first part are connected to the output terminal 13 of the weighted capacitor network 10, and the first plates of all capacitors in the second part are connected to the first plates of all capacitors in the first part through the first switch 11. When the first switch 11 is closed and the third switch 40 is closed, the output terminal 13 of the weighted capacitor network 10 is connected to a common-mode voltage, and the first plates of all capacitors in the weighted capacitor network 10 are connected to a common-mode voltage; when the first switch 11 is open and the third switch 40 is closed, the output terminal 13 of the weighted capacitor network 10 is connected to a common-mode voltage, that is, the first plates of all capacitors in the first part are connected to a common-mode voltage.

[0048] Figure 5 A block diagram of another analog-to-digital converter circuit according to an exemplary embodiment of this application is shown. As some embodiments, it further includes a fourth switch 50; one end of the fourth switch 50 is used to connect to a common-mode voltage, and the other end of the fourth switch 50 is connected to a predetermined node. The predetermined node is connected to the output terminal 13 of the weighted capacitor network 10 when all first switches 11 are closed, and disconnected from the output terminal 13 of the weighted capacitor network 10 when any one of the first switches 11 is open. The fourth switch 50 is used to reset the first capacitors 12 connected to the predetermined node using a common-mode voltage when it is on. For example, when the fourth switch 50 and all first switches 11 are on, all first capacitors 12 are connected to the predetermined node, and all first capacitors 12 can be reset. When any one of the first switches 11 is open, only a portion of the first capacitors 12 are connected to the predetermined node, and the fourth switch 50 only resets the portion of the first capacitors 12 connected to the predetermined node.

[0049] As one embodiment, the weighted capacitor network 10, as described above, includes a first switch 11. When the first switch 11 is open, the capacitance of the first portion (e.g., Figure 5 The capacitor to the right of the first switch 11 can be reset by the common-mode voltage introduced by the third switch 40, but the capacitor in the second part (e.g.) Figure 5 The capacitor to the left of the first switch 11 cannot be reset by the common-mode voltage introduced by the third switch 40. At this time, the capacitors in the second part can be reset by the common-mode voltage introduced by the fourth switch 50. Thus, when the first switch 11 is open, all the first capacitors can be reset by the third switch 40 and the fourth switch 50.

[0050] According to another aspect of this application, a converter is provided, comprising the analog-to-digital conversion circuit of any of the above-described embodiments and a logic control circuit, wherein the logic control circuit is used to control the on / off state of all switches in the analog-to-digital conversion circuit.

[0051] As some embodiments, the converter includes, but is not limited to, a successive approximation analog-to-digital converter, or a pipelined-successive approximation hybrid analog-to-digital converter, or an incremental-successive approximation hybrid analog-to-digital converter, or a Σ-Δ-successive approximation hybrid analog-to-digital converter.

[0052] As one example, Figure 6 A block diagram of a SAR ADC according to an exemplary embodiment of this application is shown, mainly including the analog-to-digital conversion circuit and logic control circuit of this application. The analog-to-digital conversion circuit includes a DAC circuit (including a weighted capacitor network 10 and a switch network 20) ​​and a CMP (Comparator 30). Vin is the voltage to be measured, Vref is the reference voltage, SW is the reset switch, Vcm is the common-mode voltage, and Vdac is the analog voltage output by the analog-to-digital conversion circuit.

[0053] As some embodiments, the comparator is used to compare the analog signal output by the weighted capacitor network 10 of the analog-to-digital converter circuit with the voltage to be measured to obtain a first comparison result; the first comparison result is sent to an external controller so that the external controller controls the analog-to-digital converter circuit according to the first comparison result.

[0054] As one example, Figure 7 This illustration shows a flowchart of a method for converting a voltage to be measured into a digital quantity using a SAR ADC successive approximation according to an exemplary embodiment of this application. The method includes:

[0055] Step 701: Configure the current quantization bit as the most significant bit of the voltage data; the current quantization bit is one bit of the voltage data.

[0056] Step 702: Determine whether the common-mode voltage is greater than the analog voltage (i.e., obtain the first comparison result): If yes, proceed to step 703; otherwise, proceed to step 704.

[0057] Step 703: Configure the value of the current quantization bit to 1, then jump to step 705;

[0058] Step 704: Configure the value of the current quantization bit to 0, then proceed to step 705;

[0059] Step 705: Determine whether the least significant bit of the voltage data has been quantized (i.e., determine whether successive approximation has been completed): If yes, proceed to step 706; otherwise, proceed to step 707.

[0060] Step 706: Determine the voltage data as the conversion result;

[0061] Step 707: Update the analog voltage output by the DAC based on the current quantization bit value;

[0062] Step 708: Decrease the current quantization bit by 1 bit, then jump to step 702.

[0063] As an example, Figure 8 A block diagram of a single-ended SAR ADC according to an exemplary embodiment of this application is shown. SW1 is a first switch 11, used to turn on or off the connection between the first capacitor 12 (CL1-CL1) of one part and the first capacitor 12 (CM1-CMj) of another part in the analog-to-digital conversion circuit. V1-V3 are common-mode voltages, and the voltage to be measured can be input from the switch network 20. SW3 is a third switch, and SW5 is a fourth switch.

[0064] As some embodiments, the comparator is used to compare the analog signals output by two analog-to-digital converter circuits to obtain a second comparison result; the second comparison result is sent to an external controller so that the external controller controls the two analog-to-digital converter circuits according to the second comparison result.

[0065] As an example, Figure 9 A differential SAR ADC structure diagram according to an exemplary embodiment of this application is shown. CM1-CMj is a portion of the first capacitor 12; CL1-CLi is another portion of the first capacitor 12. Switches SW1 / 2 (i.e., the first switch 11) and SW5 / 6 (i.e., the fourth switch) can be double-pole single-throw switches. V1-V4 are the common-mode voltage Vcm, and the voltage to be measured by the ADC is Vin. When high resolution is required, SW1 / 2 is turned on and SW5 / 6 is turned off. The effective capacitors of the DAC are CMi-CMj and CL1-CLi, with more and larger effective capacitors used for voltage conversion. When a high conversion rate is required, SW1 / 2 is turned off and SW5 / 6 is turned on. The effective capacitors of the DAC used for voltage conversion are CL1-i, with fewer and smaller effective capacitors.

[0066] As one embodiment, all converters in this application can be sampled by the first plate or by the second plate.

[0067] Figure 10 A flowchart illustrating a control method for a converter according to an exemplary embodiment of this application is shown. The converter includes a weighted capacitor network, a switching network, and a comparator. The weighted capacitor network includes at least one first switch and a plurality of first capacitors. Each first switch is used to turn on or off the connection between a portion of the first capacitors and another portion of the first capacitors. Each first capacitor is used to store charge so that the output terminal of the weighted capacitor network outputs an analog voltage according to the charge stored in each first capacitor. The switching network is used to control the polarity of the charge stored in each first capacitor according to a digital control signal to control the analog voltage output by the output terminal of the weighted capacitor network. A comparator is connected to the output terminal of the weighted capacitor network. The method includes the following steps:

[0068] Step 1001: Control at least one first switch in the control capacitor network to open, or control all first switches to close;

[0069] Step 1002: Control the switching network to control the polarity of the charge stored in each first capacitor, so as to control the analog voltage output at the output terminal of the weighted capacitor network.

[0070] In some embodiments, the converter further includes a third switch through which the common-mode voltage is connected to the output; wherein, after at least one first switch in the control weight capacitor network is opened, or after all first switches are closed, the converter further includes:

[0071] Controls the third switch to be turned on or off.

[0072] In some implementations, the converter further includes a fourth switch; the common-mode voltage is connected to a predetermined node via the fourth switch; the predetermined node is connected to the output when all the first switches are closed, and disconnected from the output when any one of the first switches is open;

[0073] Wherein, after at least one first switch in the control capacitor network is opened, or after all first switches are closed, the system further includes:

[0074] Controls the fourth switch to be turned on or off.

[0075] According to another aspect of this application, an integrated circuit is provided, comprising the analog-to-digital converter circuit or the converter of any of the above claims.

[0076] According to another aspect of this application, a smart device is provided, comprising the converter of any of the above claims.

[0077] One or more technical solutions provided in the embodiments of this application can divide the weighted capacitor network 10 of the capacitor DAC into two parts. When the accuracy requirement of the output voltage is high, both parts of the capacitor are used to ensure the output accuracy. When the accuracy requirement of the output voltage is not high, one part of the capacitor is used to ensure a higher voltage conversion speed. This achieves the technical effect of outputting both high-precision voltage and fast voltage output.

[0078] The analog-to-digital conversion circuit, converter, control method, integrated circuit, and intelligent device provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the circuits and methods of this application and their core ideas. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An analog-to-digital conversion circuit, characterized by, comprises at least one first switch and a plurality of first capacitors; each of the first switches is used to turn on or turn off the connection between a part of the first capacitors and another part of the first capacitors; each of the first capacitors is used to store electric charge, so that the output terminal of the weight capacitor network outputs an analog voltage according to the electric charge stored in each of the first capacitors; a switch network is used to control the polarity of the electric charge stored in each of the first capacitors according to a digital control signal, so as to control the analog voltage output by the output terminal of the weight capacitor network; a comparator connected to the output terminal of the weight capacitor network; a third switch, one end of the third switch is used to access a common-mode voltage, and the other end of the third switch is connected to an input terminal of the comparator; a fourth switch, one end of the fourth switch is used to access a common-mode voltage or an input voltage, and the other end of the fourth switch is connected to a predetermined node through the first switch, wherein the predetermined node is connected to the output terminal of the weight capacitor network when all the first switches are turned on, and the predetermined node is disconnected from the output terminal of the weight capacitor network when any one of the first switches is turned off.

2. The analog-to-digital conversion circuit according to claim 1, wherein a first end of the first switch is connected to a first plate of all the first capacitors in a first set, and a second end of the first switch is connected to a first plate of all the first capacitors in a second set; the capacitance of any one of the first capacitors in the first set is smaller than the capacitance of any one of the first capacitors in the second set; the first plates of all the first capacitors in the first set are connected to the output terminal. The switch network comprises a plurality of second switches. All the second switches in the switch network correspond to all the first capacitors one by one, and each of the second switches is connected to a second plate of a corresponding one of the first capacitors.

3. The analog-to-digital conversion circuit of claim 2, wherein, The analog-to-digital conversion circuit comprises the analog-to-digital conversion circuit according to any one of claims 1-3 and a logic control circuit, and the logic control circuit is used to control the on-off of all the switches in the analog-to-digital conversion circuit. The converter is a successive approximation type analog-to-digital converter, or a pipeline-successive approximation hybrid structure analog-to-digital converter, or an incremental-successive approximation hybrid structure analog-to-digital converter, or a sigma-delta-successive approximation hybrid structure analog-to-digital converter.

4. A converter characterized by The converter comprises a weight capacitor network, a switch network and a comparator, the weight capacitor network comprises at least one first switch and a plurality of first capacitors; each of the first switches is used to turn on or turn off the connection between a part of the first capacitors and another part of the first capacitors; each of the first capacitors is used to store electric charge, so that the output terminal of the weight capacitor network outputs an analog voltage according to the electric charge stored in each of the first capacitors; the switch network is used to control the polarity of the electric charge stored in each of the first capacitors according to a digital control signal, so as to control the analog voltage output by the output terminal of the weight capacitor network; 5. The converter of claim 4, wherein, ​ 6. A control method of a converter, characterized by, ​ and the comparator, an output terminal of the weighting capacitor network is connected; a third switch, one end of the third switch is used for accessing common-mode voltage, the other end of the third switch is connected with an input terminal of the comparator; a fourth switch, one end of the fourth switch is used for accessing common-mode voltage or input voltage, the other end of the fourth switch is connected with a predetermined node through the first switch, wherein, the predetermined node is connected with the output terminal of the weighting capacitor network when all the first switches are closed, and the predetermined node is disconnected with the output terminal of the weighting capacitor network when any one of the first switches is opened; the method comprises: controlling at least one of the first switches in the weighting capacitor network to be opened, or controlling all the first switches to be closed; controlling the third switch and the fourth switch to be turned on or turned off; controlling the polarity of the charge stored in each of the first capacitors through the switch network, so as to control the analog voltage output from the output terminal of the weighting capacitor network.

7. An integrated circuit, characterized by The digital-to-analog conversion circuit of any one of claims 1-3 or the converter of any one of claims 4-5.

8. A smart device, comprising: The integrated circuit of claim 7. The integrated circuit of claim 7.

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