Compact Antenna Impedance Tuner

Abstract

A circuit (100) for impedance transformation includes a first port (P1), a second port (P2), and a tap transformer (110), wherein the tap transformer (110) includes a first winding (111) and a second winding (112). Each winding includes a first terminal, a second terminal, and a plurality of taps, wherein the plurality of taps are connected at different positions between the first terminal and the second terminal. The circuit (100) further includes: a first programmable capacitor (C1) connected in parallel with the first winding (111); a second programmable capacitor (C2) connected in parallel with the second winding (112); a first set of switches (S1) connected between the plurality of taps on the first winding (111) and the terminal of the first port (P1); and a second set of switches (S2) connected between the plurality of taps on the second winding (112) and the terminal of the second port (P2). The circuit (100) is configured to transform the impedance between the first circuit (120) and the second circuit (130) by selectively connecting a first circuit (120) connected to the first port (P1) to one of the taps on the first winding (111) via a first set of switches (S1) and selectively connecting a second circuit (130) connected to the second port (P2) to one of the taps on the second winding (112) via a second set of switches (S2).

Description

Technical Field

[0001] Embodiments herein relate to circuits for impedance transformation. In particular, they relate to an antenna impedance tuner having a tapped transformer and a programmable capacitor. Background Art

[0002] Wireless communication devices or equipment typically include an antenna, a transceiver (including a transmitter and a receiver), and a baseband processing unit. The transmitter typically up-converts the baseband signal to a radio frequency (RF) signal for transmission, while the receiver down-converts the received RF signal to a baseband signal for further processing in the baseband processing unit.

[0003] In wireless communication devices, antenna impedance can vary significantly, for example when a user holds the device or places it in different environments. Because transceivers are designed for a specific antenna impedance (e.g., 50Ω), significant deviations from this value will result in degraded performance. To counteract variations in the impedance presented to the transceiver, an antenna impedance tuner can be used. It transforms varying antenna impedances to more closely match the impedance for which the transceiver was designed, and typically consists of switches and passive components such as inductors and capacitors. The switches can be turned on and off to represent different states, where the tuner performs different impedance transformations. Depending on the level of integration, some or all components may be implemented on-chip. Lowest losses are achieved if the inductor is off-chip; in this case, the inductor can have a very high quality factor. Loss is one of the key parameters of an antenna tuner. Another important parameter is the size of the so-called matching domain—that is, the range of antenna impedances that can be transformed to values ​​close to the nominal transceiver impedance. Also important is linearity—the degree of distortion, primarily caused by the switches, and the amount of power that can be handled before signal compression and breakdown. When designing a tuner for an application, the cost and size of the implementation and the simplicity of controlling the tuner to a specific impedance are other key parameters.

[0004] While antenna impedance tuners are generally beneficial for transceivers in wireless communication devices, they are even more important in the upcoming full-duplex systems. In such systems, the transmitter and receiver operate simultaneously at the same frequency, and the receiver and transmitter are connected to the antenna via an isolator or circulator. The isolation from the transmit port to the receive port will depend on the impedance presented to the antenna port. It is important to reduce the variation in this impedance. Antenna impedance tuners can therefore improve isolation and, therefore, the performance of the full-duplex transceiver.

[0005] In "A low-band cellular antenna impedance tuner in 130nm CMOS-SOI technology" by J. Lindstrand et al. (ESSCIRC 2014, pp. 459-462), a high-performance tuner is disclosed using silicon-on-insulator (SOI) complementary metal-oxide semiconductor (CMOS) technology using off-chip inductors. While this is suitable for some applications requiring the lowest possible losses, other applications may benefit from a fully integrated design to reduce cost and physical size.

[0006] US5986617A discloses an unbalanced to balanced antenna matching unit that operates over a relatively large frequency range by utilizing multiple transformers connected in series, wherein a set of bypass switches is used to control the number of transformers that are "active" in the matching unit at any particular time. The multi-band antenna matching unit can effectively shift the operating frequency while maintaining the same transformation ratio by bypassing at least one of the multiple transformers of the matching unit.

[0007] In existing solutions, antenna impedance tuners also tend to have complex matching domain behavior that can vary significantly at different frequencies. To simplify tuner control, a more regular behavior that is more consistent with frequency may be preferable. Designs that use off-chip inductors tend to use multiple individual inductors, which translates into a larger chip area in a fully integrated design. Summary of the Invention

[0008] Embodiments herein provide a circuit for impedance transformation that is suitable for full integration and has improved flexibility, cost, size, and matching domain behavior.

[0009] To minimize chip area, a single inductor or transformer structure may be more appropriate in a fully integrated tuner.

[0010] According to one aspect of the embodiments herein, a circuit for impedance conversion is provided. The circuit includes a first port, a second port, and a tapped transformer, the tapped transformer including a first winding and a second winding. The first winding includes a first terminal, a second terminal, and a plurality of taps, the plurality of taps being connected at different locations on the first winding between the first terminal and the second terminal. The second winding includes a first terminal, a second terminal, and a plurality of taps, the plurality of taps being connected at different locations on the second winding between the first terminal and the second terminal. The circuit also includes: a first programmable capacitor connected between the first and second terminals of the first winding; and a first set of switches connected between the plurality of taps on the first winding and terminals of the first port. The circuit also includes: a second programmable capacitor connected between the first and second terminals of the second winding; and a second set of switches connected between the plurality of taps on the second winding and terminals of the second port. The circuit is configured to transform the impedance between the first circuit and the second circuit by selectively connecting a first circuit connected to the first port to one of the taps on the first winding via the first set of switches and selectively connecting a second circuit connected to the second port to one of the taps on the second winding via the second set of switches.

[0011] The circuit for impedance transformation according to the embodiments of this document can be used as an antenna impedance tuner. The core of the tuner is a tapped transformer with multiple taps on two windings. Compared to using multiple separate inductors, using a single transformer reduces chip area. By using switches to connect to different taps on both sides of the transformer, the antenna impedance can be transformed up and down. The two transformer windings are connected in parallel with programmable capacitors. If these capacitors are set to resonate with the inductance of the transformer at the operating frequency, the tuner transforms between real-valued impedances. The transformation ratio can be programmed by selecting different taps to connect to the tuner port through the switch. If a transformation from complex antenna impedance to real-valued impedance is required, the capacitor can be programmed to a value smaller or larger than the resonant value. The impedance will then move along the circle in the Smith chart, sweeping through the capacitive and inductive half-fields. Sweeping the capacitance of different tap settings will produce non-overlapping arcs that cover the area of ​​the Smith chart. This represents an unusually ordered matching domain and therefore supports simpler control of the impedance tuner.

[0012] Thus, embodiments herein provide a circuit for impedance transformation with improved flexibility, cost, size, and matching domain behavior when controlling impedance transformation. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Examples of embodiments herein are described in more detail with reference to the accompanying drawings, which are:

[0014] Figure 1 is a schematic diagram of a circuit for impedance conversion according to an embodiment of the present invention;

[0015] Figure 2 is a schematic diagram of a single-ended impedance tuner according to an embodiment of the present invention;

[0016] Figure 3 is a schematic diagram of a differential to single-ended impedance tuner according to an embodiment of the present invention;

[0017] Figure 4 is a schematic diagram of a single-ended to differential impedance tuner according to an embodiment of the present invention;

[0018] Figure 5 is a schematic diagram of a differential impedance tuner according to an embodiment of the present invention;

[0019] Figure 6 shows an example layout of a tapped transformer with a single-ended structure according to embodiments herein;

[0020] Figure 7 shows an example layout of a tapped transformer with a differential structure according to embodiments herein;

[0021] Figure 8 shows simulation results of an impedance conversion circuit according to an embodiment of the present invention; and

[0022] Figure 9 is a block diagram illustrating a wireless communication device in which an impedance conversion circuit according to embodiments herein may be implemented. DETAILED DESCRIPTION

[0023] Figure 1 FIG. 3 is a schematic diagram of a circuit 100 for impedance transformation according to an embodiment of the present invention. The impedance transformation circuit 100 includes a first port P1 and a second port P2 , and a tapped transformer 110 . The tapped transformer 110 includes a first winding 111 and a second winding 112 .

[0024] The first winding 111 includes a first terminal T11, a second terminal T12 and a plurality of taps Tp11, Tp12, Tp13, Tp14, ... connected at different positions on the first winding 111 between the first and second terminals T11, T12.

[0025] The second winding 112 includes a first terminal T21, a second terminal T22 and a plurality of taps Tp21, Tp22, Tp23, Tp24, ..., which are connected at different positions on the second winding 112 between the first terminal and the second terminal T21, T22.

[0026] The impedance conversion circuit 100 further includes a first programmable capacitor C1 connected between a first terminal of the first winding 111 and second terminals T11 and T12, and a first set of switches S1 connected to a plurality of taps on the first winding 111. The programmable capacitor C1 is connected in parallel with the first winding 111.

[0027] The impedance conversion circuit 100 further includes: a second programmable capacitor C2 connected between the first terminal and the second terminals T21 and T22 of the second winding 112; and a second set of switches S2 connected to a plurality of taps on the second winding 112. The second programmable capacitor C2 is connected in parallel with the second winding 112.

[0028] The first set of switches S1 is connected to the terminals of the first port P1 of the impedance conversion circuit 100 on a first side (e.g., the left side), and the second set of switches S2 is connected to the terminals of the second port P2 of the circuit 100 on a second side (e.g., the right side). The impedance conversion circuit 100 can be connected between two circuits and convert the impedance between the two circuits. Figure 1 As shown, the first circuit 120 can be connected to the first port P1, and the second circuit 130 can be connected to the second port P2. The impedance conversion circuit 100 is configured to convert impedance by selectively connecting the first circuit 120 to one of the taps on the first winding 110 via a first set of switches S1 and selectively connecting the second circuit 130 to one of the taps on the second winding 112 via a second set of switches S2.

[0029] It can be seen that the core of the impedance conversion circuit 100 is the tap transformer 110. The first circuit 120 can be a transceiver, and the second circuit 130 can be an antenna. Then, the circuit 100 can be used as an antenna impedance tuner. By selecting different taps on the antenna and transceiver sides, different up or down conversion ratios can be achieved. In order to select the taps, there are switches S1 and S2 on both sides. Using complementary metal oxide semiconductor (CMOS) technology, the switches S1 and S2 can be implemented by a transistor connected between each tap and the corresponding tuner terminal. In Figure 1In the example shown in FIG. 1 , there may be four transistors connected between the transceiver terminals and the taps of the first transformer winding 111, and another four transistors connected between the antenna terminals and the four taps of the second transformer winding 112. One transistor in each group of four transistors can then be turned on by applying a high potential to its gate. To improve linearity, a large resistor can be connected in series between the control voltage and the gate terminal of each transistor.

[0030] As can be seen, controllable and programmable capacitors C1 and C2 are also used, and the impedance conversion circuit 100 can also be configured to select the capacitance of the first programmable capacitor and the second programmable capacitor. The programmable capacitors C1 and C2 can be implemented as a capacitor bank with switches to select or set the different capacitances required. By setting their capacitance to resonate with the inductance of the transformer 110, the tuner converts the real-value antenna impedance into a real-value transceiver impedance. However, if the antenna exhibits a complex impedance at the operating frequency, the capacitance can be increased or decreased from the resonant value to handle inductive or capacitive antenna impedance. The antenna impedance that can be converted to the nominal transceiver impedance then moves along the circle in the Smith chart. The larger the range over which the capacitance can be controlled, the longer the arc that can be achieved. However, there is a trade-off between the capacitance tuning range and the capacitor quality factor (i.e., capacitor loss).

[0031] Other trade-offs exist in the design of transformer 110. Implementing more taps results in more losses, but fewer taps provides a lower density matching domain. A larger physical size provides better coverage of higher impedances but increases chip area. Trade-offs also exist in the design of switches, where larger switches reduce losses but also reduce the size of the matching domain.

[0032] The circuit 100 for impedance conversion can be configured and used for different applications. The first terminal T11 or the second terminal T12 of the first winding 111 can be connected to a reference voltage node, such as a signal ground, for example. The first terminal T21 or the second terminal T22 of the second winding 112 can be connected to a reference voltage node, such as a signal ground, for example.

[0033] According to some embodiments herein, the circuit for impedance transformation 100 may be configured as a single-ended impedance tuner, where both the first port and the second port are single-ended ports. Figure 2 A single-ended impedance tuner 200 is shown. Figure 2As shown, one of the terminals on the first winding 111 (e.g., the second terminal T12) and one of the terminals on the second winding 112 (e.g., the second terminal T22) are connected to the signal ground, and the tap on the first winding 111 can be connected to the transceiver TRX 220 having a single-ended port via a first group of switches S1, and the tap on the second winding 112 can be connected to the antenna 230 having a single-ended port via a second group of switches S2.

[0034] According to some embodiments herein, the circuit 100 for impedance transformation may be configured as a differential-to-single-ended impedance tuner, wherein the first port is a differential port and the second port is a single-ended port. Figure 3 1 shows a differential to single-ended impedance tuner 300. In order to form a differential port, the tap transformer 110 further includes a third winding 113 having a plurality of taps and connected in series with the first winding 111. Figure 3 As shown. The third winding 113 has a structure similar to the first winding, that is, it has a first terminal T31, a second terminal T32 and a plurality of taps, and the plurality of taps are connected at different positions on the third winding 113 between the first terminal and the second terminal. The differential-to-single-ended impedance tuner 300 also includes a third set of switches S3 and a third programmable capacitor C3 connected in parallel with the third winding 113. That is, the third programmable capacitor C3 is connected between the first terminal and the second terminal of the third winding 113. The first programmable capacitor C1 and the third programmable capacitor C3 can be combined or configured as one programmable capacitor and connected between the first terminal T11 of the first winding 111 and the first terminal T31 of the third winding 113. The taps on the first winding and the third winding are connected to the differential ports P1+ and P1- through the first switch S1 and the third switch S3, respectively.

[0035] One of the terminals on the second winding 112 (e.g., the second terminal T22) is connected to the signal ground, so that the terminals of the programmable capacitor C2 connected to the non-grounded terminal of the second winding 112 will obtain the same DC potential. The interconnection of the first and third windings (i.e., the connection of the second terminals of the first and third windings) is connected to the signal ground, so that the terminals of the first and third programmable capacitors C1 and C3 connected to the non-grounded terminals of the windings will also obtain the same DC potential.

[0036] According to some embodiments herein, the circuit 100 for impedance transformation may be configured as a single-ended to differential impedance tuner. Figure 4A single-ended to differential impedance tuner 400 is shown, in which the first port P1 is a single-ended port, and the second port P2 is a differential port P2+, P2-. To form a differential port, the tapped transformer 110 further includes a third winding 113 having multiple taps and connected in series with the second winding 112. The third winding 113 has a similar structure to the second winding 112, namely, a first terminal T31, a second terminal T32, and multiple taps connected at different locations on the third winding 113 between the first and second terminals. The single-ended to differential impedance tuner 400 further includes a third set of switches S3 and a third programmable capacitor C3 connected in parallel with the third winding 113. In other words, the third programmable capacitor C3 is connected between the first and second terminals of the third winding 113. The second and third programmable capacitors C2 and C3 can be combined or configured as a single programmable capacitor, connected between the first terminal T21 of the second winding 112 and the first terminal T31 of the third winding 113. The taps on the second winding and the third winding are connected to the differential ports P2+, P2- through the second switch and the third switch (S2, S3), respectively.

[0037] One of the terminals on the first winding 111 (e.g., the second terminal T12) is connected to signal ground, so that the terminals of the programmable capacitor C1 connected to the non-grounded terminal of the first winding 111 will obtain the same DC potential. The interconnection of the second and third windings 112 and 113 (i.e., the connection of the second terminals T22 and T32 of the second and third windings 112 and 113) is connected to signal ground, so that the terminals of the second and third programmable capacitors C2 and C3 connected to the non-grounded terminals of the windings will also obtain the same DC potential.

[0038] The circuit 100 for impedance transformation may be configured as a differential impedance tuner. Figure 5 A differential impedance tuner 500 is shown, wherein both the first port and the second port P1, P2 are differential ports P1+, P1-, P2+, P2-. Figure 5As shown, tapped transformer 110 further includes a third winding 113 having multiple taps and connected in series with first winding 111, and a fourth winding 114 having multiple taps and connected in series with second winding 112. Third winding 113 has a similar structure to first winding 111, namely, a first terminal T31, a second terminal T32, and multiple taps connected at different locations on third winding 113 between the first and second terminals. Fourth winding 114 has a similar structure to second winding 112, namely, a first terminal T41, a second terminal T42, and multiple taps connected at different locations on fourth winding 114 between the first and second terminals. Differential impedance tuner 500 further includes a third set of switches S3, a fourth set of switches S4, a third programmable capacitor C3 connected in parallel with third winding 113, and a fourth programmable capacitor C4 connected in parallel with fourth winding 114. The first programmable capacitor C1 and the third programmable capacitor C3 can be combined or configured as a single programmable capacitor and connected between the first terminal T11 of the first winding 111 and the first terminal T31 of the third winding 113. The second programmable capacitor C2 and the fourth programmable capacitor C4 can be combined or configured as a single programmable capacitor and connected between the first terminal T21 of the second winding 112 and the first terminal T41 of the fourth winding 114. Taps on the first and third windings 111 and 113 are connected to the first differential ports P1+ and P1- via the first and third switches S1 and S3, respectively. Taps on the second and fourth windings 112 and 114 are connected to the second differential ports P2+ and P2- via the second and fourth switches S2 and S4, respectively.

[0039] The interconnection of the first and third windings 111 and 113 (i.e., the connection of the second terminals T12 and T32 of the first and third windings 111 and 113) is connected to the signal ground, so that the terminals of the first and third programmable capacitors C1 and C3 connected to the non-grounded terminals of the windings will obtain the same DC potential. The interconnection of the second and fourth windings 112 and 114 (i.e., the connection of the second terminals T22 and T42 of the second and fourth windings 112 and 114) is connected to the signal ground, so that the terminals of the second and fourth programmable capacitors C2 and C4 connected to the non-grounded terminals of the windings will also obtain the same DC potential.

[0040] The above-mentioned circuit 100 for impedance transformation, single-ended impedance tuner 200, differential to single-ended impedance tuner 300, single-ended to differential impedance tuner 400 and differential impedance tuner 500 may be collectively referred to as impedance transformation circuits 100, 200, 300, 400, 500 according to the embodiments of this document below.

[0041] Figure 6 Shown with Figure 2 The illustrated example layout of a tapped transformer 600, which has a single-ended configuration similar to tapped transformer 110, includes two interleaved windings, each with two turns and five taps. The taps at the top of the layout, designated by Tap 1, Tap 2, Tap 3, Tap 4, and Tap 5, are on the first winding, while the taps at the bottom of the layout, designated by Tap 1, Tap 2, Tap 3, Tap 4, and Tap 5, are on the second winding.

[0042] Figure 7 Shown with Figure 5 The illustrated example layout of a tapped transformer 700, which, like tapped transformer 110, has a fully differential structure, includes four interleaved windings, each with three taps. The taps indicated by "Tap 1," "Tap 2," and "Tap 3" in the upper left corner of the layout are on the first winding, while the taps indicated by "Tap 1," "Tap 2," and "Tap 3" in the upper right corner of the layout are on the second winding. The taps indicated by "Tap 1," "Tap 2," and "Tap 3" in the lower left corner of the layout are on the third winding, and the taps indicated by "Tap 1," "Tap 2," and "Tap 3" in the lower right corner of the layout are on the fourth winding.

[0043] To demonstrate the performance and advantages that impedance conversion circuits 100, 200, 300, 400, 500 may achieve in a practical implementation, impedance conversion circuits 100, 200, 300, 400, 500 are simulated in a fully depleted silicon-on-insulator (FDSOI) CMOS design toolkit. The switches used in both the tap and the programmable capacitor are RF low-threshold-voltage NMOS devices. Figure 6 The layout of the tapped transformer 600 shown was modeled in the electromagnetic simulation tool Momentum and then in a circuit simulator (by Provided The impedance tuner is simulated together with the impedance tuner in the simulation platform.

[0044] A frequency of 5 GHz is chosen for the impedance tuner simulation. The matching domain is given by Figure 8The Smith chart in FIG1 is shown. As can be seen from the figure, the matching arc covers the center of the Smith chart and extends to an impedance ratio of about 4 (higher in some directions and lower in some directions). Lowering the tap position of the second winding moves the arc to the left, while increasing the capacitance moves the impedance along the arc from top to bottom. The tuner losses at different impedance levels are shown in Table 1. A symmetrical layout is used in the transformer for faster implementations, which results in less than ideal tuner loss performance because the quality factor of the resonator connected to the antenna needs to be optimized to be larger to handle large voltage standing wave ratios (VSWR) (e.g. 4). An optimized layout of the inductor with improved quality factor on the antenna side (where the impedance value can be large) will result in low losses. However, the losses presented are still competitive for an on-chip antenna tuner at 5 GHz.

[0045] Table 1

[0046] Impedance (Ω) Tuner loss (dB) Remark 10-j15.5 3 50 2.2 149-j27 3.7 Transformer losses are the limiting factor.

[0047] The linearity of the tuner is determined solely by the linearity of the switches used. For low-power applications with a maximum output power close to, for example, 0 dBm, only one switching device is used for each inductor winding tap and capacitor bank. Linearity simulations are tabulated in Table 2, primarily the third-order intercept point (IIP3) and input-referred compression point (ICP). Considering the use of only one switching device, the IIP3 and ICP values ​​are as expected. However, if higher linearity requirements are imposed, the IIP3 and ICP can be improved using the well-known technique of stacking switching devices in series. For example, eight switching devices can be used in series to improve the overall linearity.

[0048] Table 2

[0049]

[0050]

[0051] The impedance conversion circuits 100, 200, 300, 400, 500 according to the embodiments herein can be used in various integrated circuits, electronic circuits or devices, communication devices or apparatuses, and are particularly useful in, for example, full-duplex short-range communication transceivers. Figure 9A block diagram of a wireless communication device 900 is shown in which the impedance conversion circuits 100, 200, 300, 400, 500 according to embodiments of the present invention may be implemented. The wireless communication device includes an antenna 910, a transceiver 920, and the impedance conversion circuits 100, 200, 300, 400, 500 according to embodiments of the present invention. The wireless communication device 900 may include other units, including a memory 930 and a processing unit 940. The wireless communication device 900 may be a user equipment or mobile device for a cellular communication system. User equipment is a non-limiting term that refers to any terminal, wireless communication terminal, machine type communication (MTC) device, device-to-device (D2D) terminal or node, such as a smartphone, laptop, mobile phone, sensor, repeater, mobile tablet, or even a small base station communicating within a cell.

[0052] In summary, the impedance conversion circuits 100, 200, 300, 400, and 500 according to the embodiments herein are very compact and suitable for full integration. They also exhibit very low losses, making them attractive for fully integrated tuners. Therefore, the impedance conversion circuits 100, 200, 300, 400, and 500 according to the embodiments herein can be fully integrated on a chip. The structure of the impedance conversion circuits 100, 200, 300, 400, and 500 is based on a single-tap transformer, along with switches and programmable capacitors. The core of the tuner is a tapped transformer with multiple taps on two windings. By using switches to connect to different taps on either side of the transformer, the antenna impedance can be transformed upward or downward. Programmable capacitors are connected in parallel to the transformer windings on both sides. If these capacitors are set to resonate with the transformer's inductance at the operating frequency, the tuner converts between real-valued impedances. The conversion ratio can be programmed by selecting different taps to connect to the tuner port using the switches. If a conversion from a complex antenna impedance to a real-valued impedance is desired, the capacitors can be programmed to a value lower or higher than the resonant value. The impedance then moves along the circles on the Smith chart, sweeping through the capacitive and inductive half-fields. Sweeping the capacitance of different tap settings will produce non-overlapping arcs that overlap the area of ​​the Smith chart. This represents an unusually ordered matching domain and, therefore, enables simpler control of the impedance tuner. As a result, the matching domain is very regular, with only two primary parameters to control. This simplifies the control algorithm while still enabling a wide matching domain.

[0053] Those skilled in the art will understand that the impedance conversion circuits 100, 200, 300, 400, 500 according to the embodiments of this document can be implemented by any semiconductor technology, such as bipolar, N-type metal oxide semiconductor (NMOS), P-type metal oxide semiconductor (PMOS), complementary metal oxide semiconductor (CMOS), silicon on insulator (SOI) CMOS, fin field effect transistor (finFET), MOSFET or microelectromechanical system (MEMS) technology, etc.

[0054] When used herein, the word "comprising" or "including" is to be interpreted in a non-limiting sense, ie, meaning "consisting at least of.

[0055] The embodiments herein are not limited to the preferred embodiments described above. Various alternatives, modifications, and equivalents may be used. Therefore, the above embodiments should not be considered to limit the scope of the present invention, which is defined by the appended claims.

Claims

1. A circuit (100) for impedance conversion, comprising: a first port (P1) and a second port (P2); A tapped transformer (110) comprising a first winding (111) and a second winding (112); wherein the first winding (111) comprises a first terminal (T11), a second terminal (T12) and a plurality of taps (Tp11, Tp12...), the plurality of taps (Tp11, Tp12...) being connected at different positions on the first winding (111) between the first terminal and the second terminal; and The second winding (112) includes a first terminal (T21), a second terminal (T22), and a plurality of taps (Tp21, Tp22...), wherein the plurality of taps (Tp21, Tp22...) are connected at different positions on the second winding (112) between the first terminal and the second terminal; a first programmable capacitor (C1) connected between the first terminal and the second terminal of the first winding (111); a first set of switches (S1) connected between the plurality of taps on the first winding (111) and terminals of the first port (P1); a second programmable capacitor (C2) connected between the first terminal and the second terminal of the second winding (112); and a second set of switches (S2) connected between the plurality of taps on the second winding (112) and terminals of the second port (P2); and wherein, The circuit (100) is configured to transform the impedance between the first circuit (120) and the second circuit (130) by selectively connecting the first circuit (120) connected to the first port (P1) to one of the taps on the first winding (111) via the first set of switches (S1) and selectively connecting the second circuit (130) connected to the second port (P2) to one of the taps on the second winding (112) via the second set of switches (S2).

2. The circuit (100) of claim 1, further configured to select capacitances of the first and second programmable capacitors (C1, C2).

3. The circuit (100) according to any one of claims 1-2, configured as a single-ended antenna impedance tuner (200), wherein: Both the first port and the second port are single-ended ports, wherein one of the terminals (T12) on the first winding (111) and one of the terminals (T22) on the second winding (112) are connected to a signal ground, and the first port is to be connected to a transceiver having a single-ended port, and the second port is to be connected to a single-ended antenna port.

4. The circuit (100) according to any one of claims 1-2, configured as a differential to single-ended impedance tuner (300), wherein: The first port (P1) is a differential port (P1+, P1-), the second port (P2) is a single-ended port, and wherein the tap transformer (110) further includes a third winding (113) having a first terminal (T31), a second terminal (T32) and a plurality of taps and connected in series with the first winding (111), the differential-to-single-ended impedance tuner (300) further includes a third group of switches (S3) and a third programmable capacitor (C3) connected in parallel with the third winding (113), and the taps on the first winding are connected to the differential port (P1+) through the first group of switches (S1), and the taps on the third winding are connected to the differential port (P1-) through the third group of switches (S3).

5. The circuit (100) of claim 4, wherein: The first programmable capacitor (C1) and the third programmable capacitor (C3) are configured as one programmable capacitor and are connected between the first terminal (T11) of the first winding (111) and the first terminal (T31) of the third winding (113).

6. The circuit (100) according to any one of claims 1-2, configured as a single-ended to differential impedance tuner (400), wherein: The first port (P1) is a single-ended port, the second port (P2) is a differential port (P2+, P2-), and wherein the tap transformer (110) further includes a third winding (113) having a first terminal (T31), a second terminal (T32) and a plurality of taps and connected in series with the second winding (112), the single-ended to differential impedance tuner (400) further includes a third set of switches (S3) and a third programmable capacitor (C3) connected in parallel with the third winding (113), the taps on the second winding are connected to the differential port (P2+) through the second set of switches (S2), and the taps on the third winding are connected to the differential port (P2-) through the third set of switches (S3).

7. The circuit (100) of claim 6, wherein: The second programmable capacitor (C2) and the third programmable capacitor (C3) are configured as one programmable capacitor and are connected between the first terminal (T21) of the second winding (112) and the first terminal (T31) of the third winding (113).

8. The circuit (100) according to any one of claims 1-2, configured as a differential impedance tuner (500), wherein: The first port and the second port (P1, P2) are both differential ports (P1+, P1-, P2+, P2-), and wherein the tap transformer (110) further includes a third winding (113) having a plurality of taps and connected in series with the first winding (111), and a fourth winding (114) having a plurality of taps and connected in series with the second winding (112), and the differential impedance tuner (500) further includes a third group of switches (S3), a fourth group of switches (S4), a third programmable capacitor (C1) connected in parallel with the third winding (113), and a fourth capacitor (C2) connected in parallel with the third winding (113). 3) and a fourth programmable capacitor (C4) connected in parallel with the fourth winding (114), the tap on the first winding is connected to the first differential port (P1+) through the first group of switches (S1), the tap on the third winding is connected to the first differential port (P1-) through the third group of switches (S3), the tap on the second winding is connected to the second differential port (P2+) through the second group of switches (S2), and the tap on the fourth winding is connected to the second differential port (P2-) through the fourth group of switches (S4).

9. The circuit (100) of claim 8, wherein: The first programmable capacitor (C1) and the third programmable capacitor (C3) are configured as one programmable capacitor and are connected between the first terminal (T11) of the first winding (111) and the first terminal (T31) of the third winding (113); the second programmable capacitor (C2) and the fourth programmable capacitor (C4) are configured as one programmable capacitor and are connected between the first terminal (T21) of the second winding (112) and the first terminal (T41) of the fourth winding (114).

10. The circuit (100, 200, 300, 400, 500) according to any one of claims 1-2, 5, 7 and 9, said circuit being fully integrated on a chip.

11. A wireless communication device comprising the circuit according to any one of claims 1 to 10.

12. The wireless communication device of claim 11, wherein the wireless communication device is a user equipment.

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