Server and server backplane detection method based on multi-backplane cascading

Abstract

The invention discloses a server based on multi-backplane cascade and a server backplane detection method. The server comprises a mainboard and a plurality of backplanes. A main control system is arranged on the mainboard. The plurality of backplanes are sequentially connected in series to the same connection end of the main control system. The server also comprises an in-situ detection system. The in-situ detection system comprises at least one first detection resistor configured for each backplane, a detection signal line configured for the mainboard, and a detection signal source configured for the detection signal line. When the backplane is installed to the installation position, the first detection resistor on the backplane is electrically connected to the detection signal line, so that the signal strength loaded on the detection signal line by the detection signal source changes. The server of the invention adopts a cascaded backplane structure to configure the backplane on the mainboard. The main control system can judge the installation status of the backplane on the current mainboard by reading the signal strength change on the detection signal line, so as to facilitate the main control system to make corresponding adjustment measures for the backplane.

Description

Technical Field

[0001] The present invention relates to the technical field of server backplane control, and in particular to a server based on multi-backplane cascading and a server backplane detection method. Background Art

[0002] With the continuous development of information technology, at present, servers are generally equipped with multiple backplanes. The server backplane is a framework that supports the interconnection between the mainboard and storage in the server and provides power and data signal transmission for the supported mainboard. Today's server backplane configuration methods mainly include the following two forms: First, multiple connectors are set on the mainboard, each connector corresponds to a backplane, and the mainboard controller distinguishes the position of each backplane in the system according to the connection port, thereby accessing the corresponding backplane. For this form of backplane structure, although the control process is relatively simple, due to the setting of multiple connection ports, not only the port resources of the mainboard controller are wasted, but also the physical space of the mainboard is relatively large, and the cost is high. Second, multiple backplanes are cascaded, that is, each backplane is connected in series to the same connection port on the mainboard controller in turn, and a bus component with a configurable address is set on the backplane. The bus components on each backplane are configured to different addresses through the IIC bus, and the mainboard controller accesses the backplane according to the bus address configured for each backplane. For the cascaded backplane structure, although it can save the physical space of the mainboard, and the mainboard can also communicate with each backplane, the mainboard cannot recognize whether the backplane is inserted after the IIC configures the address. In this way, when the mainboard cannot read the physical address of one of the backplanes, it is not known whether it is caused by not importing the corresponding backplane or the inserted backplane firmware does not match the mainboard. Manual troubleshooting is required to solve the problem. Summary of the invention

[0003] The object of the present invention is to provide a server based on multi-backplane cascading and a server backplane detection method which can effectively confirm whether a backplane is installed in place.

[0004] In order to achieve the above-mentioned object, the present invention discloses a server based on multi-backplane cascade, characterized in that it includes a mainboard and a plurality of backplanes, the mainboard is provided with a main control system, the mainboard is also provided with a plurality of mounting positions for mounting the backplanes, the mounting positions are provided with interface circuits, and the plurality of interface circuits are sequentially connected in series to the same connection end of the main control system, the server also includes an in-situ detection system, the in-situ detection system includes at least one first detection resistor configured for each of the backplanes, a detection signal line configured for the mainboard, and a detection signal source configured for the detection signal line;

[0005] The detection signal line has contacts on the main control system and each of the installation positions. When the backplane is installed to the installation position, the first detection resistor on the backplane is electrically connected to the detection signal line so that the signal strength loaded onto the detection signal line by the detection signal source changes.

[0006] Preferably, the first detection resistor is a pull-down resistor, and at least one second detection resistor is also configured in the main control system. The detection signal line is connected in series from the signal port on the main control system to the interface circuit of each installation position in sequence, and the detection signal source includes a voltage source arranged on the main control system and electrically connected to the second detection resistor.

[0007] Preferably, the first detection resistor is a pull-down resistor, and the detection signal line includes a first signal line and a plurality of second signal lines independent of each other;

[0008] The first signal line is electrically connected between the signal port of the main control system and the first installation position connected to the main control system;

[0009] A plurality of the second signal lines are electrically connected between two adjacent mounting positions, respectively, and,

[0010] When the backplane is installed at any of the installation positions between the first and last positions, the first detection resistor on the backplane is electrically connected to the second signal line of the previous stage, and a signal port on the backplane is electrically connected to the second signal line of the next stage;

[0011] The detection signal source includes a plurality of voltage sources respectively arranged on the main control system and a plurality of the backplanes. The voltage source arranged on the main control system is electrically connected to the first signal line through at least one second detection resistor, and the voltage source arranged on the backplane not used for the final installation position is electrically connected to the second signal line of the subsequent stage through at least one third detection resistor.

[0012] Preferably, the main control system is connected to the plurality of backplanes via a serial bus communication, and the serial bus is used to transmit detection signals sent by signal ports on each of the backplanes.

[0013] Preferably, the main control system is further configured to send a characteristic signal with a certain frequency to the backplane located at the first position, and the characteristic signal is transmitted to the backplanes of other levels in sequence through the backplane;

[0014] Each of the backplanes is configured to: after receiving the characteristic signal, perform frequency conversion processing on the characteristic signal, and transmit the characteristic signal after the frequency conversion to the backplane of the next level, so that the frequencies of the characteristic signals received by the backplanes of each level are different from each other;

[0015] Each of the backplanes is also configured to configure a corresponding bus address based on the frequency of the characteristic signal received by itself.

[0016] The present invention also discloses a server backplane detection method based on multi-backplane cascade, wherein the server comprises a mainboard and a plurality of backplanes, the mainboard is provided with a main control system, the mainboard is also provided with a plurality of mounting positions for mounting the backplanes, the mounting positions are provided with interface circuits, and the plurality of interface circuits are sequentially connected in series to the same connection end of the main control system, and the detection method comprises an in-situ detection method for identifying the backplane on the mounting position:

[0017] Configuring at least one first detection resistor for each of the back plates;

[0018] A detection signal line is configured for the mainboard, and a detection signal source is configured for the detection signal line, the detection signal line has contacts on the main control system and each of the installation positions, and when the backplane is installed to the installation position, the first detection resistor on the backplane is electrically connected to the detection signal line, so that the signal strength loaded by the detection signal source on the detection signal line changes;

[0019] The main control system reads the signal strength on the detection signal line in real time to detect the installation status of the backplane.

[0020] Preferably, the first detection resistor is a pull-down resistor, and at least one second detection resistor is configured for the main control system, the detection signal line is sequentially connected in series from the signal port on the main control system to the interface circuit of each installation position, and the detection signal source includes a voltage source arranged on the main control system and electrically connected to the second detection resistor;

[0021] The main control system detects the installation status of the backplane by reading the voltage signal on the signal port in real time.

[0022] Preferably, the first detection resistor is a pull-down resistor, and the detection signal line includes a first signal line and a plurality of second signal lines independent of each other;

[0023] The first signal line is electrically connected between the signal port of the main control system and the first installation position connected to the main control system;

[0024] A plurality of the second signal lines are electrically connected between two adjacent mounting positions, respectively, and,

[0025] When the backplane is installed at any of the installation positions between the first and last positions, the first detection resistor on the backplane is electrically connected to the second signal line of the previous stage, and a signal port on the backplane is electrically connected to the second signal line of the next stage;

[0026] The detection signal source includes a plurality of voltage sources respectively arranged on the main control system and a plurality of the backplanes, the voltage source arranged on the main control system is electrically connected to the first signal line through at least one second detection resistor, and the voltage source arranged on the backplane not used for the last installation position is electrically connected to the second signal line of the subsequent stage through at least one third detection resistor;

[0027] The main control system detects the installation status of the backplane by reading the voltage signals of its own signal port and the signal ports of each installed backplane.

[0028] Preferably, the main control system is connected to the plurality of backplanes via a serial bus communication.

[0029] Preferably, the method further includes an address detection method:

[0030] The main control system sends a characteristic signal with a certain frequency to the backplane located at the first position, and the characteristic signal is transmitted to the backplanes of other levels in sequence through the backplane;

[0031] For each of the backplanes, after receiving the characteristic signal, the characteristic signal is subjected to frequency conversion processing, and the characteristic signal after the frequency conversion is transmitted to the backplane of the next level, so that the frequencies of the characteristic signals received by the backplanes of each level are different from each other;

[0032] Each of the backplanes configures a corresponding bus address based on the frequency of the characteristic signal received by itself;

[0033] The main control system reads the bus address of the backplane through the communication bus connected to the backplane.

[0034] Compared with the prior art, the technical solution of the present invention adopts a cascaded backplane structure to configure the backplane on the main board, thereby saving the physical space of the main board. At the same time, a detection signal line and a detection signal source are configured for the main control system of the main board, and a first detection resistor is configured for each backplane. When the backplane is inserted into the corresponding installation position on the main board, the first detection resistor on the main board is connected to the detection signal line through an interface circuit, thereby changing the impedance on the detection signal line, and then changing the signal loaded onto the detection signal line by the detection signal line. Therefore, the main control system can determine the installation status of the backplane on the current main board by reading the change in signal strength on the detection signal line, so as to facilitate the main control system to make corresponding adjustment measures to the backplane. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a schematic diagram of the server structure in one embodiment of the present invention.

[0036] Figure 2 for Figure 1 Detection principle circuit diagram of a backplane installed in the.

[0037] Figure 3 for Figure 1 Detection principle circuit diagram of installing two back panels.

[0038] Figure 4 for Figure 1 Detection principle circuit diagram of three backplanes installed in the system.

[0039] Figure 5 for Figure 1 Detection principle circuit diagram without backplane installed.

[0040] Figure 6 This is a schematic diagram of the server structure in another embodiment of the present invention. DETAILED DESCRIPTION

[0041] In order to explain the technical content, structural features, achieved objectives and effects of the present invention in detail, the following is a detailed description in conjunction with the implementation methods and the accompanying drawings.

[0042] like Figure 1 This embodiment discloses a server that provides computing or application services. The server includes a mainboard and a plurality of backplanes 20. A main control system 10 is arranged on the mainboard. The mainboard is also provided with a plurality of mounting positions (such as slots) for mounting the backplanes 20. The mounting positions are provided with interface circuits. When the backplanes 20 are inserted into the mounting positions, the backplanes 20 are electrically connected to the main control system 10 on the mainboard through the interface circuits. The plurality of interface circuits are sequentially connected in series to the same connection end of the main control system 10, so that the plurality of backplanes 20 installed on the mainboard are sequentially connected in series to the same connection end of the main control system 10, thereby forming a cascade configuration structure of the backplanes 20, saving interface resources for the main control system 10, and since the main control system 10 needs to be connected to the backplane 20 through a connector arranged at the connection end, the physical space occupied by the connector on the mainboard is saved, and the material cost is saved.

[0043] To facilitate the control of each backplane 20 by the main control system 10, the server in this embodiment is also provided with an in-situ detection system, which includes a detection signal line L, a detection signal source V0 and at least one first detection resistor R1, R2, R3 configured for each backplane 20, and the detection signal source V0 is used to provide the detection signal line L with a detection signal source with a certain strength.

[0044] The detection signal line L has contacts on the main control system 10 and each installation position (i.e., the interface circuit). When the backplane 20 is installed to the installation position, the first detection resistors R1, R2, and R3 on the backplane 20 are electrically connected to the detection signal line L, so that the signal strength loaded by the detection signal source V0 onto the detection signal line L changes.

[0045] Therefore, during the operation of the server, the main control system 10 can read the signal strength on the detection signal line L in real time, and can judge the position of the backplane 20 on the current mainboard through the change in signal strength, that is, how many backplanes 20 are correctly inserted, so as to facilitate the main control system 10 to make corresponding adjustments to the backplane 20. For example, if the main control system 10 cannot read the physical address of a certain backplane 20, but the backplane 20 is detected to be in place through the above-mentioned detection system, it is considered that the firmware of the backplane 20 is damaged or mismatched, and the main control system 10 can perform an online firmware refresh on the backplane 20 to automatically repair the current problem of the backplane 20. It should also be noted that the detection system in this embodiment defaults to installing the backplane 20 in order according to the level of the installation position.

[0046] Optionally, the main control system 10 includes a management controller 101 (BMC) and a main processor 100, and a slave processor 200 is arranged in the backplane 20. The main processor 100 and the slave processor 200 are both programmable devices, such as CPLD, GPLD and single-chip microcomputer, or other devices that can be programmed to process data and have a receiving data port and an output data port.

[0047] Specifically, a specific implementation mode of the detection system is as follows:

[0048] like Figure 1 , the first detection resistors R1, R2, and R3 configured in the backplane 20 are pull-down resistors, and at least one second detection resistor R0 is configured in the main control system 10. The detection signal line L is connected in series to the interface circuit of each installation position from the signal port (ADC) on the main control system 10 in sequence. The signal port in this embodiment is preferably an ADC pin, and the detection signal source V0 includes a voltage source V0 provided on the main control system 10 and electrically connected to the second detection resistor R0. In this embodiment, the ADC pin is located on the main processor 100. The ADC pin is an inherent pin of the chip and is an analog-to-digital conversion pin used for analog signal input. The main control system 10 detects the installation status of the backplane 20 by reading the voltage signal on the ADC pin in real time. Of course, the technology in this field can also select other pins on the main processor 100 as signal ports for receiving detection signals.

[0049] Specifically, the voltage source V0 used as the detection signal source V0 is provided by one of the ports of the main processor 100, and the voltage source V0 is 3.3 V. Since the main control system 10 has a second detection resistor R0 (pull-up resistor) and the backplane 20 has first detection resistors R1, R2, and R3 (pull-down resistors), when the backplane 20 is inserted into the mounting position on the mainboard, Figure 4, the second detection resistor R0 is connected in series with the first detection resistors R1, R2, and R3 to divide the voltage, so that the voltage signal of the ADC pin on the main processor 100 becomes smaller. When the server is equipped with three backplanes 20, the voltage signal detected by the ADC pin is divided into the following situations: 1. Figure 1 and Figure 2 , when the first backplane BP1 of the first stage (first level) is connected, the first detection resistor R1 on the backplane BP1 and the second detection resistor R0 on the main control system 10 are connected in series to divide the voltage, and the voltage division signal collected by the ADC pin from the collection point D0 of the detection signal line L is 3V; 2. Figure 1 and Figure 3 , when the second backplane BP2 is connected, the first detection resistors R1 and R2 of the first backplane BP1 and the second backplane BP2 are connected in parallel and then connected in series with the second detection resistor R0 for voltage division. The resistance value after parallel connection is reduced. Therefore, the voltage division signal collected by the ADC pin from the collection point D0 of the detection signal line L becomes 2.75V; 3. Figure 1 and Figure 4 When the third backplane BP3 is connected, the first detection resistors R1, R2, and R3 of the three backplanes BP1, BP2, and BP3 are connected in parallel and connected in series with the second detection resistor R0 for voltage division. The resistance value after parallel connection is further reduced, and the voltage division signal collected by the ADC pin from the collection point D0 of the detection signal line L becomes 2.58V; 4. Figure 1 and Figure 5 , when the three backplanes BP1, BP2, and BP3 are not plugged in, the voltage signal collected by the ADC pin from the collection point D0 of the detection signal line L is the voltage 3.3V of the voltage source V0. Similarly, the voltage signal of the ADC pin on the main processor 100 can be used to determine how many backplanes 20 are currently plugged in.

[0050] Specific implementation method 2 of the detection system:

[0051] like Figure 6 The first detection resistors R1, R2, and R3 configured in the backplane 20 are pull-down resistors. Different from the above-mentioned embodiment 1, in this embodiment, the detection signal line L is divided into multiple lines, namely, a first signal line L1 and a plurality of second signal lines L2 and L3 that are independent of each other.

[0052] The first signal line L1 is electrically connected between the signal port N0 of the main control system 10 and the first mounting position connected to the main control system 10. Through the first signal line L1, the main control system 10 can detect whether the first-level backplane BP1 connected thereto is inserted in place.

[0053] A plurality of second signal lines L2 and L3 are respectively electrically connected between two adjacent mounting positions, and when a backplane 20 (such as BP2) is installed at any mounting position between the first and last positions, a first detection resistor R2 on the backplane BP2 is electrically connected to the second signal line L2 of the previous stage, and a signal port N2 on the backplane BP2 is electrically connected to the second signal line L3 of the subsequent stage.

[0054] Correspondingly, in this embodiment, the detection signal source V0 also includes multiple voltage sources V0, which are respectively arranged on the main control system 10 and a plurality of backplanes 20, that is, a voltage source V0 used as a detection signal source is respectively arranged on the main control system 10 and each backplane 20. The voltage source V0 arranged on the main control system 10 is electrically connected to the first signal line L1 through at least one second detection resistor R0, and the voltage source V0 arranged on the backplane 20 (such as BP1, BP2) not used for the last installation position is electrically connected to the second signal lines L2, L3 of the subsequent stage through at least one third detection resistor R11, R22, that is, the voltage source VO on the backplane BP1 is electrically connected to the second signal line L2 through the third detection resistor R11, and the voltage source VO on the backplane BP2 is electrically connected to the third signal line L3 through the third detection resistor R22.

[0055] In this embodiment, when the server is working, the main control system 10 detects the installation status of the backplane 20 by reading the voltage signals of the signal port N0 of its own main processor 100 and the signal ports N1 and N2 of the slave processor 200 of each installed backplane 20. For example, the voltage source V0 configured for the main control system 10 and each backplane 20 is 3.3V. When the backplane BP1 is not inserted in the first-level installation position, the detection signal loaded by the voltage source V0 in the main control system 10 through the second detection resistor R0 to the signal port N0 of the main processor 100 is 3.3V. When the backplane BP1 is inserted in the first-level installation position, the first detection resistor R1 on the backplane BP1 is connected in series with the second detection resistor R0 to divide the voltage, and the voltage divided by the signal port N0 of the main processor 100 collected from the first signal line L1 is 3V.

[0056] When the first-stage backplane BP1 is installed in place, if the backplane BP2 is not inserted in the second-stage installation position, the voltage source V0 on the backplane BP1 is loaded to the voltage of the slave processing signal port N1 on the backplane BP1 through the third detection resistor R11 to be 3.3 V. When the backplane BP2 is inserted in place on the second-stage installation position, the first detection resistor R2 on the backplane BP2 is connected in series with the third detection resistor R11 on the backplane BP1 to form a voltage divider circuit, so that the voltage collected from the second signal line L2 by the slave processor 200 signal port N1 on the backplane BP1 is 3V.

[0057] Similarly, for the second-stage backplane BP2, if the backplane BP3 is not inserted in the third-stage installation position, the voltage source V0 on the backplane BP2 is loaded to the voltage of the slave processing signal port N2 on the backplane BP2 through the third detection resistor R22 to be 3.3 V. When the backplane BP3 is inserted into the third-stage installation position, the first detection resistor R3 on the backplane BP3 is connected in series with the third detection resistor R22 on the backplane BP2 to form a voltage divider circuit, so that the voltage collected from the second signal line L3 by the slave processor 200 signal port N2 on the backplane BP2 is 3V.

[0058] Therefore, the main control system 10 can confirm whether the first-level backplane BP1 is inserted in place by reading the voltage of its own signal port N0, and can confirm whether the third-level backplane BP3 is inserted in place by reading the voltage of the signal port N1 on the second-level backplane BP2. And so on. For more levels of backplanes 20, by reading the voltage of the signal ports of each in-place backplane 20, it can be confirmed whether there is a backplane 20 inserted in place at the next-level installation position.

[0059] In addition, in this embodiment, the main control system 10 is connected to the plurality of backplanes 20 via a serial bus communication. The serial bus in this embodiment is preferably an SGPIO bus connecting the main processor 100 and the slave processors 200 on each backplane 20, and the main processor 100 reads the detection signals of the signal ports N1 and N2 of the slave processors 200 on each backplane 20 via the SGPIO bus.

[0060] Furthermore, if Figure 1 Since the backplane 20 on the server disclosed above is a cascade structure, in order to facilitate the main control system 10 to read the address of each backplane 20 respectively for mutual communication, this embodiment also discloses an address detection system for detecting the backplane address. The technical solution of the address detection system is as follows:

[0061] When the server is working, the main control system 10 is configured to send a characteristic signal CLK with a certain frequency to the backplane 20 located at the first position (first level), and the characteristic signal CLK is transmitted to the backplanes 20 of other levels in the rear in sequence through the backplane 20;

[0062] For each backplane 20, after receiving the characteristic signal CLK, the characteristic signal CLK is subjected to frequency conversion processing, and the characteristic signal CLK after the frequency change is transmitted to the next level backplane 20, so that the frequencies of the characteristic signal CLK received by each level backplane 20 are different from each other;

[0063] Each backplane 20 configures a corresponding bus address based on the frequency of the characteristic signal CLK received by itself;

[0064] The main control system 10 reads the bus address of the backplane 20 via the communication bus (IIC) connected to the backplane 20 .

[0065] Optionally, after receiving the characteristic signal CLK, the main control system 10 and the backplane 20 uniformly convert the frequency of the received characteristic signal CLK by N times and send it to the next level backplane 20, where N>0. Taking N as 1 / 2 as an example, Figure 1 The management controller 101 in the main control system 10 is connected to the slave processors 200 on each backplane 20 through the IIC bus. The main control system 10 sends a characteristic signal CLK with a frequency of 256KHz to the slave processor C1 on the first-level backplane BP1 through the main processor 100. When the slave processor C1 of the first-level backplane BP1 receives the characteristic signal CLK (256KHz), it configures the bus address (0XE5) with a frequency of 256KHz, sends the bus address to the IIC bus, changes the frequency of the characteristic signal CLK to 128KHz, and then sends the characteristic signal CLK with a frequency of 128KHz to the second-level backplane BP2. After receiving the characteristic signal CLK with a frequency of 128KHz, the second-level backplane BP2 configures the bus address (0XE6) with a frequency of 128KHz, sends the bus address to the IIC bus, changes the frequency of the characteristic signal CLK to 64KHz, and then sends the characteristic signal CLK with a frequency of 64KHz to the third-level backplane BP3. The third backplane BP3 configures the bus address (0XE7) at a frequency of 64KHz and sends the bus address to the IIC bus. Therefore, the main control system 10 can obtain the bus address of each backplane 20 in place by reading the bus address information on the IIC bus through the management controller 101.

[0066] Optionally, the slave processor 200 on each backplane 20 stores the mapping relationship between the received characteristic signal CLK frequency and the level, and the mapping relationship between the level of each installation position and the bus address. For example, the received signal frequency is 256K, the corresponding backplane 20 is located at the first level, and the bus address corresponding to the first level backplane BP1 is OXE5. Other levels are analogous.

[0067] In addition, the mapping relationship between the received signal frequency and the bus address can be directly stored in the slave processor 200 of each level of backplane 20, and the bus address configuration of each backplane 20 can be directly performed based on the mapping relationship between the received signal frequency and the bus address. For example, the received signal frequency is 256K, and the bus address is configured as OXE5.

[0068] Furthermore, a FRU (Field Replace Unit) can be configured for each backplane 20. The FRU is connected to the address configuration pin of the slave processor 200 on the backplane 20, and each FRU is connected to the IIC bus. The slave processor 200 of each backplane 20 also configures the bus address of the FRU according to the received signal frequency.

[0069] In summary, if Figure 1 and Figure 6 The present invention discloses a server, which includes a mainboard and a plurality of backplanes 20 configured for the mainboard, wherein the backplanes 20 are arranged in cascade on the mainboard, so that only one connection plug-in needs to be arranged on one of the connection ports of the main control system 10 of the mainboard, thereby saving the physical space occupied by the mainboard. For the cascaded backplane 20 structure, in order to facilitate the communication between each backplane 20 and the main control system 10, the main control system 10 sends a characteristic signal CLK which is transmitted to each backplane 20 in sequence, wherein the frequency of the characteristic signal CLK received by each backplane 20 is different, each backplane 20 configures a corresponding bus address based on the frequency of the received characteristic signal CLK, and the main control system 10 reads the bus address of each backplane 20 from the IIC bus. In addition, a detection signal line L and a detection signal source V0 are arranged between the main control system 10 and each backplane 20. During the operation of the server, the main control system 10 also reads the signal strength of the detection signal source V0 on the detection signal line L through the SGPIO bus, thereby judging whether the backplane 20 of each level is in place. Therefore, for a server with the above functions, when the mainboard cannot read the backplane 20 at any level, if the backplane 20 can be detected in place through the detection signal line L, the main control system 10 can perform an online firmware refresh on the backplane 20 to automatically repair the current problems with the backplane 20.

[0070] The above disclosure is only the preferred embodiment of the present invention, which certainly cannot be used to limit the scope of rights of the present invention. Therefore, equivalent changes made according to the scope of the patent application of the present invention are still within the scope covered by the present invention.

Claims

1. A server based on multi-backplane cascading, characterized in that: The server comprises a mainboard and several backboards, wherein the mainboard is provided with a main control system, and the mainboard is also provided with several mounting positions for mounting the backboards, the mounting positions are provided with interface circuits, and the several interface circuits are sequentially connected in series to the same connection end of the main control system, the server further comprises an in-situ detection system, and the in-situ detection system comprises at least one first detection resistor configured for each of the backboards, a detection signal line configured for the mainboard, and a detection signal source configured for the detection signal line; The detection signal line has contacts on the main control system and each of the installation positions. When the backplane is installed at the installation position, the first detection resistor on the backplane is electrically connected to the detection signal line, so that the signal strength loaded by the detection signal source on the detection signal line changes; the first detection resistor is a pull-down resistor, and the detection signal line includes a first signal line and a plurality of second signal lines independent of each other; The first signal line is electrically connected between the signal port of the main control system and the first installation position connected to the main control system; A plurality of the second signal lines are electrically connected between two adjacent mounting positions, respectively, and, When the backplane is installed at any of the installation positions between the first and last positions, the first detection resistor on the backplane is electrically connected to the second signal line of the previous stage, and a signal port on the backplane is electrically connected to the second signal line of the next stage; The detection signal source includes a plurality of voltage sources respectively arranged on the main control system and several of the backplanes, the voltage source arranged on the main control system is electrically connected to the first signal line through at least one second detection resistor, and the voltage source arranged on the backplane not used for the final installation position is electrically connected to the second signal line of the subsequent stage through at least one third detection resistor; the main control system and several of the backplanes are connected through a serial bus communication, and the serial bus is used to transmit the detection signals emitted by the signal ports on each of the backplanes.

2. The server based on multi-backplane cascading according to claim 1, characterized in that: The first detection resistor is a pull-down resistor, and at least one second detection resistor is also configured in the main control system. The detection signal line is connected in series from the signal port on the main control system to the interface circuit of each installation position in sequence, and the detection signal source includes a voltage source arranged on the main control system and electrically connected to the second detection resistor.

3. The server based on multi-backplane cascading according to claim 1, characterized in that: The main control system is also configured to send a characteristic signal with a certain frequency to the backplane located at the first position, and the characteristic signal is transmitted to the backplanes of other levels in sequence through the backplane; Each of the backplanes is configured to: after receiving the characteristic signal, perform frequency conversion processing on the characteristic signal, and transmit the characteristic signal after the frequency conversion to the backplane of the next level, so that the frequencies of the characteristic signals received by the backplanes of each level are different from each other; Each of the backplanes is also configured to configure a corresponding bus address based on the frequency of the characteristic signal received by itself.

4. A server backplane detection method based on multi-backplane cascading, characterized in that: The server includes a mainboard and several backplanes, the mainboard is provided with a main control system, the mainboard is also provided with several mounting positions for mounting the backplanes, the mounting positions are provided with interface circuits, and the several interface circuits are sequentially connected in series to the same connection end of the main control system, and the detection method includes a detection method for identifying the presence of the backplane on the mounting position: Configuring at least one first detection resistor for each of the back plates; A detection signal line is configured for the mainboard, and a detection signal source is configured for the detection signal line, the detection signal line has contacts on the main control system and each of the installation positions, and when the backplane is installed to the installation position, the first detection resistor on the backplane is electrically connected to the detection signal line, so that the signal strength loaded by the detection signal source on the detection signal line changes; The main control system reads the signal strength on the detection signal line in real time to detect the installation status of the backplane; the first detection resistor is a pull-down resistor, and the detection signal line includes a first signal line and a plurality of second signal lines independent of each other; The first signal line is electrically connected between the signal port of the main control system and the first installation position connected to the main control system; A plurality of the second signal lines are electrically connected between two adjacent mounting positions, respectively, and, When the backplane is installed at any of the installation positions between the first and last positions, the first detection resistor on the backplane is electrically connected to the second signal line of the previous stage, and a signal port on the backplane is electrically connected to the second signal line of the next stage; The detection signal source includes a plurality of voltage sources respectively arranged on the main control system and a plurality of the backplanes, the voltage source arranged on the main control system is electrically connected to the first signal line through at least one second detection resistor, and the voltage source arranged on the backplane not used for the last installation position is electrically connected to the second signal line of the subsequent stage through at least one third detection resistor; The main control system detects the installation status of the backplane by reading the voltage signals of its own signal port and the signal ports of each installed backplane; the main control system is connected to the backplanes via a serial bus communication.

5. The server backplane detection method based on multi-backplane cascading according to claim 4 is characterized in that: The first detection resistor is a pull-down resistor, and at least one second detection resistor is configured for the main control system. The detection signal line is sequentially connected in series from the signal port on the main control system to the interface circuit of each installation position, and the detection signal source includes a voltage source arranged on the main control system and electrically connected to the second detection resistor; The main control system detects the installation status of the backplane by reading the voltage signal on the signal port in real time.

6. The server backplane detection method based on multi-backplane cascading according to claim 4 is characterized in that: Also includes address detection methods: The main control system sends a characteristic signal with a certain frequency to the backplane located at the first position, and the characteristic signal is transmitted to the backplanes of other levels in sequence through the backplane; For each of the backplanes, after receiving the characteristic signal, the characteristic signal is subjected to frequency conversion processing, and the characteristic signal after the frequency conversion is transmitted to the backplane of the next level, so that the frequencies of the characteristic signals received by the backplanes of each level are different from each other; Each of the backplanes configures a corresponding bus address based on the frequency of the characteristic signal received by itself; The main control system reads the bus address of the backplane through the communication bus connected to the backplane.

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