A read logic circuit based on magnetic tunnel junction

Abstract

The present invention discloses a magnetic tunnel junction (MTJ)-based read logic circuit, comprising magnetic tunnel junction devices MTJ1-MTJ2, inverting amplifiers I1-I2, PMOS transistors PM0-PM5, and NMOS transistors NM0-NM4. The read logic circuit comprises two phases: a precharge phase and a discharge phase. When the control signal clk is low, the read logic circuit enters the precharge phase; when the control signal clk is high, the logic circuit enters the discharge phase. The present invention separates the precharge and discharge branches, effectively reducing the read error rate. During the precharge phase, the voltages of nodes associated with the precharge voltage decrease, effectively reducing the circuit's power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a read logic circuit based on a magnetic tunnel junction. Background Art

[0002] With the recent scaling of integrated circuit manufacturing process nodes, leakage current caused by quantum tunneling has continued to increase, leading to a sharp increase in the static power consumption of logic circuits based on complementary metal oxide semiconductor technology. Furthermore, the structure that separates logic computing from data storage circuits is no longer suitable for processing massive amounts of data, and the dynamic power consumption required is also increasing exponentially. As a result, power consumption has gradually become one of the major factors hindering the scalability of traditional logic circuits and traditional computing systems.

[0003] Because magnetic tunnel junctions (MTJs) can effectively address power consumption issues, they have attracted widespread attention from both academia and industry. MTJs, due to their non-volatility, can be used in storage applications, and they can also be applied to logic circuits. However, existing read logic circuits are primarily designed based on precharge sense amplifiers (PCSAs). PCSA-based read logic circuits consist of two phases: a precharge phase and a discharge phase, both of which are controlled by a control signal (clk). When the read logic circuit enters the precharge phase, the charging node is charged to the power supply voltage. However, due to the high charging voltage, excessive read current can cause the MTJ device to flip, resulting in an increased read error rate and higher power consumption. Furthermore, because PCSA-based read logic circuits are controlled only by the control signal (clk), they cannot separate the precharge and discharge phases, potentially resulting in a higher read error rate. Summary of the Invention

[0004] The present invention aims to solve the problems of high read error rate and high power consumption of existing read logic circuits, and provides a read logic circuit based on a magnetic tunnel junction.

[0005] To solve the above problems, the present invention is achieved through the following technical solutions:

[0006] A read logic circuit based on a magnetic tunnel junction is composed of magnetic tunnel junction devices MTJ1-MTJ2, inverting amplifiers I1-I2, PMOS transistors PM0-PM5, and NMOS transistors NM0-NM4; the sources of the PMOS transistors PM0, PM2, PM3, and PM4, and the power supply terminals vdd of the inverting amplifiers I1 and I2 are simultaneously connected to the power supply voltage; the NMOS transistors NM2, NM3, and NMOS transistors are connected to the power supply voltage. The source of the transistor NM4 and the ground terminals gnd of the inverting amplifier I1 and the inverting amplifier I2 are grounded at the same time; the gates of the PMOS transistor PM1, the PMOS transistor PM5 and the NMOS transistor NM2 are connected to the control signal clk at the same time; the free ends T2 of the magnetic tunnel junction device MTJ1 and the magnetic tunnel junction device MTJ2 are connected to the drain of the NMOS transistor NM2; the fixed end T1 of the magnetic tunnel junction device MTJ1 is connected to the input terminal vi of the inverting amplifier I1 and the drain of the PMOS transistor PM3; the fixed end T2 of the magnetic tunnel junction device MTJ2 is connected to the input terminal vi of the inverting amplifier I1 and the drain of the PMOS transistor PM3; the fixed end T1 of the magnetic tunnel junction device MTJ2 ... The fixed terminal T1 is connected to the input terminal vi of the inverting amplifier I2 and the drain of the PMOS transistor PM4; the gate of the PMOS transistor PM3 is connected to the drain of the PMOS transistor PM5; the gate of the PMOS transistor PM4 is connected to the source of the PMOS transistor PM5; the output terminal vo of the inverting amplifier I1 is connected to the gate of the NMOS transistor NM3; the output terminal vo of the inverting amplifier I2 is connected to the gate of the NMOS transistor NM4; the drain of the NMOS transistor NM3 is connected to the source of the NMOS transistor NM0; the drain of the NMOS transistor NM4 is connected to the source of the NMOS transistor NM1; the drains of the PMOS transistor PM0 and the NMOS transistor NM0, the gates of the PMOS transistor PM2 and the NMOS transistor NM1, and the source of the PMOS transistor PM1 are connected to form a reverse output terminal a- of the read logic circuit; the drains of the PMOS transistor PM2 and the NMOS transistor NM1, the gates of the PMOS transistor PM0 and the NMOS transistor NM0, and the drain of the PMOS transistor PM1 are connected to form a forward output terminal a of the read logic circuit.

[0007] In the above solution, the magnetic tunnel junction devices MTJ1-MTJ2 are perpendicular magnetic anisotropy magnetic tunnel junction devices.

[0008] In the above scheme, the inverting amplifier is composed of a PMOS transistor PM and an NMOS transistor NM; the drain of the NMOS transistor NM forms the power supply terminal vdd of the inverting amplifier; the drain of the PMOS transistor PM forms the ground terminal gnd of the inverting amplifier; the source of the NMOS transistor NM and the source of the PMOS transistor PM are connected to form the output terminal vo of the inverting amplifier; the gate of the NMOS transistor NM and the gate of the PMOS transistor PM are connected to form the input terminal vi of the inverting amplifier.

[0009] Compared with the prior art, the present invention has the following characteristics:

[0010] 1. Separating the pre-charge circuit and the discharge branch effectively reduces the read error rate;

[0011] 2. In the pre-charging stage, the voltage of the nodes related to the pre-charging voltage becomes smaller, which effectively reduces the related power consumption of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a schematic diagram of the read logic circuit based on MTJ;

[0013] Figure 2 It is a schematic diagram of the MTJ device structure;

[0014] Figure 3 It is a schematic diagram of the inverting amplifier structure;

[0015] Figure 4 This is a schematic diagram of the simulation results of the MTJ-based read logic circuit. DETAILED DESCRIPTION

[0016] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to specific examples.

[0017] A read logic circuit based on a magnetic tunnel junction, such as Figure 1As shown, it mainly consists of magnetic tunnel junction devices MTJ1-MTJ2, inverting amplifiers I1-I2, PMOS transistors PM0-PM5, and NMOS transistors NM0-NM4. The sources of PMOS transistors PM0, PM2, PM3, and PM4, as well as the power supply terminal vdd of inverting amplifiers I1 and I2, are simultaneously connected to the power supply voltage; the sources of NMOS transistors NM2, NM3, and NM4, as well as the ground terminal gnd of inverting amplifiers I1 and I2, are simultaneously connected to ground; and the gates of PMOS transistors PM1, PM5, and NMOS transistor NM2 are simultaneously connected to the control signal clk. The free ends T2 of the magnetic tunnel junction device MTJ1 and the magnetic tunnel junction device MTJ2 are connected to the drain of the NMOS transistor NM2; the fixed end T1 of the magnetic tunnel junction device MTJ1 is connected to the input end vi of the inverting amplifier I1 and the drain of the PMOS transistor PM3; the fixed end T1 of the magnetic tunnel junction device MTJ2 is connected to the input end vi of the inverting amplifier I2 and the drain of the PMOS transistor PM4; the gate of the PMOS transistor PM3 is connected to the drain of the PMOS transistor PM5; and the gate of the PMOS transistor PM4 is connected to the source of the PMOS transistor PM5. The output terminal vo of the inverting amplifier I1 is connected to the gate of the NMOS transistor NM3; the output terminal vo of the inverting amplifier I2 is connected to the gate of the NMOS transistor NM4; the drain of the NMOS transistor NM3 is connected to the source of the NMOS transistor NM0; the drain of the NMOS transistor NM4 is connected to the source of the NMOS transistor NM1; the drains of the PMOS transistor PM0 and the NMOS transistor NM0, the gates of the PMOS transistor PM2 and the NMOS transistor NM1, and the source of the PMOS transistor PM1 are connected to form a reverse output terminal a- of the read logic circuit; the drains of the PMOS transistor PM2 and the NMOS transistor NM1, the gates of the PMOS transistor PM0 and the NMOS transistor NM0, and the drain of the PMOS transistor PM1 are connected to form a forward output terminal a of the read logic circuit.

[0018] See also Figure 2, a magnetic tunnel junction (MTJ) device consists of two ferromagnetic layers (CoFeB) and an oxide (MgO) insulating layer located between the two ferromagnetic layers. The intermediate insulating layer separates the two ferromagnetic layers, and the typical thickness of the insulating layer is only 1-2 nanometers, so that electrons can tunnel from one ferromagnetic layer to the other. In the standard application of MTJ devices, the direction of the magnetization intensity of one ferromagnetic layer is fixed, called the fixed layer, while the direction of the magnetization intensity of the other ferromagnetic layer can freely adopt two directions (parallel and antiparallel), called the free layer. Depending on the relative direction of the two ferromagnetic layers, the MTJ device can be divided into a parallel state or an antiparallel state, and the corresponding MTJ device shows low resistance (RP) or high resistance (RAP) characteristics. The resistance difference between the two states of the MTJ device is expressed by the tunnel magnetoresistance ratio, and the formula is as follows:

[0019] TMR=(RAP-RP) / RP

[0020] Where TMR is the tunnel magnetoresistance ratio, RAP is the resistance of the MTJ device in the antiparallel state, and RP is the resistance of the MTJ device in the parallel state.

[0021] Two input and output terminals are connected to the fixed terminal T1 of the MTJ device's fixed layer, and the free terminal T2 of the MTJ device's free layer. Switching between the parallel and antiparallel states is achieved by injecting current (usually higher than the critical switching current Ic0) into the MTJ device. The occurrence of the conversion depends on the direction, magnitude, and duration of the applied current. When the applied current is greater than the critical switching current or the duration is long enough, the MTJ device state may switch.

[0022] According to magnetic anisotropy, MTJ devices can be divided into perpendicular magnetic anisotropic magnetic tunnel junction devices (PMA-MTJ) and in-plane magnetic anisotropic magnetic tunnel junction devices (IMA-MTJ). The MTJ device used in the present invention is a PMA-MTJ.

[0023] See also Figure 3 The inverting amplifier consists of two CMOS transistors: a PMOS transistor PM and an NMOS transistor NM. The drain of the NMOS transistor NM forms the inverting amplifier's power supply terminal, vdd; the drain of the PMOS transistor PM forms the inverting amplifier's ground terminal, gnd. The source of the NMOS transistor NM is connected to the source of the PMOS transistor PM, forming the inverting amplifier's output terminal, vo; and the gate of the NMOS transistor NM is connected to the gate of the PMOS transistor PM, forming the inverting amplifier's input terminal, vi. The inverting amplifier amplifies the input signal in reverse, effectively controlling the turn-on and turn-off of transistors NM3 and NM4, ultimately achieving the circuit's corresponding function.

[0024] The above-mentioned read logic circuit based on MTJ device includes two stages: pre-charge stage and discharge stage:

[0025] When the control signal clk is low, the read logic circuit enters the precharge phase. At this point, the PM1 transistor is turned on, and the NM2 transistor is turned off. Unlike PCSA-based read logic circuits, due to the presence of the PM1 transistor, when the PM0 and PM2 transistors are turned on, the NM0 and NM1 transistors are in the off state. At this point, the voltages at the a and a- nodes are precharged to vdd-th, which is less than the power supply voltage. Similarly, when the control signal clk is low, the PM3, PM4, and PM5 transistors are turned on, causing the voltage at the top junction of the MTJ device to also be precharged to vdd-th. At this point, the inverting amplifier's input terminal vi is high, and the inverting amplifier's output terminal vo is low, with the NM3 and NM4 transistors in the off state. This separates the precharge and discharge circuits, preventing interference, effectively reducing the read error rate and the associated power consumption of the circuit.

[0026] When the control signal clk is high, the logic read circuit enters the discharge phase. At this point, the PM0, PM1, and PM2 transistors are off, while the NM0, NM1, NM3, and NM4 transistors are on. Nodes a and a- discharge. Similarly, the PM3, PM4, and PM5 transistors are also off, while the NM2 transistor is on. At this point, the connection points at the tops of the left and right MTJ devices begin to discharge, setting the two MTJ devices in opposite directions. Since the left MTJ1 device is parallel and the right MTJ2 device is antiparallel, the resistance of the left branch is relatively low, while the resistance of the right branch is relatively high. Therefore, the left branch discharges faster than the right branch. The voltage at the connection point at the top of the left MTJ1 device reaches the inverting amplifier input's threshold voltage first, and the output of the inverting amplifier is high. At this point, the NM3 transistor reaches the threshold voltage for the on-state before the NM4 transistor. Similarly, the left branch in the upper half discharges faster than the right branch. At this time, the a-end will be charged again and reach vdd-th, while the other end a will be discharged to "0". Finally, the corresponding readout node a-end outputs a high level and a end outputs a low level.

[0027] Figure 4This diagram shows the simulation results of a read logic circuit based on an MTJ. When the control signal clk is low, the read logic circuit precharges to vdd-th. When the control signal clk is high, the read logic circuit discharges, with one branch discharging to "0" and the other branch discharging for a period of time before charging to vdd-th. The circuit's charging and discharging process is very fast, significantly reducing the delay compared to existing logic read circuits, achieving almost instant switching.

[0028] It should be noted that although the embodiments of the present invention described above are illustrative, they are not intended to limit the present invention. Therefore, the present invention is not limited to the above-mentioned specific embodiments. Without departing from the principles of the present invention, any other embodiments obtained by those skilled in the art under the guidance of the present invention are deemed to be within the protection of the present invention.

Claims

1. A read logic circuit based on a magnetic tunnel junction, characterized in that: The invention is composed of magnetic tunnel junction devices MTJ1-MTJ2, inverting amplifiers I1-I2, PMOS transistors PM0-PM5, and NMOS transistors NM0-NM4; the magnetic tunnel junction devices MTJ1-MTJ2 are perpendicular magnetic anisotropy magnetic tunnel junction devices; the inverting amplifier is composed of a PMOS transistor PM and an NMOS transistor NM; the drain of the NMOS transistor NM forms the power supply terminal vdd of the inverting amplifier; the drain of the PMOS transistor PM forms the ground terminal gnd of the inverting amplifier; the source of the NMOS transistor NM is connected to the source of the PMOS transistor PM to form the output terminal vo of the inverting amplifier; the gate of the NMOS transistor NM is connected to the gate of the PMOS transistor PM to form the input terminal vi of the inverting amplifier; The sources of the PMOS transistors PM0, PM2, PM3, and PM4, and the power supply terminals vdd of the inverting amplifiers I1 and I2 are simultaneously connected to the power supply voltage; the sources of the NMOS transistors NM2, NM3, and NM4, and the ground terminals gnd of the inverting amplifiers I1 and I2 are simultaneously grounded; the gates of the PMOS transistors PM1, PM5, and NM2 are simultaneously connected to the control signal clk; The free ends T2 of the magnetic tunnel junction device MTJ1 and the magnetic tunnel junction device MTJ2 are connected to the drain of the NMOS transistor NM2; the fixed end T1 of the magnetic tunnel junction device MTJ1 is connected to the input end vi of the inverting amplifier I1 and the drain of the PMOS transistor PM3; the fixed end T1 of the magnetic tunnel junction device MTJ2 is connected to the input end vi of the inverting amplifier I2 and the drain of the PMOS transistor PM4; the gate of the PMOS transistor PM3 is connected to the drain of the PMOS transistor PM5; and the gate of the PMOS transistor PM4 is connected to the source of the PMOS transistor PM5. The output terminal vo of the inverting amplifier I1 is connected to the gate of the NMOS transistor NM3; the output terminal vo of the inverting amplifier I2 is connected to the gate of the NMOS transistor NM4; the drain of the NMOS transistor NM3 is connected to the source of the NMOS transistor NM0; the drain of the NMOS transistor NM4 is connected to the source of the NMOS transistor NM1; the drains of the PMOS transistor PM0 and the NMOS transistor NM0, the gates of the PMOS transistor PM2 and the NMOS transistor NM1, and the source of the PMOS transistor PM1 are connected to form a reverse output terminal a- of the read logic circuit; the drains of the PMOS transistor PM2 and the NMOS transistor NM1, the gates of the PMOS transistor PM0 and the NMOS transistor NM0, and the drain of the PMOS transistor PM1 are connected to form a forward output terminal a of the read logic circuit.

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